thread_context.hh revision 6022
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_CONTEXT_HH__ 32#define __CPU_THREAD_CONTEXT_HH__ 33 34#include "arch/regfile.hh" 35#include "arch/types.hh" 36#include "config/full_system.hh" 37#include "mem/request.hh" 38#include "sim/faults.hh" 39#include "sim/host.hh" 40#include "sim/serialize.hh" 41#include "sim/byteswap.hh" 42 43// @todo: Figure out a more architecture independent way to obtain the ITB and 44// DTB pointers. 45namespace TheISA 46{ 47 class TLB; 48} 49class BaseCPU; 50class EndQuiesceEvent; 51class Event; 52class TranslatingPort; 53class FunctionalPort; 54class VirtualPort; 55class Process; 56class System; 57namespace TheISA { 58 namespace Kernel { 59 class Statistics; 60 }; 61}; 62 63/** 64 * ThreadContext is the external interface to all thread state for 65 * anything outside of the CPU. It provides all accessor methods to 66 * state that might be needed by external objects, ranging from 67 * register values to things such as kernel stats. It is an abstract 68 * base class; the CPU can create its own ThreadContext by either 69 * deriving from it, or using the templated ProxyThreadContext. 70 * 71 * The ThreadContext is slightly different than the ExecContext. The 72 * ThreadContext provides access to an individual thread's state; an 73 * ExecContext provides ISA access to the CPU (meaning it is 74 * implicitly multithreaded on SMT systems). Additionally the 75 * ThreadState is an abstract class that exactly defines the 76 * interface; the ExecContext is a more implicit interface that must 77 * be implemented so that the ISA can access whatever state it needs. 78 */ 79class ThreadContext 80{ 81 protected: 82 typedef TheISA::RegFile RegFile; 83 typedef TheISA::MachInst MachInst; 84 typedef TheISA::IntReg IntReg; 85 typedef TheISA::FloatReg FloatReg; 86 typedef TheISA::FloatRegBits FloatRegBits; 87 typedef TheISA::MiscRegFile MiscRegFile; 88 typedef TheISA::MiscReg MiscReg; 89 public: 90 enum Status 91 { 92 /// Initialized but not running yet. All CPUs start in 93 /// this state, but most transition to Active on cycle 1. 94 /// In MP or SMT systems, non-primary contexts will stay 95 /// in this state until a thread is assigned to them. 96 Unallocated, 97 98 /// Running. Instructions should be executed only when 99 /// the context is in this state. 100 Active, 101 102 /// Temporarily inactive. Entered while waiting for 103 /// synchronization, etc. 104 Suspended, 105 106 /// Permanently shut down. Entered when target executes 107 /// m5exit pseudo-instruction. When all contexts enter 108 /// this state, the simulation will terminate. 109 Halted 110 }; 111 112 virtual ~ThreadContext() { }; 113 114 virtual BaseCPU *getCpuPtr() = 0; 115 116 virtual int cpuId() = 0; 117 118 virtual int threadId() = 0; 119 120 virtual void setThreadId(int id) = 0; 121 122 virtual int contextId() = 0; 123 124 virtual void setContextId(int id) = 0; 125 126 virtual TheISA::TLB *getITBPtr() = 0; 127 128 virtual TheISA::TLB *getDTBPtr() = 0; 129 130 virtual System *getSystemPtr() = 0; 131 132#if FULL_SYSTEM 133 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 134 135 virtual FunctionalPort *getPhysPort() = 0; 136 137 virtual VirtualPort *getVirtPort() = 0; 138 139 virtual void connectMemPorts(ThreadContext *tc) = 0; 140#else 141 virtual TranslatingPort *getMemPort() = 0; 142 143 virtual Process *getProcessPtr() = 0; 144#endif 145 146 virtual Status status() const = 0; 147 148 virtual void setStatus(Status new_status) = 0; 149 150 /// Set the status to Active. Optional delay indicates number of 151 /// cycles to wait before beginning execution. 152 virtual void activate(int delay = 1) = 0; 153 154 /// Set the status to Suspended. 155 virtual void suspend(int delay = 0) = 0; 156 157 /// Set the status to Unallocated. 158 virtual void deallocate(int delay = 0) = 0; 159 160 /// Set the status to Halted. 161 virtual void halt(int delay = 0) = 0; 162 163#if FULL_SYSTEM 164 virtual void dumpFuncProfile() = 0; 165#endif 166 167 virtual void takeOverFrom(ThreadContext *old_context) = 0; 168 169 virtual void regStats(const std::string &name) = 0; 170 171 virtual void serialize(std::ostream &os) = 0; 172 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 173 174#if FULL_SYSTEM 175 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 176 177 // Not necessarily the best location for these... 178 // Having an extra function just to read these is obnoxious 179 virtual Tick readLastActivate() = 0; 180 virtual Tick readLastSuspend() = 0; 181 182 virtual void profileClear() = 0; 183 virtual void profileSample() = 0; 184#endif 185 186 // Also somewhat obnoxious. Really only used for the TLB fault. 187 // However, may be quite useful in SPARC. 188 virtual TheISA::MachInst getInst() = 0; 189 190 virtual void copyArchRegs(ThreadContext *tc) = 0; 191 192 virtual void clearArchRegs() = 0; 193 194 // 195 // New accessors for new decoder. 196 // 197 virtual uint64_t readIntReg(int reg_idx) = 0; 198 199 virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 200 201 virtual FloatReg readFloatReg(int reg_idx) = 0; 202 203 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 204 205 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 206 207 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 208 209 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 210 211 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 212 213 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 214 215 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 216 217 virtual uint64_t readPC() = 0; 218 219 virtual void setPC(uint64_t val) = 0; 220 221 virtual uint64_t readNextPC() = 0; 222 223 virtual void setNextPC(uint64_t val) = 0; 224 225 virtual uint64_t readNextNPC() = 0; 226 227 virtual void setNextNPC(uint64_t val) = 0; 228 229 virtual uint64_t readMicroPC() = 0; 230 231 virtual void setMicroPC(uint64_t val) = 0; 232 233 virtual uint64_t readNextMicroPC() = 0; 234 235 virtual void setNextMicroPC(uint64_t val) = 0; 236 237 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 238 239 virtual MiscReg readMiscReg(int misc_reg) = 0; 240 241 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 242 243 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 244 245 virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; } 246 247 virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { }; 248 249 // Also not necessarily the best location for these two. Hopefully will go 250 // away once we decide upon where st cond failures goes. 251 virtual unsigned readStCondFailures() = 0; 252 253 virtual void setStCondFailures(unsigned sc_failures) = 0; 254 255 // Only really makes sense for old CPU model. Still could be useful though. 256 virtual bool misspeculating() = 0; 257 258#if !FULL_SYSTEM 259 // Same with st cond failures. 260 virtual Counter readFuncExeInst() = 0; 261 262 virtual void syscall(int64_t callnum) = 0; 263 264 // This function exits the thread context in the CPU and returns 265 // 1 if the CPU has no more active threads (meaning it's OK to exit); 266 // Used in syscall-emulation mode when a thread calls the exit syscall. 267 virtual int exit() { return 1; }; 268#endif 269 270 /** function to compare two thread contexts (for debugging) */ 271 static void compare(ThreadContext *one, ThreadContext *two); 272}; 273 274/** 275 * ProxyThreadContext class that provides a way to implement a 276 * ThreadContext without having to derive from it. ThreadContext is an 277 * abstract class, so anything that derives from it and uses its 278 * interface will pay the overhead of virtual function calls. This 279 * class is created to enable a user-defined Thread object to be used 280 * wherever ThreadContexts are used, without paying the overhead of 281 * virtual function calls when it is used by itself. See 282 * simple_thread.hh for an example of this. 283 */ 284template <class TC> 285class ProxyThreadContext : public ThreadContext 286{ 287 public: 288 ProxyThreadContext(TC *actual_tc) 289 { actualTC = actual_tc; } 290 291 private: 292 TC *actualTC; 293 294 public: 295 296 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 297 298 int cpuId() { return actualTC->cpuId(); } 299 300 int threadId() { return actualTC->threadId(); } 301 302 void setThreadId(int id) { return actualTC->setThreadId(id); } 303 304 int contextId() { return actualTC->contextId(); } 305 306 void setContextId(int id) { actualTC->setContextId(id); } 307 308 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 309 310 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 311 312 System *getSystemPtr() { return actualTC->getSystemPtr(); } 313 314#if FULL_SYSTEM 315 TheISA::Kernel::Statistics *getKernelStats() 316 { return actualTC->getKernelStats(); } 317 318 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 319 320 VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } 321 322 void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); } 323#else 324 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 325 326 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 327#endif 328 329 Status status() const { return actualTC->status(); } 330 331 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 332 333 /// Set the status to Active. Optional delay indicates number of 334 /// cycles to wait before beginning execution. 335 void activate(int delay = 1) { actualTC->activate(delay); } 336 337 /// Set the status to Suspended. 338 void suspend(int delay = 0) { actualTC->suspend(); } 339 340 /// Set the status to Unallocated. 341 void deallocate(int delay = 0) { actualTC->deallocate(); } 342 343 /// Set the status to Halted. 344 void halt(int delay = 0) { actualTC->halt(); } 345 346#if FULL_SYSTEM 347 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 348#endif 349 350 void takeOverFrom(ThreadContext *oldContext) 351 { actualTC->takeOverFrom(oldContext); } 352 353 void regStats(const std::string &name) { actualTC->regStats(name); } 354 355 void serialize(std::ostream &os) { actualTC->serialize(os); } 356 void unserialize(Checkpoint *cp, const std::string §ion) 357 { actualTC->unserialize(cp, section); } 358 359#if FULL_SYSTEM 360 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 361 362 Tick readLastActivate() { return actualTC->readLastActivate(); } 363 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 364 365 void profileClear() { return actualTC->profileClear(); } 366 void profileSample() { return actualTC->profileSample(); } 367#endif 368 // @todo: Do I need this? 369 MachInst getInst() { return actualTC->getInst(); } 370 371 // @todo: Do I need this? 372 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 373 374 void clearArchRegs() { actualTC->clearArchRegs(); } 375 376 // 377 // New accessors for new decoder. 378 // 379 uint64_t readIntReg(int reg_idx) 380 { return actualTC->readIntReg(reg_idx); } 381 382 FloatReg readFloatReg(int reg_idx, int width) 383 { return actualTC->readFloatReg(reg_idx, width); } 384 385 FloatReg readFloatReg(int reg_idx) 386 { return actualTC->readFloatReg(reg_idx); } 387 388 FloatRegBits readFloatRegBits(int reg_idx, int width) 389 { return actualTC->readFloatRegBits(reg_idx, width); } 390 391 FloatRegBits readFloatRegBits(int reg_idx) 392 { return actualTC->readFloatRegBits(reg_idx); } 393 394 void setIntReg(int reg_idx, uint64_t val) 395 { actualTC->setIntReg(reg_idx, val); } 396 397 void setFloatReg(int reg_idx, FloatReg val, int width) 398 { actualTC->setFloatReg(reg_idx, val, width); } 399 400 void setFloatReg(int reg_idx, FloatReg val) 401 { actualTC->setFloatReg(reg_idx, val); } 402 403 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 404 { actualTC->setFloatRegBits(reg_idx, val, width); } 405 406 void setFloatRegBits(int reg_idx, FloatRegBits val) 407 { actualTC->setFloatRegBits(reg_idx, val); } 408 409 uint64_t readPC() { return actualTC->readPC(); } 410 411 void setPC(uint64_t val) { actualTC->setPC(val); } 412 413 uint64_t readNextPC() { return actualTC->readNextPC(); } 414 415 void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 416 417 uint64_t readNextNPC() { return actualTC->readNextNPC(); } 418 419 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 420 421 uint64_t readMicroPC() { return actualTC->readMicroPC(); } 422 423 void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); } 424 425 uint64_t readNextMicroPC() { return actualTC->readMicroPC(); } 426 427 void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); } 428 429 MiscReg readMiscRegNoEffect(int misc_reg) 430 { return actualTC->readMiscRegNoEffect(misc_reg); } 431 432 MiscReg readMiscReg(int misc_reg) 433 { return actualTC->readMiscReg(misc_reg); } 434 435 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 436 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 437 438 void setMiscReg(int misc_reg, const MiscReg &val) 439 { return actualTC->setMiscReg(misc_reg, val); } 440 441 unsigned readStCondFailures() 442 { return actualTC->readStCondFailures(); } 443 444 void setStCondFailures(unsigned sc_failures) 445 { actualTC->setStCondFailures(sc_failures); } 446 447 // @todo: Fix this! 448 bool misspeculating() { return actualTC->misspeculating(); } 449 450#if !FULL_SYSTEM 451 void syscall(int64_t callnum) 452 { actualTC->syscall(callnum); } 453 454 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 455#endif 456}; 457 458#endif 459