thread_context.hh revision 13905
12SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Kevin Lim 422SN/A */ 432SN/A 442680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 452680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 462SN/A 478229Snate@binkert.org#include <iostream> 487680Sgblack@eecs.umich.edu#include <string> 497680Sgblack@eecs.umich.edu 506329Sgblack@eecs.umich.edu#include "arch/registers.hh" 513453Sgblack@eecs.umich.edu#include "arch/types.hh" 526216Snate@binkert.org#include "base/types.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 5412104Snathanael.premillieu@arm.com#include "cpu/reg_class.hh" 552SN/A 562190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 572190SN/A// DTB pointers. 583453Sgblack@eecs.umich.edunamespace TheISA 593453Sgblack@eecs.umich.edu{ 6013693Sgiacomo.gabrielli@arm.com class ISA; 619020Sgblack@eecs.umich.edu class Decoder; 623453Sgblack@eecs.umich.edu} 632190SN/Aclass BaseCPU; 6412406Sgabeblack@google.comclass BaseTLB; 658887Sgeoffrey.blake@arm.comclass CheckerCPU; 667680Sgblack@eecs.umich.educlass Checkpoint; 672313SN/Aclass EndQuiesceEvent; 688706Sandreas.hansson@arm.comclass SETranslatingPortProxy; 698706Sandreas.hansson@arm.comclass FSTranslatingPortProxy; 708706Sandreas.hansson@arm.comclass PortProxy; 712190SN/Aclass Process; 722190SN/Aclass System; 7313905Sgabeblack@google.comnamespace Kernel { 7413905Sgabeblack@google.com class Statistics; 758902Sandreas.hansson@arm.com} 762SN/A 772680Sktlim@umich.edu/** 782680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 792680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 802680Sktlim@umich.edu * state that might be needed by external objects, ranging from 812680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 8213865Sgabeblack@google.com * base class; the CPU can create its own ThreadContext by 8313865Sgabeblack@google.com * deriving from it. 842680Sktlim@umich.edu * 852680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 862680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 872680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 882682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 892680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 902680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 912680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 922680Sktlim@umich.edu */ 932680Sktlim@umich.educlass ThreadContext 942SN/A{ 952107SN/A protected: 962107SN/A typedef TheISA::MachInst MachInst; 9712109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 9812109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 9913610Sgiacomo.gabrielli@arm.com using VecPredRegContainer = TheISA::VecPredRegContainer; 10013610Sgiacomo.gabrielli@arm.com 1012SN/A public: 1026029Ssteve.reinhardt@amd.com 103246SN/A enum Status 104246SN/A { 105246SN/A /// Running. Instructions should be executed only when 106246SN/A /// the context is in this state. 107246SN/A Active, 108246SN/A 109246SN/A /// Temporarily inactive. Entered while waiting for 1102190SN/A /// synchronization, etc. 111246SN/A Suspended, 112246SN/A 11313641Sqtt2@cornell.edu /// Trying to exit and waiting for an event to completely exit. 11413641Sqtt2@cornell.edu /// Entered when target executes an exit syscall. 11513641Sqtt2@cornell.edu Halting, 11613641Sqtt2@cornell.edu 117246SN/A /// Permanently shut down. Entered when target executes 118246SN/A /// m5exit pseudo-instruction. When all contexts enter 119246SN/A /// this state, the simulation will terminate. 120246SN/A Halted 121246SN/A }; 1222SN/A 1232680Sktlim@umich.edu virtual ~ThreadContext() { }; 1242423SN/A 1252190SN/A virtual BaseCPU *getCpuPtr() = 0; 126180SN/A 12710110Sandreas.hansson@arm.com virtual int cpuId() const = 0; 1282190SN/A 12910190Sakash.bagdia@arm.com virtual uint32_t socketId() const = 0; 13010190Sakash.bagdia@arm.com 13110110Sandreas.hansson@arm.com virtual int threadId() const = 0; 1325715Shsul@eecs.umich.edu 1335715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1345714Shsul@eecs.umich.edu 13513865Sgabeblack@google.com virtual ContextID contextId() const = 0; 1365714Shsul@eecs.umich.edu 13713865Sgabeblack@google.com virtual void setContextId(ContextID id) = 0; 1385714Shsul@eecs.umich.edu 13912406Sgabeblack@google.com virtual BaseTLB *getITBPtr() = 0; 1402190SN/A 14112406Sgabeblack@google.com virtual BaseTLB *getDTBPtr() = 0; 1422521SN/A 1438887Sgeoffrey.blake@arm.com virtual CheckerCPU *getCheckerCpuPtr() = 0; 1448733Sgeoffrey.blake@arm.com 14513693Sgiacomo.gabrielli@arm.com virtual TheISA::ISA *getIsaPtr() = 0; 14613693Sgiacomo.gabrielli@arm.com 1479020Sgblack@eecs.umich.edu virtual TheISA::Decoder *getDecoderPtr() = 0; 1488541Sgblack@eecs.umich.edu 1494997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1504997Sgblack@eecs.umich.edu 15113905Sgabeblack@google.com virtual ::Kernel::Statistics *getKernelStats() = 0; 1522654SN/A 1538852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() = 0; 1542521SN/A 1558852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy() = 0; 1563673Srdreslin@umich.edu 1578706Sandreas.hansson@arm.com /** 1588706Sandreas.hansson@arm.com * Initialise the physical and virtual port proxies and tie them to 1598706Sandreas.hansson@arm.com * the data port of the CPU. 1608706Sandreas.hansson@arm.com * 1618706Sandreas.hansson@arm.com * tc ThreadContext for the virtual-to-physical translation 1628706Sandreas.hansson@arm.com */ 1638706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) = 0; 1648799Sgblack@eecs.umich.edu 1658852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() = 0; 1662518SN/A 1672190SN/A virtual Process *getProcessPtr() = 0; 1682190SN/A 16911886Sbrandon.potter@amd.com virtual void setProcessPtr(Process *p) = 0; 17011886Sbrandon.potter@amd.com 1712190SN/A virtual Status status() const = 0; 1722159SN/A 1732235SN/A virtual void setStatus(Status new_status) = 0; 1742103SN/A 17510407Smitch.hayenga@arm.com /// Set the status to Active. 17610407Smitch.hayenga@arm.com virtual void activate() = 0; 177393SN/A 178393SN/A /// Set the status to Suspended. 17910407Smitch.hayenga@arm.com virtual void suspend() = 0; 180393SN/A 181393SN/A /// Set the status to Halted. 18210407Smitch.hayenga@arm.com virtual void halt() = 0; 1832159SN/A 18411627Smichael.lebeane@amd.com /// Quiesce thread context 18511627Smichael.lebeane@amd.com void quiesce(); 18611627Smichael.lebeane@amd.com 18711627Smichael.lebeane@amd.com /// Quiesce, suspend, and schedule activate at resume 18811627Smichael.lebeane@amd.com void quiesceTick(Tick resume); 18911627Smichael.lebeane@amd.com 1902190SN/A virtual void dumpFuncProfile() = 0; 1912159SN/A 1922680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1932159SN/A 1942190SN/A virtual void regStats(const std::string &name) = 0; 1952159SN/A 1962313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1972235SN/A 1982235SN/A // Not necessarily the best location for these... 1992235SN/A // Having an extra function just to read these is obnoxious 2002235SN/A virtual Tick readLastActivate() = 0; 2012235SN/A virtual Tick readLastSuspend() = 0; 2022254SN/A 2032254SN/A virtual void profileClear() = 0; 2042254SN/A virtual void profileSample() = 0; 2052235SN/A 2062680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 2072159SN/A 2082190SN/A virtual void clearArchRegs() = 0; 2092159SN/A 2102159SN/A // 2112159SN/A // New accessors for new decoder. 2122159SN/A // 21313865Sgabeblack@google.com virtual RegVal readIntReg(RegIndex reg_idx) const = 0; 2142159SN/A 21513865Sgabeblack@google.com virtual RegVal readFloatReg(RegIndex reg_idx) const = 0; 2162159SN/A 21712109SRekai.GonzalezAlberquilla@arm.com virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0; 21812109SRekai.GonzalezAlberquilla@arm.com virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0; 21912109SRekai.GonzalezAlberquilla@arm.com 22012109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 22112109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 22212109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 22312109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 22412109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const = 0; 22512109SRekai.GonzalezAlberquilla@arm.com 22612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 22712109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 22812109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const = 0; 22912109SRekai.GonzalezAlberquilla@arm.com 23012109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 23112109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 23212109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const = 0; 23312109SRekai.GonzalezAlberquilla@arm.com 23412109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 23512109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 23612109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const = 0; 23712109SRekai.GonzalezAlberquilla@arm.com 23812109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 23912109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24012109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) = 0; 24112109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24212109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) = 0; 24312109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24412109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) = 0; 24512109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24612109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) = 0; 24712109SRekai.GonzalezAlberquilla@arm.com /** @} */ 24812109SRekai.GonzalezAlberquilla@arm.com 24912109SRekai.GonzalezAlberquilla@arm.com virtual const VecElem& readVecElem(const RegId& reg) const = 0; 25012109SRekai.GonzalezAlberquilla@arm.com 25113610Sgiacomo.gabrielli@arm.com virtual const VecPredRegContainer& readVecPredReg(const RegId& reg) 25213610Sgiacomo.gabrielli@arm.com const = 0; 25313610Sgiacomo.gabrielli@arm.com virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0; 25413610Sgiacomo.gabrielli@arm.com 25513865Sgabeblack@google.com virtual RegVal readCCReg(RegIndex reg_idx) const = 0; 2569920Syasuko.eckert@amd.com 25713865Sgabeblack@google.com virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0; 2582159SN/A 25913865Sgabeblack@google.com virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0; 2602455SN/A 26112109SRekai.GonzalezAlberquilla@arm.com virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0; 26212109SRekai.GonzalezAlberquilla@arm.com 26312109SRekai.GonzalezAlberquilla@arm.com virtual void setVecElem(const RegId& reg, const VecElem& val) = 0; 26412109SRekai.GonzalezAlberquilla@arm.com 26513610Sgiacomo.gabrielli@arm.com virtual void setVecPredReg(const RegId& reg, 26613610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) = 0; 26713610Sgiacomo.gabrielli@arm.com 26813865Sgabeblack@google.com virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0; 2699920Syasuko.eckert@amd.com 27013865Sgabeblack@google.com virtual TheISA::PCState pcState() const = 0; 2712159SN/A 2727720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2732159SN/A 27411886Sbrandon.potter@amd.com void 27511886Sbrandon.potter@amd.com setNPC(Addr val) 27611886Sbrandon.potter@amd.com { 27711886Sbrandon.potter@amd.com TheISA::PCState pc_state = pcState(); 27811886Sbrandon.potter@amd.com pc_state.setNPC(val); 27911886Sbrandon.potter@amd.com pcState(pc_state); 28011886Sbrandon.potter@amd.com } 28111886Sbrandon.potter@amd.com 2828733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 2838733Sgeoffrey.blake@arm.com 28413865Sgabeblack@google.com virtual Addr instAddr() const = 0; 2852159SN/A 28613865Sgabeblack@google.com virtual Addr nextInstAddr() const = 0; 2872159SN/A 28813865Sgabeblack@google.com virtual MicroPC microPC() const = 0; 2895260Sksewell@umich.edu 29013865Sgabeblack@google.com virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0; 2914172Ssaidi@eecs.umich.edu 29213865Sgabeblack@google.com virtual RegVal readMiscReg(RegIndex misc_reg) = 0; 2932159SN/A 29413865Sgabeblack@google.com virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0; 2952190SN/A 29613865Sgabeblack@google.com virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0; 2972190SN/A 29812106SRekai.GonzalezAlberquilla@arm.com virtual RegId flattenRegId(const RegId& regId) const = 0; 2996313Sgblack@eecs.umich.edu 3002235SN/A // Also not necessarily the best location for these two. Hopefully will go 3012235SN/A // away once we decide upon where st cond failures goes. 30213865Sgabeblack@google.com virtual unsigned readStCondFailures() const = 0; 3032190SN/A 3042190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 3052159SN/A 3062235SN/A // Same with st cond failures. 30713865Sgabeblack@google.com virtual Counter readFuncExeInst() const = 0; 3082834Sksewell@umich.edu 30911877Sbrandon.potter@amd.com virtual void syscall(int64_t callnum, Fault *fault) = 0; 3104111Sgblack@eecs.umich.edu 3112834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 3122834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 3132834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 3142834Sksewell@umich.edu virtual int exit() { return 1; }; 3152525SN/A 3165217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 3175217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 3189426SAndreas.Sandberg@ARM.com 3199426SAndreas.Sandberg@ARM.com /** @{ */ 3209426SAndreas.Sandberg@ARM.com /** 3219426SAndreas.Sandberg@ARM.com * Flat register interfaces 3229426SAndreas.Sandberg@ARM.com * 3239426SAndreas.Sandberg@ARM.com * Some architectures have different registers visible in 3249426SAndreas.Sandberg@ARM.com * different modes. Such architectures "flatten" a register (see 32512106SRekai.GonzalezAlberquilla@arm.com * flattenRegId()) to map it into the 3269426SAndreas.Sandberg@ARM.com * gem5 register file. This interface provides a flat interface to 3279426SAndreas.Sandberg@ARM.com * the underlying register file, which allows for example 3289426SAndreas.Sandberg@ARM.com * serialization code to access all registers. 3299426SAndreas.Sandberg@ARM.com */ 3309426SAndreas.Sandberg@ARM.com 33113865Sgabeblack@google.com virtual RegVal readIntRegFlat(RegIndex idx) const = 0; 33213865Sgabeblack@google.com virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0; 3339426SAndreas.Sandberg@ARM.com 33413865Sgabeblack@google.com virtual RegVal readFloatRegFlat(RegIndex idx) const = 0; 33513865Sgabeblack@google.com virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0; 3369426SAndreas.Sandberg@ARM.com 33713865Sgabeblack@google.com virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0; 33813865Sgabeblack@google.com virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0; 33913865Sgabeblack@google.com virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0; 34012109SRekai.GonzalezAlberquilla@arm.com 34113865Sgabeblack@google.com virtual const VecElem& readVecElemFlat(RegIndex idx, 34212109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIdx) const = 0; 34313865Sgabeblack@google.com virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx, 34412109SRekai.GonzalezAlberquilla@arm.com const VecElem& val) = 0; 34512109SRekai.GonzalezAlberquilla@arm.com 34613865Sgabeblack@google.com virtual const VecPredRegContainer & 34713865Sgabeblack@google.com readVecPredRegFlat(RegIndex idx) const = 0; 34813865Sgabeblack@google.com virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0; 34913865Sgabeblack@google.com virtual void setVecPredRegFlat(RegIndex idx, 35013610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) = 0; 35113610Sgiacomo.gabrielli@arm.com 35213865Sgabeblack@google.com virtual RegVal readCCRegFlat(RegIndex idx) const = 0; 35313865Sgabeblack@google.com virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0; 3549426SAndreas.Sandberg@ARM.com /** @} */ 3559426SAndreas.Sandberg@ARM.com 3562159SN/A}; 3572159SN/A 3589428SAndreas.Sandberg@ARM.com/** @{ */ 3599428SAndreas.Sandberg@ARM.com/** 3609428SAndreas.Sandberg@ARM.com * Thread context serialization helpers 3619428SAndreas.Sandberg@ARM.com * 3629428SAndreas.Sandberg@ARM.com * These helper functions provide a way to the data in a 3639428SAndreas.Sandberg@ARM.com * ThreadContext. They are provided as separate helper function since 3649428SAndreas.Sandberg@ARM.com * implementing them as members of the ThreadContext interface would 3659428SAndreas.Sandberg@ARM.com * be confusing when the ThreadContext is exported via a proxy. 3669428SAndreas.Sandberg@ARM.com */ 3679428SAndreas.Sandberg@ARM.com 36813865Sgabeblack@google.comvoid serialize(const ThreadContext &tc, CheckpointOut &cp); 36910905Sandreas.sandberg@arm.comvoid unserialize(ThreadContext &tc, CheckpointIn &cp); 3709428SAndreas.Sandberg@ARM.com 3719428SAndreas.Sandberg@ARM.com/** @} */ 3729428SAndreas.Sandberg@ARM.com 3739441SAndreas.Sandberg@ARM.com 3749441SAndreas.Sandberg@ARM.com/** 3759441SAndreas.Sandberg@ARM.com * Copy state between thread contexts in preparation for CPU handover. 3769441SAndreas.Sandberg@ARM.com * 3779441SAndreas.Sandberg@ARM.com * @note This method modifies the old thread contexts as well as the 3789441SAndreas.Sandberg@ARM.com * new thread context. The old thread context will have its quiesce 3799441SAndreas.Sandberg@ARM.com * event descheduled if it is scheduled and its status set to halted. 3809441SAndreas.Sandberg@ARM.com * 3819441SAndreas.Sandberg@ARM.com * @param new_tc Destination ThreadContext. 3829441SAndreas.Sandberg@ARM.com * @param old_tc Source ThreadContext. 3839441SAndreas.Sandberg@ARM.com */ 3849441SAndreas.Sandberg@ARM.comvoid takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 3859441SAndreas.Sandberg@ARM.com 3862190SN/A#endif 387