thread_context.hh revision 10110
1360SN/A/* 21458SN/A * Copyright (c) 2011-2012 ARM Limited 3360SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 4360SN/A * All rights reserved 5360SN/A * 6360SN/A * The license below extends only to copyright in the software and shall 7360SN/A * not be construed as granting a license to any other intellectual 8360SN/A * property including but not limited to intellectual property relating 9360SN/A * to a hardware implementation of the functionality of the software 10360SN/A * licensed hereunder. You may use the software subject to the license 11360SN/A * terms below provided that you ensure that this notice is replicated 12360SN/A * unmodified and in its entirety in all distributions of the software, 13360SN/A * modified or unmodified, in source code or in binary form. 14360SN/A * 15360SN/A * Copyright (c) 2006 The Regents of The University of Michigan 16360SN/A * All rights reserved. 17360SN/A * 18360SN/A * Redistribution and use in source and binary forms, with or without 19360SN/A * modification, are permitted provided that the following conditions are 20360SN/A * met: redistributions of source code must retain the above copyright 21360SN/A * notice, this list of conditions and the following disclaimer; 22360SN/A * redistributions in binary form must reproduce the above copyright 23360SN/A * notice, this list of conditions and the following disclaimer in the 24360SN/A * documentation and/or other materials provided with the distribution; 25360SN/A * neither the name of the copyright holders nor the names of its 26360SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30360SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31360SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322093SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33360SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34360SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356712Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366712Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37360SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38360SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397680Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402474SN/A * 41360SN/A * Authors: Kevin Lim 426658Snate@binkert.org */ 438229Snate@binkert.org 442680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 458232Snate@binkert.org#define __CPU_THREAD_CONTEXT_HH__ 462474SN/A 47360SN/A#include <iostream> 488229Snate@binkert.org#include <string> 498229Snate@binkert.org 506029Ssteve.reinhardt@amd.com#include "arch/registers.hh" 51360SN/A#include "arch/types.hh" 52360SN/A#include "base/types.hh" 532107SN/A#include "config/the_isa.hh" 54360SN/A 55360SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 563114Sgblack@eecs.umich.edu// DTB pointers. 57360SN/Anamespace TheISA 586702Sgblack@eecs.umich.edu{ 596701Sgblack@eecs.umich.edu class Decoder; 606702Sgblack@eecs.umich.edu class TLB; 616111Ssteve.reinhardt@amd.com} 626111Ssteve.reinhardt@amd.comclass BaseCPU; 637823Ssteve.reinhardt@amd.comclass CheckerCPU; 646701Sgblack@eecs.umich.educlass Checkpoint; 656701Sgblack@eecs.umich.educlass EndQuiesceEvent; 666701Sgblack@eecs.umich.educlass SETranslatingPortProxy; 676701Sgblack@eecs.umich.educlass FSTranslatingPortProxy; 68360SN/Aclass PortProxy; 692680Sktlim@umich.educlass Process; 70360SN/Aclass System; 712495SN/Anamespace TheISA { 727823Ssteve.reinhardt@amd.com namespace Kernel { 73360SN/A class Statistics; 741450SN/A } 755958Sgblack@eecs.umich.edu} 76360SN/A 77360SN/A/** 78360SN/A * ThreadContext is the external interface to all thread state for 791450SN/A * anything outside of the CPU. It provides all accessor methods to 803114Sgblack@eecs.umich.edu * state that might be needed by external objects, ranging from 812680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 82360SN/A * base class; the CPU can create its own ThreadContext by either 831969SN/A * deriving from it, or using the templated ProxyThreadContext. 842484SN/A * 852484SN/A * The ThreadContext is slightly different than the ExecContext. The 86360SN/A * ThreadContext provides access to an individual thread's state; an 87360SN/A * ExecContext provides ISA access to the CPU (meaning it is 88360SN/A * implicitly multithreaded on SMT systems). Additionally the 891450SN/A * ThreadState is an abstract class that exactly defines the 903114Sgblack@eecs.umich.edu * interface; the ExecContext is a more implicit interface that must 912680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 92360SN/A */ 936701Sgblack@eecs.umich.educlass ThreadContext 941969SN/A{ 956701Sgblack@eecs.umich.edu protected: 96360SN/A typedef TheISA::MachInst MachInst; 971458SN/A typedef TheISA::IntReg IntReg; 98360SN/A typedef TheISA::FloatReg FloatReg; 99360SN/A typedef TheISA::FloatRegBits FloatRegBits; 100360SN/A typedef TheISA::CCReg CCReg; 1011450SN/A typedef TheISA::MiscReg MiscReg; 1028149SChris.Emmons@ARM.com public: 1038149SChris.Emmons@ARM.com 1048149SChris.Emmons@ARM.com enum Status 1058149SChris.Emmons@ARM.com { 1068149SChris.Emmons@ARM.com /// Running. Instructions should be executed only when 1078149SChris.Emmons@ARM.com /// the context is in this state. 1088149SChris.Emmons@ARM.com Active, 1098149SChris.Emmons@ARM.com 1108149SChris.Emmons@ARM.com /// Temporarily inactive. Entered while waiting for 1118149SChris.Emmons@ARM.com /// synchronization, etc. 1128149SChris.Emmons@ARM.com Suspended, 1138149SChris.Emmons@ARM.com 1143114Sgblack@eecs.umich.edu /// Permanently shut down. Entered when target executes 1152680Sktlim@umich.edu /// m5exit pseudo-instruction. When all contexts enter 116360SN/A /// this state, the simulation will terminate. 1176029Ssteve.reinhardt@amd.com Halted 1186029Ssteve.reinhardt@amd.com }; 1196701Sgblack@eecs.umich.edu 1205958Sgblack@eecs.umich.edu virtual ~ThreadContext() { }; 1216701Sgblack@eecs.umich.edu 1226029Ssteve.reinhardt@amd.com virtual BaseCPU *getCpuPtr() = 0; 1236029Ssteve.reinhardt@amd.com 1246029Ssteve.reinhardt@amd.com virtual int cpuId() const = 0; 1252834Sksewell@umich.edu 126360SN/A virtual int threadId() const = 0; 1271458SN/A 128360SN/A virtual void setThreadId(int id) = 0; 129360SN/A 130360SN/A virtual int contextId() const = 0; 1311450SN/A 1326109Ssanchezd@stanford.edu virtual void setContextId(int id) = 0; 1336109Ssanchezd@stanford.edu 1346109Ssanchezd@stanford.edu virtual TheISA::TLB *getITBPtr() = 0; 1356109Ssanchezd@stanford.edu 1366109Ssanchezd@stanford.edu virtual TheISA::TLB *getDTBPtr() = 0; 1376701Sgblack@eecs.umich.edu 1386109Ssanchezd@stanford.edu virtual CheckerCPU *getCheckerCpuPtr() = 0; 1396701Sgblack@eecs.umich.edu 1406109Ssanchezd@stanford.edu virtual TheISA::Decoder *getDecoderPtr() = 0; 1416109Ssanchezd@stanford.edu 1426109Ssanchezd@stanford.edu virtual System *getSystemPtr() = 0; 1436109Ssanchezd@stanford.edu 1446109Ssanchezd@stanford.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1456109Ssanchezd@stanford.edu 1463114Sgblack@eecs.umich.edu virtual PortProxy &getPhysProxy() = 0; 147360SN/A 1482107SN/A virtual FSTranslatingPortProxy &getVirtProxy() = 0; 149360SN/A 150360SN/A /** 151360SN/A * Initialise the physical and virtual port proxies and tie them to 1521450SN/A * the data port of the CPU. 1535748SSteve.Reinhardt@amd.com * 154360SN/A * tc ThreadContext for the virtual-to-physical translation 155360SN/A */ 1566701Sgblack@eecs.umich.edu virtual void initMemProxies(ThreadContext *tc) = 0; 1576701Sgblack@eecs.umich.edu 1585748SSteve.Reinhardt@amd.com virtual SETranslatingPortProxy &getMemProxy() = 0; 1595748SSteve.Reinhardt@amd.com 1605748SSteve.Reinhardt@amd.com virtual Process *getProcessPtr() = 0; 1615748SSteve.Reinhardt@amd.com 1625748SSteve.Reinhardt@amd.com virtual Status status() const = 0; 1635748SSteve.Reinhardt@amd.com 1645748SSteve.Reinhardt@amd.com virtual void setStatus(Status new_status) = 0; 1655748SSteve.Reinhardt@amd.com 1662474SN/A /// Set the status to Active. Optional delay indicates number of 1672474SN/A /// cycles to wait before beginning execution. 1685748SSteve.Reinhardt@amd.com virtual void activate(Cycles delay = Cycles(1)) = 0; 1698601Ssteve.reinhardt@amd.com 1706687Stjones1@inf.ed.ac.uk /// Set the status to Suspended. 1716687Stjones1@inf.ed.ac.uk virtual void suspend(Cycles delay = Cycles(0)) = 0; 1726687Stjones1@inf.ed.ac.uk 1736687Stjones1@inf.ed.ac.uk /// Set the status to Halted. 1746687Stjones1@inf.ed.ac.uk virtual void halt(Cycles delay = Cycles(0)) = 0; 1756687Stjones1@inf.ed.ac.uk 1766687Stjones1@inf.ed.ac.uk virtual void dumpFuncProfile() = 0; 1776687Stjones1@inf.ed.ac.uk 1786687Stjones1@inf.ed.ac.uk virtual void takeOverFrom(ThreadContext *old_context) = 0; 1796687Stjones1@inf.ed.ac.uk 1806687Stjones1@inf.ed.ac.uk virtual void regStats(const std::string &name) = 0; 1816687Stjones1@inf.ed.ac.uk 1826687Stjones1@inf.ed.ac.uk virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1836687Stjones1@inf.ed.ac.uk 1846687Stjones1@inf.ed.ac.uk // Not necessarily the best location for these... 1856687Stjones1@inf.ed.ac.uk // Having an extra function just to read these is obnoxious 1866687Stjones1@inf.ed.ac.uk virtual Tick readLastActivate() = 0; 1876687Stjones1@inf.ed.ac.uk virtual Tick readLastSuspend() = 0; 1882474SN/A 1891450SN/A virtual void profileClear() = 0; 1905748SSteve.Reinhardt@amd.com virtual void profileSample() = 0; 1915748SSteve.Reinhardt@amd.com 1921458SN/A virtual void copyArchRegs(ThreadContext *tc) = 0; 1931458SN/A 194360SN/A virtual void clearArchRegs() = 0; 195360SN/A 196360SN/A // 1971450SN/A // New accessors for new decoder. 1983114Sgblack@eecs.umich.edu // 199360SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 2006701Sgblack@eecs.umich.edu 2016701Sgblack@eecs.umich.edu virtual FloatReg readFloatReg(int reg_idx) = 0; 2027508Stjones1@inf.ed.ac.uk 2037508Stjones1@inf.ed.ac.uk virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 2047508Stjones1@inf.ed.ac.uk 2057508Stjones1@inf.ed.ac.uk virtual CCReg readCCReg(int reg_idx) = 0; 2061970SN/A 2071970SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2081970SN/A 209360SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 210360SN/A 211360SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2121450SN/A 2133114Sgblack@eecs.umich.edu virtual void setCCReg(int reg_idx, CCReg val) = 0; 214360SN/A 2156701Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() = 0; 2166701Sgblack@eecs.umich.edu 2176701Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2186701Sgblack@eecs.umich.edu 2196701Sgblack@eecs.umich.edu virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 220360SN/A 221360SN/A virtual Addr instAddr() = 0; 222360SN/A 223360SN/A virtual Addr nextInstAddr() = 0; 2242680Sktlim@umich.edu 225360SN/A virtual MicroPC microPC() = 0; 2261458SN/A 227360SN/A virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 228360SN/A 2291450SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2303114Sgblack@eecs.umich.edu 231360SN/A virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2326701Sgblack@eecs.umich.edu 2336701Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2346701Sgblack@eecs.umich.edu 2356701Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg) = 0; 2366701Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg) = 0; 237360SN/A virtual int flattenCCIndex(int reg) = 0; 2382680Sktlim@umich.edu virtual int flattenMiscIndex(int reg) = 0; 239360SN/A 240360SN/A virtual uint64_t 241360SN/A readRegOtherThread(int misc_reg, ThreadID tid) 242360SN/A { 243360SN/A return 0; 2441458SN/A } 245360SN/A 246360SN/A virtual void 247360SN/A setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 2481450SN/A { 2493114Sgblack@eecs.umich.edu } 250360SN/A 2516701Sgblack@eecs.umich.edu // Also not necessarily the best location for these two. Hopefully will go 2526701Sgblack@eecs.umich.edu // away once we decide upon where st cond failures goes. 2536701Sgblack@eecs.umich.edu virtual unsigned readStCondFailures() = 0; 2546701Sgblack@eecs.umich.edu 255360SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 256360SN/A 257360SN/A // Only really makes sense for old CPU model. Still could be useful though. 2581458SN/A virtual bool misspeculating() = 0; 259360SN/A 260360SN/A // Same with st cond failures. 261360SN/A virtual Counter readFuncExeInst() = 0; 2621450SN/A 2634118Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2644118Sgblack@eecs.umich.edu 2656701Sgblack@eecs.umich.edu // This function exits the thread context in the CPU and returns 2666701Sgblack@eecs.umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2676701Sgblack@eecs.umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2686701Sgblack@eecs.umich.edu virtual int exit() { return 1; }; 2696701Sgblack@eecs.umich.edu 2706701Sgblack@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2714118Sgblack@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2724118Sgblack@eecs.umich.edu 2734118Sgblack@eecs.umich.edu /** @{ */ 2744118Sgblack@eecs.umich.edu /** 2754118Sgblack@eecs.umich.edu * Flat register interfaces 2764118Sgblack@eecs.umich.edu * 2774118Sgblack@eecs.umich.edu * Some architectures have different registers visible in 2784118Sgblack@eecs.umich.edu * different modes. Such architectures "flatten" a register (see 2794118Sgblack@eecs.umich.edu * flattenIntIndex() and flattenFloatIndex()) to map it into the 2804118Sgblack@eecs.umich.edu * gem5 register file. This interface provides a flat interface to 2816111Ssteve.reinhardt@amd.com * the underlying register file, which allows for example 2826111Ssteve.reinhardt@amd.com * serialization code to access all registers. 2836111Ssteve.reinhardt@amd.com */ 2846111Ssteve.reinhardt@amd.com 2854118Sgblack@eecs.umich.edu virtual uint64_t readIntRegFlat(int idx) = 0; 2864118Sgblack@eecs.umich.edu virtual void setIntRegFlat(int idx, uint64_t val) = 0; 2874118Sgblack@eecs.umich.edu 2884118Sgblack@eecs.umich.edu virtual FloatReg readFloatRegFlat(int idx) = 0; 2894118Sgblack@eecs.umich.edu virtual void setFloatRegFlat(int idx, FloatReg val) = 0; 2904118Sgblack@eecs.umich.edu 2914118Sgblack@eecs.umich.edu virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; 2924118Sgblack@eecs.umich.edu virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; 2934118Sgblack@eecs.umich.edu 2944118Sgblack@eecs.umich.edu virtual CCReg readCCRegFlat(int idx) = 0; 2954118Sgblack@eecs.umich.edu virtual void setCCRegFlat(int idx, CCReg val) = 0; 2964118Sgblack@eecs.umich.edu /** @} */ 2973114Sgblack@eecs.umich.edu 298360SN/A}; 299360SN/A 3001458SN/A/** 301360SN/A * ProxyThreadContext class that provides a way to implement a 302360SN/A * ThreadContext without having to derive from it. ThreadContext is an 303360SN/A * abstract class, so anything that derives from it and uses its 304360SN/A * interface will pay the overhead of virtual function calls. This 305360SN/A * class is created to enable a user-defined Thread object to be used 3061450SN/A * wherever ThreadContexts are used, without paying the overhead of 3073114Sgblack@eecs.umich.edu * virtual function calls when it is used by itself. See 308360SN/A * simple_thread.hh for an example of this. 3096701Sgblack@eecs.umich.edu */ 3106701Sgblack@eecs.umich.edutemplate <class TC> 3116701Sgblack@eecs.umich.educlass ProxyThreadContext : public ThreadContext 3126701Sgblack@eecs.umich.edu{ 313360SN/A public: 314360SN/A ProxyThreadContext(TC *actual_tc) 315360SN/A { actualTC = actual_tc; } 3162680Sktlim@umich.edu 317360SN/A private: 3181458SN/A TC *actualTC; 319360SN/A 320360SN/A public: 3211450SN/A 3225513SMichael.Adler@intel.com BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 3235513SMichael.Adler@intel.com 3245513SMichael.Adler@intel.com int cpuId() const { return actualTC->cpuId(); } 3256731Svince@csl.cornell.edu 3266701Sgblack@eecs.umich.edu int threadId() const { return actualTC->threadId(); } 3276701Sgblack@eecs.umich.edu 3286701Sgblack@eecs.umich.edu void setThreadId(int id) { actualTC->setThreadId(id); } 3295513SMichael.Adler@intel.com 3305513SMichael.Adler@intel.com int contextId() const { return actualTC->contextId(); } 3315513SMichael.Adler@intel.com 3325513SMichael.Adler@intel.com void setContextId(int id) { actualTC->setContextId(id); } 3335513SMichael.Adler@intel.com 3345513SMichael.Adler@intel.com TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 3355513SMichael.Adler@intel.com 3365513SMichael.Adler@intel.com TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 3375513SMichael.Adler@intel.com 3385513SMichael.Adler@intel.com CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 3395513SMichael.Adler@intel.com 3405513SMichael.Adler@intel.com TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 3415513SMichael.Adler@intel.com 3425513SMichael.Adler@intel.com System *getSystemPtr() { return actualTC->getSystemPtr(); } 3435513SMichael.Adler@intel.com 3445513SMichael.Adler@intel.com TheISA::Kernel::Statistics *getKernelStats() 3455513SMichael.Adler@intel.com { return actualTC->getKernelStats(); } 3465513SMichael.Adler@intel.com 3475513SMichael.Adler@intel.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 3485513SMichael.Adler@intel.com 3495513SMichael.Adler@intel.com FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 3505513SMichael.Adler@intel.com 3515513SMichael.Adler@intel.com void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 3525513SMichael.Adler@intel.com 3535513SMichael.Adler@intel.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 3545513SMichael.Adler@intel.com 3555513SMichael.Adler@intel.com Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3565513SMichael.Adler@intel.com 3575513SMichael.Adler@intel.com Status status() const { return actualTC->status(); } 3585513SMichael.Adler@intel.com 3595513SMichael.Adler@intel.com void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3606701Sgblack@eecs.umich.edu 3616701Sgblack@eecs.umich.edu /// Set the status to Active. Optional delay indicates number of 3625513SMichael.Adler@intel.com /// cycles to wait before beginning execution. 3635513SMichael.Adler@intel.com void activate(Cycles delay = Cycles(1)) 3645513SMichael.Adler@intel.com { actualTC->activate(delay); } 3655513SMichael.Adler@intel.com 3665513SMichael.Adler@intel.com /// Set the status to Suspended. 3676701Sgblack@eecs.umich.edu void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); } 3686701Sgblack@eecs.umich.edu 3696701Sgblack@eecs.umich.edu /// Set the status to Halted. 3706701Sgblack@eecs.umich.edu void halt(Cycles delay = Cycles(0)) { actualTC->halt(); } 3715513SMichael.Adler@intel.com 3725513SMichael.Adler@intel.com void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3735513SMichael.Adler@intel.com 3745513SMichael.Adler@intel.com void takeOverFrom(ThreadContext *oldContext) 3755513SMichael.Adler@intel.com { actualTC->takeOverFrom(oldContext); } 3765513SMichael.Adler@intel.com 3775513SMichael.Adler@intel.com void regStats(const std::string &name) { actualTC->regStats(name); } 3785513SMichael.Adler@intel.com 3795513SMichael.Adler@intel.com EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3803114Sgblack@eecs.umich.edu 381511SN/A Tick readLastActivate() { return actualTC->readLastActivate(); } 3821706SN/A Tick readLastSuspend() { return actualTC->readLastSuspend(); } 383360SN/A 3846701Sgblack@eecs.umich.edu void profileClear() { return actualTC->profileClear(); } 3856701Sgblack@eecs.umich.edu void profileSample() { return actualTC->profileSample(); } 3861450SN/A 387511SN/A // @todo: Do I need this? 3883669Sbinkertn@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3893669Sbinkertn@umich.edu 3903669Sbinkertn@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 391511SN/A 3921458SN/A // 393511SN/A // New accessors for new decoder. 394511SN/A // 3955513SMichael.Adler@intel.com uint64_t readIntReg(int reg_idx) 3965513SMichael.Adler@intel.com { return actualTC->readIntReg(reg_idx); } 3975513SMichael.Adler@intel.com 3985513SMichael.Adler@intel.com FloatReg readFloatReg(int reg_idx) 3995513SMichael.Adler@intel.com { return actualTC->readFloatReg(reg_idx); } 4005513SMichael.Adler@intel.com 4016701Sgblack@eecs.umich.edu FloatRegBits readFloatRegBits(int reg_idx) 4026701Sgblack@eecs.umich.edu { return actualTC->readFloatRegBits(reg_idx); } 4035513SMichael.Adler@intel.com 4045513SMichael.Adler@intel.com CCReg readCCReg(int reg_idx) 4055513SMichael.Adler@intel.com { return actualTC->readCCReg(reg_idx); } 4065513SMichael.Adler@intel.com 4075513SMichael.Adler@intel.com void setIntReg(int reg_idx, uint64_t val) 4086701Sgblack@eecs.umich.edu { actualTC->setIntReg(reg_idx, val); } 4095513SMichael.Adler@intel.com 4105513SMichael.Adler@intel.com void setFloatReg(int reg_idx, FloatReg val) 4115513SMichael.Adler@intel.com { actualTC->setFloatReg(reg_idx, val); } 4125513SMichael.Adler@intel.com 4135513SMichael.Adler@intel.com void setFloatRegBits(int reg_idx, FloatRegBits val) 4141450SN/A { actualTC->setFloatRegBits(reg_idx, val); } 4153114Sgblack@eecs.umich.edu 416511SN/A void setCCReg(int reg_idx, CCReg val) 4171706SN/A { actualTC->setCCReg(reg_idx, val); } 418511SN/A 4196701Sgblack@eecs.umich.edu TheISA::PCState pcState() { return actualTC->pcState(); } 4206701Sgblack@eecs.umich.edu 4211458SN/A void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 422511SN/A 4231706SN/A void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 424511SN/A 4256701Sgblack@eecs.umich.edu Addr instAddr() { return actualTC->instAddr(); } 4261458SN/A Addr nextInstAddr() { return actualTC->nextInstAddr(); } 427511SN/A MicroPC microPC() { return actualTC->microPC(); } 4283669Sbinkertn@umich.edu 4293669Sbinkertn@umich.edu bool readPredicate() { return actualTC->readPredicate(); } 4303669Sbinkertn@umich.edu 4313669Sbinkertn@umich.edu void setPredicate(bool val) 4321706SN/A { actualTC->setPredicate(val); } 4331458SN/A 434511SN/A MiscReg readMiscRegNoEffect(int misc_reg) 435511SN/A { return actualTC->readMiscRegNoEffect(misc_reg); } 4361706SN/A 4373114Sgblack@eecs.umich.edu MiscReg readMiscReg(int misc_reg) 4381706SN/A { return actualTC->readMiscReg(misc_reg); } 4391706SN/A 4401706SN/A void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4416701Sgblack@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 4426701Sgblack@eecs.umich.edu 4431706SN/A void setMiscReg(int misc_reg, const MiscReg &val) 4441706SN/A { return actualTC->setMiscReg(misc_reg, val); } 4456701Sgblack@eecs.umich.edu 4461706SN/A int flattenIntIndex(int reg) 4473669Sbinkertn@umich.edu { return actualTC->flattenIntIndex(reg); } 4483669Sbinkertn@umich.edu 4493669Sbinkertn@umich.edu int flattenFloatIndex(int reg) 4501706SN/A { return actualTC->flattenFloatIndex(reg); } 4511706SN/A 4521706SN/A int flattenCCIndex(int reg) 4531706SN/A { return actualTC->flattenCCIndex(reg); } 4541706SN/A 4556111Ssteve.reinhardt@amd.com int flattenMiscIndex(int reg) 4566111Ssteve.reinhardt@amd.com { return actualTC->flattenMiscIndex(reg); } 4571706SN/A 4586701Sgblack@eecs.umich.edu unsigned readStCondFailures() 4596701Sgblack@eecs.umich.edu { return actualTC->readStCondFailures(); } 4601706SN/A 4611706SN/A void setStCondFailures(unsigned sc_failures) 4621706SN/A { actualTC->setStCondFailures(sc_failures); } 4631706SN/A 4646701Sgblack@eecs.umich.edu // @todo: Fix this! 4651706SN/A bool misspeculating() { return actualTC->misspeculating(); } 4661706SN/A 4671706SN/A void syscall(int64_t callnum) 4681706SN/A { actualTC->syscall(callnum); } 4691999SN/A 4701999SN/A Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4716703Svince@csl.cornell.edu 4726703Svince@csl.cornell.edu uint64_t readIntRegFlat(int idx) 4736703Svince@csl.cornell.edu { return actualTC->readIntRegFlat(idx); } 4746703Svince@csl.cornell.edu 4756703Svince@csl.cornell.edu void setIntRegFlat(int idx, uint64_t val) 4766703Svince@csl.cornell.edu { actualTC->setIntRegFlat(idx, val); } 4776703Svince@csl.cornell.edu 4786703Svince@csl.cornell.edu FloatReg readFloatRegFlat(int idx) 4796703Svince@csl.cornell.edu { return actualTC->readFloatRegFlat(idx); } 4806744SAli.Saidi@arm.com 4816703Svince@csl.cornell.edu void setFloatRegFlat(int idx, FloatReg val) 4826703Svince@csl.cornell.edu { actualTC->setFloatRegFlat(idx, val); } 4836703Svince@csl.cornell.edu 4846703Svince@csl.cornell.edu FloatRegBits readFloatRegBitsFlat(int idx) 4856744SAli.Saidi@arm.com { return actualTC->readFloatRegBitsFlat(idx); } 4866744SAli.Saidi@arm.com 4876744SAli.Saidi@arm.com void setFloatRegBitsFlat(int idx, FloatRegBits val) 4886703Svince@csl.cornell.edu { actualTC->setFloatRegBitsFlat(idx, val); } 4896744SAli.Saidi@arm.com 4906703Svince@csl.cornell.edu CCReg readCCRegFlat(int idx) 4916703Svince@csl.cornell.edu { return actualTC->readCCRegFlat(idx); } 4926703Svince@csl.cornell.edu 4936703Svince@csl.cornell.edu void setCCRegFlat(int idx, CCReg val) 4946685Stjones1@inf.ed.ac.uk { actualTC->setCCRegFlat(idx, val); } 4956685Stjones1@inf.ed.ac.uk}; 4966685Stjones1@inf.ed.ac.uk 4976701Sgblack@eecs.umich.edu/** @{ */ 4986701Sgblack@eecs.umich.edu/** 4996685Stjones1@inf.ed.ac.uk * Thread context serialization helpers 5006685Stjones1@inf.ed.ac.uk * 5016685Stjones1@inf.ed.ac.uk * These helper functions provide a way to the data in a 5026685Stjones1@inf.ed.ac.uk * ThreadContext. They are provided as separate helper function since 5036744SAli.Saidi@arm.com * implementing them as members of the ThreadContext interface would 5046685Stjones1@inf.ed.ac.uk * be confusing when the ThreadContext is exported via a proxy. 5056744SAli.Saidi@arm.com */ 5066744SAli.Saidi@arm.com 5076744SAli.Saidi@arm.comvoid serialize(ThreadContext &tc, std::ostream &os); 5086685Stjones1@inf.ed.ac.ukvoid unserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion); 5096744SAli.Saidi@arm.com 5106685Stjones1@inf.ed.ac.uk/** @} */ 5116685Stjones1@inf.ed.ac.uk 5126685Stjones1@inf.ed.ac.uk 5136685Stjones1@inf.ed.ac.uk/** 5145513SMichael.Adler@intel.com * Copy state between thread contexts in preparation for CPU handover. 5155513SMichael.Adler@intel.com * 5165513SMichael.Adler@intel.com * @note This method modifies the old thread contexts as well as the 5175513SMichael.Adler@intel.com * new thread context. The old thread context will have its quiesce 5185513SMichael.Adler@intel.com * event descheduled if it is scheduled and its status set to halted. 5195513SMichael.Adler@intel.com * 5205513SMichael.Adler@intel.com * @param new_tc Destination ThreadContext. 5215521Snate@binkert.org * @param old_tc Source ThreadContext. 5225513SMichael.Adler@intel.com */ 5235513SMichael.Adler@intel.comvoid takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 5245513SMichael.Adler@intel.com 5253114Sgblack@eecs.umich.edu#endif 5261999SN/A