thread_context.hh revision 10110
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_THREAD_CONTEXT_HH__ 45#define __CPU_THREAD_CONTEXT_HH__ 46 47#include <iostream> 48#include <string> 49 50#include "arch/registers.hh" 51#include "arch/types.hh" 52#include "base/types.hh" 53#include "config/the_isa.hh" 54 55// @todo: Figure out a more architecture independent way to obtain the ITB and 56// DTB pointers. 57namespace TheISA 58{ 59 class Decoder; 60 class TLB; 61} 62class BaseCPU; 63class CheckerCPU; 64class Checkpoint; 65class EndQuiesceEvent; 66class SETranslatingPortProxy; 67class FSTranslatingPortProxy; 68class PortProxy; 69class Process; 70class System; 71namespace TheISA { 72 namespace Kernel { 73 class Statistics; 74 } 75} 76 77/** 78 * ThreadContext is the external interface to all thread state for 79 * anything outside of the CPU. It provides all accessor methods to 80 * state that might be needed by external objects, ranging from 81 * register values to things such as kernel stats. It is an abstract 82 * base class; the CPU can create its own ThreadContext by either 83 * deriving from it, or using the templated ProxyThreadContext. 84 * 85 * The ThreadContext is slightly different than the ExecContext. The 86 * ThreadContext provides access to an individual thread's state; an 87 * ExecContext provides ISA access to the CPU (meaning it is 88 * implicitly multithreaded on SMT systems). Additionally the 89 * ThreadState is an abstract class that exactly defines the 90 * interface; the ExecContext is a more implicit interface that must 91 * be implemented so that the ISA can access whatever state it needs. 92 */ 93class ThreadContext 94{ 95 protected: 96 typedef TheISA::MachInst MachInst; 97 typedef TheISA::IntReg IntReg; 98 typedef TheISA::FloatReg FloatReg; 99 typedef TheISA::FloatRegBits FloatRegBits; 100 typedef TheISA::CCReg CCReg; 101 typedef TheISA::MiscReg MiscReg; 102 public: 103 104 enum Status 105 { 106 /// Running. Instructions should be executed only when 107 /// the context is in this state. 108 Active, 109 110 /// Temporarily inactive. Entered while waiting for 111 /// synchronization, etc. 112 Suspended, 113 114 /// Permanently shut down. Entered when target executes 115 /// m5exit pseudo-instruction. When all contexts enter 116 /// this state, the simulation will terminate. 117 Halted 118 }; 119 120 virtual ~ThreadContext() { }; 121 122 virtual BaseCPU *getCpuPtr() = 0; 123 124 virtual int cpuId() const = 0; 125 126 virtual int threadId() const = 0; 127 128 virtual void setThreadId(int id) = 0; 129 130 virtual int contextId() const = 0; 131 132 virtual void setContextId(int id) = 0; 133 134 virtual TheISA::TLB *getITBPtr() = 0; 135 136 virtual TheISA::TLB *getDTBPtr() = 0; 137 138 virtual CheckerCPU *getCheckerCpuPtr() = 0; 139 140 virtual TheISA::Decoder *getDecoderPtr() = 0; 141 142 virtual System *getSystemPtr() = 0; 143 144 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 145 146 virtual PortProxy &getPhysProxy() = 0; 147 148 virtual FSTranslatingPortProxy &getVirtProxy() = 0; 149 150 /** 151 * Initialise the physical and virtual port proxies and tie them to 152 * the data port of the CPU. 153 * 154 * tc ThreadContext for the virtual-to-physical translation 155 */ 156 virtual void initMemProxies(ThreadContext *tc) = 0; 157 158 virtual SETranslatingPortProxy &getMemProxy() = 0; 159 160 virtual Process *getProcessPtr() = 0; 161 162 virtual Status status() const = 0; 163 164 virtual void setStatus(Status new_status) = 0; 165 166 /// Set the status to Active. Optional delay indicates number of 167 /// cycles to wait before beginning execution. 168 virtual void activate(Cycles delay = Cycles(1)) = 0; 169 170 /// Set the status to Suspended. 171 virtual void suspend(Cycles delay = Cycles(0)) = 0; 172 173 /// Set the status to Halted. 174 virtual void halt(Cycles delay = Cycles(0)) = 0; 175 176 virtual void dumpFuncProfile() = 0; 177 178 virtual void takeOverFrom(ThreadContext *old_context) = 0; 179 180 virtual void regStats(const std::string &name) = 0; 181 182 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 183 184 // Not necessarily the best location for these... 185 // Having an extra function just to read these is obnoxious 186 virtual Tick readLastActivate() = 0; 187 virtual Tick readLastSuspend() = 0; 188 189 virtual void profileClear() = 0; 190 virtual void profileSample() = 0; 191 192 virtual void copyArchRegs(ThreadContext *tc) = 0; 193 194 virtual void clearArchRegs() = 0; 195 196 // 197 // New accessors for new decoder. 198 // 199 virtual uint64_t readIntReg(int reg_idx) = 0; 200 201 virtual FloatReg readFloatReg(int reg_idx) = 0; 202 203 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 204 205 virtual CCReg readCCReg(int reg_idx) = 0; 206 207 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 208 209 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 210 211 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 212 213 virtual void setCCReg(int reg_idx, CCReg val) = 0; 214 215 virtual TheISA::PCState pcState() = 0; 216 217 virtual void pcState(const TheISA::PCState &val) = 0; 218 219 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 220 221 virtual Addr instAddr() = 0; 222 223 virtual Addr nextInstAddr() = 0; 224 225 virtual MicroPC microPC() = 0; 226 227 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 228 229 virtual MiscReg readMiscReg(int misc_reg) = 0; 230 231 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 232 233 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 234 235 virtual int flattenIntIndex(int reg) = 0; 236 virtual int flattenFloatIndex(int reg) = 0; 237 virtual int flattenCCIndex(int reg) = 0; 238 virtual int flattenMiscIndex(int reg) = 0; 239 240 virtual uint64_t 241 readRegOtherThread(int misc_reg, ThreadID tid) 242 { 243 return 0; 244 } 245 246 virtual void 247 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 248 { 249 } 250 251 // Also not necessarily the best location for these two. Hopefully will go 252 // away once we decide upon where st cond failures goes. 253 virtual unsigned readStCondFailures() = 0; 254 255 virtual void setStCondFailures(unsigned sc_failures) = 0; 256 257 // Only really makes sense for old CPU model. Still could be useful though. 258 virtual bool misspeculating() = 0; 259 260 // Same with st cond failures. 261 virtual Counter readFuncExeInst() = 0; 262 263 virtual void syscall(int64_t callnum) = 0; 264 265 // This function exits the thread context in the CPU and returns 266 // 1 if the CPU has no more active threads (meaning it's OK to exit); 267 // Used in syscall-emulation mode when a thread calls the exit syscall. 268 virtual int exit() { return 1; }; 269 270 /** function to compare two thread contexts (for debugging) */ 271 static void compare(ThreadContext *one, ThreadContext *two); 272 273 /** @{ */ 274 /** 275 * Flat register interfaces 276 * 277 * Some architectures have different registers visible in 278 * different modes. Such architectures "flatten" a register (see 279 * flattenIntIndex() and flattenFloatIndex()) to map it into the 280 * gem5 register file. This interface provides a flat interface to 281 * the underlying register file, which allows for example 282 * serialization code to access all registers. 283 */ 284 285 virtual uint64_t readIntRegFlat(int idx) = 0; 286 virtual void setIntRegFlat(int idx, uint64_t val) = 0; 287 288 virtual FloatReg readFloatRegFlat(int idx) = 0; 289 virtual void setFloatRegFlat(int idx, FloatReg val) = 0; 290 291 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; 292 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; 293 294 virtual CCReg readCCRegFlat(int idx) = 0; 295 virtual void setCCRegFlat(int idx, CCReg val) = 0; 296 /** @} */ 297 298}; 299 300/** 301 * ProxyThreadContext class that provides a way to implement a 302 * ThreadContext without having to derive from it. ThreadContext is an 303 * abstract class, so anything that derives from it and uses its 304 * interface will pay the overhead of virtual function calls. This 305 * class is created to enable a user-defined Thread object to be used 306 * wherever ThreadContexts are used, without paying the overhead of 307 * virtual function calls when it is used by itself. See 308 * simple_thread.hh for an example of this. 309 */ 310template <class TC> 311class ProxyThreadContext : public ThreadContext 312{ 313 public: 314 ProxyThreadContext(TC *actual_tc) 315 { actualTC = actual_tc; } 316 317 private: 318 TC *actualTC; 319 320 public: 321 322 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 323 324 int cpuId() const { return actualTC->cpuId(); } 325 326 int threadId() const { return actualTC->threadId(); } 327 328 void setThreadId(int id) { actualTC->setThreadId(id); } 329 330 int contextId() const { return actualTC->contextId(); } 331 332 void setContextId(int id) { actualTC->setContextId(id); } 333 334 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 335 336 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 337 338 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 339 340 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 341 342 System *getSystemPtr() { return actualTC->getSystemPtr(); } 343 344 TheISA::Kernel::Statistics *getKernelStats() 345 { return actualTC->getKernelStats(); } 346 347 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 348 349 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 350 351 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 352 353 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 354 355 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 356 357 Status status() const { return actualTC->status(); } 358 359 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 360 361 /// Set the status to Active. Optional delay indicates number of 362 /// cycles to wait before beginning execution. 363 void activate(Cycles delay = Cycles(1)) 364 { actualTC->activate(delay); } 365 366 /// Set the status to Suspended. 367 void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); } 368 369 /// Set the status to Halted. 370 void halt(Cycles delay = Cycles(0)) { actualTC->halt(); } 371 372 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 373 374 void takeOverFrom(ThreadContext *oldContext) 375 { actualTC->takeOverFrom(oldContext); } 376 377 void regStats(const std::string &name) { actualTC->regStats(name); } 378 379 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 380 381 Tick readLastActivate() { return actualTC->readLastActivate(); } 382 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 383 384 void profileClear() { return actualTC->profileClear(); } 385 void profileSample() { return actualTC->profileSample(); } 386 387 // @todo: Do I need this? 388 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 389 390 void clearArchRegs() { actualTC->clearArchRegs(); } 391 392 // 393 // New accessors for new decoder. 394 // 395 uint64_t readIntReg(int reg_idx) 396 { return actualTC->readIntReg(reg_idx); } 397 398 FloatReg readFloatReg(int reg_idx) 399 { return actualTC->readFloatReg(reg_idx); } 400 401 FloatRegBits readFloatRegBits(int reg_idx) 402 { return actualTC->readFloatRegBits(reg_idx); } 403 404 CCReg readCCReg(int reg_idx) 405 { return actualTC->readCCReg(reg_idx); } 406 407 void setIntReg(int reg_idx, uint64_t val) 408 { actualTC->setIntReg(reg_idx, val); } 409 410 void setFloatReg(int reg_idx, FloatReg val) 411 { actualTC->setFloatReg(reg_idx, val); } 412 413 void setFloatRegBits(int reg_idx, FloatRegBits val) 414 { actualTC->setFloatRegBits(reg_idx, val); } 415 416 void setCCReg(int reg_idx, CCReg val) 417 { actualTC->setCCReg(reg_idx, val); } 418 419 TheISA::PCState pcState() { return actualTC->pcState(); } 420 421 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 422 423 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 424 425 Addr instAddr() { return actualTC->instAddr(); } 426 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 427 MicroPC microPC() { return actualTC->microPC(); } 428 429 bool readPredicate() { return actualTC->readPredicate(); } 430 431 void setPredicate(bool val) 432 { actualTC->setPredicate(val); } 433 434 MiscReg readMiscRegNoEffect(int misc_reg) 435 { return actualTC->readMiscRegNoEffect(misc_reg); } 436 437 MiscReg readMiscReg(int misc_reg) 438 { return actualTC->readMiscReg(misc_reg); } 439 440 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 441 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 442 443 void setMiscReg(int misc_reg, const MiscReg &val) 444 { return actualTC->setMiscReg(misc_reg, val); } 445 446 int flattenIntIndex(int reg) 447 { return actualTC->flattenIntIndex(reg); } 448 449 int flattenFloatIndex(int reg) 450 { return actualTC->flattenFloatIndex(reg); } 451 452 int flattenCCIndex(int reg) 453 { return actualTC->flattenCCIndex(reg); } 454 455 int flattenMiscIndex(int reg) 456 { return actualTC->flattenMiscIndex(reg); } 457 458 unsigned readStCondFailures() 459 { return actualTC->readStCondFailures(); } 460 461 void setStCondFailures(unsigned sc_failures) 462 { actualTC->setStCondFailures(sc_failures); } 463 464 // @todo: Fix this! 465 bool misspeculating() { return actualTC->misspeculating(); } 466 467 void syscall(int64_t callnum) 468 { actualTC->syscall(callnum); } 469 470 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 471 472 uint64_t readIntRegFlat(int idx) 473 { return actualTC->readIntRegFlat(idx); } 474 475 void setIntRegFlat(int idx, uint64_t val) 476 { actualTC->setIntRegFlat(idx, val); } 477 478 FloatReg readFloatRegFlat(int idx) 479 { return actualTC->readFloatRegFlat(idx); } 480 481 void setFloatRegFlat(int idx, FloatReg val) 482 { actualTC->setFloatRegFlat(idx, val); } 483 484 FloatRegBits readFloatRegBitsFlat(int idx) 485 { return actualTC->readFloatRegBitsFlat(idx); } 486 487 void setFloatRegBitsFlat(int idx, FloatRegBits val) 488 { actualTC->setFloatRegBitsFlat(idx, val); } 489 490 CCReg readCCRegFlat(int idx) 491 { return actualTC->readCCRegFlat(idx); } 492 493 void setCCRegFlat(int idx, CCReg val) 494 { actualTC->setCCRegFlat(idx, val); } 495}; 496 497/** @{ */ 498/** 499 * Thread context serialization helpers 500 * 501 * These helper functions provide a way to the data in a 502 * ThreadContext. They are provided as separate helper function since 503 * implementing them as members of the ThreadContext interface would 504 * be confusing when the ThreadContext is exported via a proxy. 505 */ 506 507void serialize(ThreadContext &tc, std::ostream &os); 508void unserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion); 509 510/** @} */ 511 512 513/** 514 * Copy state between thread contexts in preparation for CPU handover. 515 * 516 * @note This method modifies the old thread contexts as well as the 517 * new thread context. The old thread context will have its quiesce 518 * event descheduled if it is scheduled and its status set to halted. 519 * 520 * @param new_tc Destination ThreadContext. 521 * @param old_tc Source ThreadContext. 522 */ 523void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 524 525#endif 526