thread_context.cc revision 13610
15217Ssaidi@eecs.umich.edu/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2012, 2016-2017 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 49428SAndreas.Sandberg@ARM.com * All rights reserved 59428SAndreas.Sandberg@ARM.com * 69428SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 79428SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 89428SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 99428SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 109428SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 119428SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 129428SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 139428SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 149428SAndreas.Sandberg@ARM.com * 155217Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 165217Ssaidi@eecs.umich.edu * All rights reserved. 175217Ssaidi@eecs.umich.edu * 185217Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 195217Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 205217Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 215217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 225217Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 235217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 245217Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 255217Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 265217Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 275217Ssaidi@eecs.umich.edu * this software without specific prior written permission. 285217Ssaidi@eecs.umich.edu * 295217Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305217Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315217Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325217Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335217Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345217Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355217Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365217Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375217Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385217Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395217Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405217Ssaidi@eecs.umich.edu * 415217Ssaidi@eecs.umich.edu * Authors: Kevin Lim 425217Ssaidi@eecs.umich.edu */ 435217Ssaidi@eecs.umich.edu 4411793Sbrandon.potter@amd.com#include "cpu/thread_context.hh" 4511793Sbrandon.potter@amd.com 4613610Sgiacomo.gabrielli@arm.com#include "arch/generic/vec_pred_reg.hh" 4711627Smichael.lebeane@amd.com#include "arch/kernel_stats.hh" 4812334Sgabeblack@google.com#include "base/logging.hh" 495217Ssaidi@eecs.umich.edu#include "base/trace.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 519441SAndreas.Sandberg@ARM.com#include "cpu/base.hh" 529441SAndreas.Sandberg@ARM.com#include "cpu/quiesce_event.hh" 538232Snate@binkert.org#include "debug/Context.hh" 5411627Smichael.lebeane@amd.com#include "debug/Quiesce.hh" 5511627Smichael.lebeane@amd.com#include "params/BaseCPU.hh" 569441SAndreas.Sandberg@ARM.com#include "sim/full_system.hh" 575217Ssaidi@eecs.umich.edu 585217Ssaidi@eecs.umich.eduvoid 595217Ssaidi@eecs.umich.eduThreadContext::compare(ThreadContext *one, ThreadContext *two) 605217Ssaidi@eecs.umich.edu{ 615217Ssaidi@eecs.umich.edu DPRINTF(Context, "Comparing thread contexts\n"); 625217Ssaidi@eecs.umich.edu 635217Ssaidi@eecs.umich.edu // First loop through the integer registers. 645217Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 6513557Sgabeblack@google.com RegVal t1 = one->readIntReg(i); 6613557Sgabeblack@google.com RegVal t2 = two->readIntReg(i); 675217Ssaidi@eecs.umich.edu if (t1 != t2) 685217Ssaidi@eecs.umich.edu panic("Int reg idx %d doesn't match, one: %#x, two: %#x", 695217Ssaidi@eecs.umich.edu i, t1, t2); 705217Ssaidi@eecs.umich.edu } 715217Ssaidi@eecs.umich.edu 725217Ssaidi@eecs.umich.edu // Then loop through the floating point registers. 735217Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 7413557Sgabeblack@google.com RegVal t1 = one->readFloatRegBits(i); 7513557Sgabeblack@google.com RegVal t2 = two->readFloatRegBits(i); 765217Ssaidi@eecs.umich.edu if (t1 != t2) 775217Ssaidi@eecs.umich.edu panic("Float reg idx %d doesn't match, one: %#x, two: %#x", 785217Ssaidi@eecs.umich.edu i, t1, t2); 795217Ssaidi@eecs.umich.edu } 8012109SRekai.GonzalezAlberquilla@arm.com 8112109SRekai.GonzalezAlberquilla@arm.com // Then loop through the vector registers. 8212109SRekai.GonzalezAlberquilla@arm.com for (int i = 0; i < TheISA::NumVecRegs; ++i) { 8312109SRekai.GonzalezAlberquilla@arm.com RegId rid(VecRegClass, i); 8412109SRekai.GonzalezAlberquilla@arm.com const TheISA::VecRegContainer& t1 = one->readVecReg(rid); 8512109SRekai.GonzalezAlberquilla@arm.com const TheISA::VecRegContainer& t2 = two->readVecReg(rid); 8612109SRekai.GonzalezAlberquilla@arm.com if (t1 != t2) 8712109SRekai.GonzalezAlberquilla@arm.com panic("Vec reg idx %d doesn't match, one: %#x, two: %#x", 8812109SRekai.GonzalezAlberquilla@arm.com i, t1, t2); 8912109SRekai.GonzalezAlberquilla@arm.com } 9013610Sgiacomo.gabrielli@arm.com 9113610Sgiacomo.gabrielli@arm.com // Then loop through the predicate registers. 9213610Sgiacomo.gabrielli@arm.com for (int i = 0; i < TheISA::NumVecPredRegs; ++i) { 9313610Sgiacomo.gabrielli@arm.com RegId rid(VecPredRegClass, i); 9413610Sgiacomo.gabrielli@arm.com const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid); 9513610Sgiacomo.gabrielli@arm.com const TheISA::VecPredRegContainer& t2 = two->readVecPredReg(rid); 9613610Sgiacomo.gabrielli@arm.com if (t1 != t2) 9713610Sgiacomo.gabrielli@arm.com panic("Pred reg idx %d doesn't match, one: %#x, two: %#x", 9813610Sgiacomo.gabrielli@arm.com i, t1, t2); 9913610Sgiacomo.gabrielli@arm.com } 10013610Sgiacomo.gabrielli@arm.com 1015217Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 10213557Sgabeblack@google.com RegVal t1 = one->readMiscRegNoEffect(i); 10313557Sgabeblack@google.com RegVal t2 = two->readMiscRegNoEffect(i); 1045217Ssaidi@eecs.umich.edu if (t1 != t2) 1055217Ssaidi@eecs.umich.edu panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", 1065217Ssaidi@eecs.umich.edu i, t1, t2); 1075217Ssaidi@eecs.umich.edu } 1085217Ssaidi@eecs.umich.edu 1099920Syasuko.eckert@amd.com // loop through the Condition Code registers. 1109920Syasuko.eckert@amd.com for (int i = 0; i < TheISA::NumCCRegs; ++i) { 1119920Syasuko.eckert@amd.com TheISA::CCReg t1 = one->readCCReg(i); 1129920Syasuko.eckert@amd.com TheISA::CCReg t2 = two->readCCReg(i); 1139920Syasuko.eckert@amd.com if (t1 != t2) 1149920Syasuko.eckert@amd.com panic("CC reg idx %d doesn't match, one: %#x, two: %#x", 1159920Syasuko.eckert@amd.com i, t1, t2); 1169920Syasuko.eckert@amd.com } 1177720Sgblack@eecs.umich.edu if (!(one->pcState() == two->pcState())) 1187720Sgblack@eecs.umich.edu panic("PC state doesn't match."); 1195712Shsul@eecs.umich.edu int id1 = one->cpuId(); 1205712Shsul@eecs.umich.edu int id2 = two->cpuId(); 1215217Ssaidi@eecs.umich.edu if (id1 != id2) 1225217Ssaidi@eecs.umich.edu panic("CPU ids don't match, one: %d, two: %d", id1, id2); 1235714Shsul@eecs.umich.edu 12411005Sandreas.sandberg@arm.com const ContextID cid1 = one->contextId(); 12511005Sandreas.sandberg@arm.com const ContextID cid2 = two->contextId(); 12611005Sandreas.sandberg@arm.com if (cid1 != cid2) 1275714Shsul@eecs.umich.edu panic("Context ids don't match, one: %d, two: %d", id1, id2); 1285714Shsul@eecs.umich.edu 1295714Shsul@eecs.umich.edu 1305217Ssaidi@eecs.umich.edu} 1319428SAndreas.Sandberg@ARM.com 1329428SAndreas.Sandberg@ARM.comvoid 13311627Smichael.lebeane@amd.comThreadContext::quiesce() 13411627Smichael.lebeane@amd.com{ 13511627Smichael.lebeane@amd.com if (!getCpuPtr()->params()->do_quiesce) 13611627Smichael.lebeane@amd.com return; 13711627Smichael.lebeane@amd.com 13811627Smichael.lebeane@amd.com DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name()); 13911627Smichael.lebeane@amd.com 14011627Smichael.lebeane@amd.com suspend(); 14111627Smichael.lebeane@amd.com if (getKernelStats()) 14211627Smichael.lebeane@amd.com getKernelStats()->quiesce(); 14311627Smichael.lebeane@amd.com} 14411627Smichael.lebeane@amd.com 14511627Smichael.lebeane@amd.com 14611627Smichael.lebeane@amd.comvoid 14711627Smichael.lebeane@amd.comThreadContext::quiesceTick(Tick resume) 14811627Smichael.lebeane@amd.com{ 14911627Smichael.lebeane@amd.com BaseCPU *cpu = getCpuPtr(); 15011627Smichael.lebeane@amd.com 15111627Smichael.lebeane@amd.com if (!cpu->params()->do_quiesce) 15211627Smichael.lebeane@amd.com return; 15311627Smichael.lebeane@amd.com 15411627Smichael.lebeane@amd.com EndQuiesceEvent *quiesceEvent = getQuiesceEvent(); 15511627Smichael.lebeane@amd.com 15611627Smichael.lebeane@amd.com cpu->reschedule(quiesceEvent, resume, true); 15711627Smichael.lebeane@amd.com 15811627Smichael.lebeane@amd.com DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume); 15911627Smichael.lebeane@amd.com 16011627Smichael.lebeane@amd.com suspend(); 16111627Smichael.lebeane@amd.com if (getKernelStats()) 16211627Smichael.lebeane@amd.com getKernelStats()->quiesce(); 16311627Smichael.lebeane@amd.com} 16411627Smichael.lebeane@amd.com 16511627Smichael.lebeane@amd.comvoid 16610905Sandreas.sandberg@arm.comserialize(ThreadContext &tc, CheckpointOut &cp) 1679428SAndreas.Sandberg@ARM.com{ 1689428SAndreas.Sandberg@ARM.com using namespace TheISA; 1699428SAndreas.Sandberg@ARM.com 17013557Sgabeblack@google.com RegVal floatRegs[NumFloatRegs]; 1719428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumFloatRegs; ++i) 1729428SAndreas.Sandberg@ARM.com floatRegs[i] = tc.readFloatRegBitsFlat(i); 1739428SAndreas.Sandberg@ARM.com // This is a bit ugly, but needed to maintain backwards 1749428SAndreas.Sandberg@ARM.com // compatibility. 17510905Sandreas.sandberg@arm.com arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs); 1769428SAndreas.Sandberg@ARM.com 17712109SRekai.GonzalezAlberquilla@arm.com std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs); 17812109SRekai.GonzalezAlberquilla@arm.com for (int i = 0; i < NumVecRegs; ++i) { 17912109SRekai.GonzalezAlberquilla@arm.com vecRegs[i] = tc.readVecRegFlat(i); 18012109SRekai.GonzalezAlberquilla@arm.com } 18112109SRekai.GonzalezAlberquilla@arm.com SERIALIZE_CONTAINER(vecRegs); 18212109SRekai.GonzalezAlberquilla@arm.com 18313610Sgiacomo.gabrielli@arm.com std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs); 18413610Sgiacomo.gabrielli@arm.com for (int i = 0; i < NumVecPredRegs; ++i) { 18513610Sgiacomo.gabrielli@arm.com vecPredRegs[i] = tc.readVecPredRegFlat(i); 18613610Sgiacomo.gabrielli@arm.com } 18713610Sgiacomo.gabrielli@arm.com SERIALIZE_CONTAINER(vecPredRegs); 18813610Sgiacomo.gabrielli@arm.com 18913557Sgabeblack@google.com RegVal intRegs[NumIntRegs]; 1909428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumIntRegs; ++i) 1919428SAndreas.Sandberg@ARM.com intRegs[i] = tc.readIntRegFlat(i); 1929428SAndreas.Sandberg@ARM.com SERIALIZE_ARRAY(intRegs, NumIntRegs); 1939428SAndreas.Sandberg@ARM.com 1949920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 1959920Syasuko.eckert@amd.com CCReg ccRegs[NumCCRegs]; 1969920Syasuko.eckert@amd.com for (int i = 0; i < NumCCRegs; ++i) 1979920Syasuko.eckert@amd.com ccRegs[i] = tc.readCCRegFlat(i); 1989920Syasuko.eckert@amd.com SERIALIZE_ARRAY(ccRegs, NumCCRegs); 1999920Syasuko.eckert@amd.com#endif 2009920Syasuko.eckert@amd.com 20110905Sandreas.sandberg@arm.com tc.pcState().serialize(cp); 2029428SAndreas.Sandberg@ARM.com 2039428SAndreas.Sandberg@ARM.com // thread_num and cpu_id are deterministic from the config 2049428SAndreas.Sandberg@ARM.com} 2059428SAndreas.Sandberg@ARM.com 2069428SAndreas.Sandberg@ARM.comvoid 20710905Sandreas.sandberg@arm.comunserialize(ThreadContext &tc, CheckpointIn &cp) 2089428SAndreas.Sandberg@ARM.com{ 2099428SAndreas.Sandberg@ARM.com using namespace TheISA; 2109428SAndreas.Sandberg@ARM.com 21113557Sgabeblack@google.com RegVal floatRegs[NumFloatRegs]; 2129428SAndreas.Sandberg@ARM.com // This is a bit ugly, but needed to maintain backwards 2139428SAndreas.Sandberg@ARM.com // compatibility. 21410905Sandreas.sandberg@arm.com arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs); 2159428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumFloatRegs; ++i) 2169428SAndreas.Sandberg@ARM.com tc.setFloatRegBitsFlat(i, floatRegs[i]); 2179428SAndreas.Sandberg@ARM.com 21812109SRekai.GonzalezAlberquilla@arm.com std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs); 21912109SRekai.GonzalezAlberquilla@arm.com UNSERIALIZE_CONTAINER(vecRegs); 22012109SRekai.GonzalezAlberquilla@arm.com for (int i = 0; i < NumVecRegs; ++i) { 22112109SRekai.GonzalezAlberquilla@arm.com tc.setVecRegFlat(i, vecRegs[i]); 22212109SRekai.GonzalezAlberquilla@arm.com } 22312109SRekai.GonzalezAlberquilla@arm.com 22413610Sgiacomo.gabrielli@arm.com std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs); 22513610Sgiacomo.gabrielli@arm.com UNSERIALIZE_CONTAINER(vecPredRegs); 22613610Sgiacomo.gabrielli@arm.com for (int i = 0; i < NumVecPredRegs; ++i) { 22713610Sgiacomo.gabrielli@arm.com tc.setVecPredRegFlat(i, vecPredRegs[i]); 22813610Sgiacomo.gabrielli@arm.com } 22913610Sgiacomo.gabrielli@arm.com 23013557Sgabeblack@google.com RegVal intRegs[NumIntRegs]; 2319428SAndreas.Sandberg@ARM.com UNSERIALIZE_ARRAY(intRegs, NumIntRegs); 2329428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumIntRegs; ++i) 2339428SAndreas.Sandberg@ARM.com tc.setIntRegFlat(i, intRegs[i]); 2349428SAndreas.Sandberg@ARM.com 2359920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 2369920Syasuko.eckert@amd.com CCReg ccRegs[NumCCRegs]; 2379920Syasuko.eckert@amd.com UNSERIALIZE_ARRAY(ccRegs, NumCCRegs); 2389920Syasuko.eckert@amd.com for (int i = 0; i < NumCCRegs; ++i) 2399920Syasuko.eckert@amd.com tc.setCCRegFlat(i, ccRegs[i]); 2409920Syasuko.eckert@amd.com#endif 2419920Syasuko.eckert@amd.com 2429428SAndreas.Sandberg@ARM.com PCState pcState; 24310905Sandreas.sandberg@arm.com pcState.unserialize(cp); 2449428SAndreas.Sandberg@ARM.com tc.pcState(pcState); 2459428SAndreas.Sandberg@ARM.com 2469428SAndreas.Sandberg@ARM.com // thread_num and cpu_id are deterministic from the config 2479428SAndreas.Sandberg@ARM.com} 2489441SAndreas.Sandberg@ARM.com 2499441SAndreas.Sandberg@ARM.comvoid 2509441SAndreas.Sandberg@ARM.comtakeOverFrom(ThreadContext &ntc, ThreadContext &otc) 2519441SAndreas.Sandberg@ARM.com{ 2529441SAndreas.Sandberg@ARM.com assert(ntc.getProcessPtr() == otc.getProcessPtr()); 2539441SAndreas.Sandberg@ARM.com 2549441SAndreas.Sandberg@ARM.com ntc.setStatus(otc.status()); 2559441SAndreas.Sandberg@ARM.com ntc.copyArchRegs(&otc); 2569441SAndreas.Sandberg@ARM.com ntc.setContextId(otc.contextId()); 2579441SAndreas.Sandberg@ARM.com ntc.setThreadId(otc.threadId()); 2589441SAndreas.Sandberg@ARM.com 2599441SAndreas.Sandberg@ARM.com if (FullSystem) { 2609441SAndreas.Sandberg@ARM.com assert(ntc.getSystemPtr() == otc.getSystemPtr()); 2619441SAndreas.Sandberg@ARM.com 2629441SAndreas.Sandberg@ARM.com BaseCPU *ncpu(ntc.getCpuPtr()); 2639441SAndreas.Sandberg@ARM.com assert(ncpu); 2649441SAndreas.Sandberg@ARM.com EndQuiesceEvent *oqe(otc.getQuiesceEvent()); 2659441SAndreas.Sandberg@ARM.com assert(oqe); 2669441SAndreas.Sandberg@ARM.com assert(oqe->tc == &otc); 2679441SAndreas.Sandberg@ARM.com 2689441SAndreas.Sandberg@ARM.com BaseCPU *ocpu(otc.getCpuPtr()); 2699441SAndreas.Sandberg@ARM.com assert(ocpu); 2709441SAndreas.Sandberg@ARM.com EndQuiesceEvent *nqe(ntc.getQuiesceEvent()); 2719441SAndreas.Sandberg@ARM.com assert(nqe); 2729441SAndreas.Sandberg@ARM.com assert(nqe->tc == &ntc); 2739441SAndreas.Sandberg@ARM.com 2749441SAndreas.Sandberg@ARM.com if (oqe->scheduled()) { 2759441SAndreas.Sandberg@ARM.com ncpu->schedule(nqe, oqe->when()); 2769441SAndreas.Sandberg@ARM.com ocpu->deschedule(oqe); 2779441SAndreas.Sandberg@ARM.com } 2789441SAndreas.Sandberg@ARM.com } 2799441SAndreas.Sandberg@ARM.com 2809441SAndreas.Sandberg@ARM.com otc.setStatus(ThreadContext::Halted); 2819441SAndreas.Sandberg@ARM.com} 282