thread_context.cc revision 13610 
1/*
2 * Copyright (c) 2012, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#include "cpu/thread_context.hh"
45
46#include "arch/generic/vec_pred_reg.hh"
47#include "arch/kernel_stats.hh"
48#include "base/logging.hh"
49#include "base/trace.hh"
50#include "config/the_isa.hh"
51#include "cpu/base.hh"
52#include "cpu/quiesce_event.hh"
53#include "debug/Context.hh"
54#include "debug/Quiesce.hh"
55#include "params/BaseCPU.hh"
56#include "sim/full_system.hh"
57
58void
59ThreadContext::compare(ThreadContext *one, ThreadContext *two)
60{
61    DPRINTF(Context, "Comparing thread contexts\n");
62
63    // First loop through the integer registers.
64    for (int i = 0; i < TheISA::NumIntRegs; ++i) {
65        RegVal t1 = one->readIntReg(i);
66        RegVal t2 = two->readIntReg(i);
67        if (t1 != t2)
68            panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
69                  i, t1, t2);
70    }
71
72    // Then loop through the floating point registers.
73    for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
74        RegVal t1 = one->readFloatRegBits(i);
75        RegVal t2 = two->readFloatRegBits(i);
76        if (t1 != t2)
77            panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
78                  i, t1, t2);
79    }
80
81    // Then loop through the vector registers.
82    for (int i = 0; i < TheISA::NumVecRegs; ++i) {
83        RegId rid(VecRegClass, i);
84        const TheISA::VecRegContainer& t1 = one->readVecReg(rid);
85        const TheISA::VecRegContainer& t2 = two->readVecReg(rid);
86        if (t1 != t2)
87            panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
88                  i, t1, t2);
89    }
90
91    // Then loop through the predicate registers.
92    for (int i = 0; i < TheISA::NumVecPredRegs; ++i) {
93        RegId rid(VecPredRegClass, i);
94        const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid);
95        const TheISA::VecPredRegContainer& t2 = two->readVecPredReg(rid);
96        if (t1 != t2)
97            panic("Pred reg idx %d doesn't match, one: %#x, two: %#x",
98                  i, t1, t2);
99    }
100
101    for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
102        RegVal t1 = one->readMiscRegNoEffect(i);
103        RegVal t2 = two->readMiscRegNoEffect(i);
104        if (t1 != t2)
105            panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
106                  i, t1, t2);
107    }
108
109    // loop through the Condition Code registers.
110    for (int i = 0; i < TheISA::NumCCRegs; ++i) {
111        TheISA::CCReg t1 = one->readCCReg(i);
112        TheISA::CCReg t2 = two->readCCReg(i);
113        if (t1 != t2)
114            panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
115                  i, t1, t2);
116    }
117    if (!(one->pcState() == two->pcState()))
118        panic("PC state doesn't match.");
119    int id1 = one->cpuId();
120    int id2 = two->cpuId();
121    if (id1 != id2)
122        panic("CPU ids don't match, one: %d, two: %d", id1, id2);
123
124    const ContextID cid1 = one->contextId();
125    const ContextID cid2 = two->contextId();
126    if (cid1 != cid2)
127        panic("Context ids don't match, one: %d, two: %d", id1, id2);
128
129
130}
131
132void
133ThreadContext::quiesce()
134{
135    if (!getCpuPtr()->params()->do_quiesce)
136        return;
137
138    DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name());
139
140    suspend();
141    if (getKernelStats())
142       getKernelStats()->quiesce();
143}
144
145
146void
147ThreadContext::quiesceTick(Tick resume)
148{
149    BaseCPU *cpu = getCpuPtr();
150
151    if (!cpu->params()->do_quiesce)
152        return;
153
154    EndQuiesceEvent *quiesceEvent = getQuiesceEvent();
155
156    cpu->reschedule(quiesceEvent, resume, true);
157
158    DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume);
159
160    suspend();
161    if (getKernelStats())
162        getKernelStats()->quiesce();
163}
164
165void
166serialize(ThreadContext &tc, CheckpointOut &cp)
167{
168    using namespace TheISA;
169
170    RegVal floatRegs[NumFloatRegs];
171    for (int i = 0; i < NumFloatRegs; ++i)
172        floatRegs[i] = tc.readFloatRegBitsFlat(i);
173    // This is a bit ugly, but needed to maintain backwards
174    // compatibility.
175    arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
176
177    std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
178    for (int i = 0; i < NumVecRegs; ++i) {
179        vecRegs[i] = tc.readVecRegFlat(i);
180    }
181    SERIALIZE_CONTAINER(vecRegs);
182
183    std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
184    for (int i = 0; i < NumVecPredRegs; ++i) {
185        vecPredRegs[i] = tc.readVecPredRegFlat(i);
186    }
187    SERIALIZE_CONTAINER(vecPredRegs);
188
189    RegVal intRegs[NumIntRegs];
190    for (int i = 0; i < NumIntRegs; ++i)
191        intRegs[i] = tc.readIntRegFlat(i);
192    SERIALIZE_ARRAY(intRegs, NumIntRegs);
193
194#ifdef ISA_HAS_CC_REGS
195    CCReg ccRegs[NumCCRegs];
196    for (int i = 0; i < NumCCRegs; ++i)
197        ccRegs[i] = tc.readCCRegFlat(i);
198    SERIALIZE_ARRAY(ccRegs, NumCCRegs);
199#endif
200
201    tc.pcState().serialize(cp);
202
203    // thread_num and cpu_id are deterministic from the config
204}
205
206void
207unserialize(ThreadContext &tc, CheckpointIn &cp)
208{
209    using namespace TheISA;
210
211    RegVal floatRegs[NumFloatRegs];
212    // This is a bit ugly, but needed to maintain backwards
213    // compatibility.
214    arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
215    for (int i = 0; i < NumFloatRegs; ++i)
216        tc.setFloatRegBitsFlat(i, floatRegs[i]);
217
218    std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
219    UNSERIALIZE_CONTAINER(vecRegs);
220    for (int i = 0; i < NumVecRegs; ++i) {
221        tc.setVecRegFlat(i, vecRegs[i]);
222    }
223
224    std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
225    UNSERIALIZE_CONTAINER(vecPredRegs);
226    for (int i = 0; i < NumVecPredRegs; ++i) {
227        tc.setVecPredRegFlat(i, vecPredRegs[i]);
228    }
229
230    RegVal intRegs[NumIntRegs];
231    UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
232    for (int i = 0; i < NumIntRegs; ++i)
233        tc.setIntRegFlat(i, intRegs[i]);
234
235#ifdef ISA_HAS_CC_REGS
236    CCReg ccRegs[NumCCRegs];
237    UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
238    for (int i = 0; i < NumCCRegs; ++i)
239        tc.setCCRegFlat(i, ccRegs[i]);
240#endif
241
242    PCState pcState;
243    pcState.unserialize(cp);
244    tc.pcState(pcState);
245
246    // thread_num and cpu_id are deterministic from the config
247}
248
249void
250takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
251{
252    assert(ntc.getProcessPtr() == otc.getProcessPtr());
253
254    ntc.setStatus(otc.status());
255    ntc.copyArchRegs(&otc);
256    ntc.setContextId(otc.contextId());
257    ntc.setThreadId(otc.threadId());
258
259    if (FullSystem) {
260        assert(ntc.getSystemPtr() == otc.getSystemPtr());
261
262        BaseCPU *ncpu(ntc.getCpuPtr());
263        assert(ncpu);
264        EndQuiesceEvent *oqe(otc.getQuiesceEvent());
265        assert(oqe);
266        assert(oqe->tc == &otc);
267
268        BaseCPU *ocpu(otc.getCpuPtr());
269        assert(ocpu);
270        EndQuiesceEvent *nqe(ntc.getQuiesceEvent());
271        assert(nqe);
272        assert(nqe->tc == &ntc);
273
274        if (oqe->scheduled()) {
275            ncpu->schedule(nqe, oqe->when());
276            ocpu->deschedule(oqe);
277        }
278    }
279
280    otc.setStatus(ThreadContext::Halted);
281}
282