RubyTester.cc revision 11266
16899SN/A/* 29542Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited 38851Sandreas.hansson@arm.com * All rights reserved 48851Sandreas.hansson@arm.com * 58851Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68851Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78851Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88851Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98851Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108851Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118851Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128851Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138851Sandreas.hansson@arm.com * 146899SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 156899SN/A * Copyright (c) 2009 Advanced Micro Devices, Inc. 166899SN/A * All rights reserved. 176899SN/A * 186899SN/A * Redistribution and use in source and binary forms, with or without 196899SN/A * modification, are permitted provided that the following conditions are 206899SN/A * met: redistributions of source code must retain the above copyright 216899SN/A * notice, this list of conditions and the following disclaimer; 226899SN/A * redistributions in binary form must reproduce the above copyright 236899SN/A * notice, this list of conditions and the following disclaimer in the 246899SN/A * documentation and/or other materials provided with the distribution; 256899SN/A * neither the name of the copyright holders nor the names of its 266899SN/A * contributors may be used to endorse or promote products derived from 276899SN/A * this software without specific prior written permission. 286899SN/A * 296899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316899SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326899SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336899SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376899SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386899SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396899SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406899SN/A */ 416899SN/A 427805Snilay@cs.wisc.edu#include "base/misc.hh" 437632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/Check.hh" 447632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 458232Snate@binkert.org#include "debug/RubyTest.hh" 467053SN/A#include "mem/ruby/common/SubBlock.hh" 476899SN/A#include "sim/sim_exit.hh" 488832SAli.Saidi@ARM.com#include "sim/system.hh" 496899SN/A 506899SN/ARubyTester::RubyTester(const Params *p) 517053SN/A : MemObject(p), checkStartEvent(this), 528832SAli.Saidi@ARM.com _masterId(p->system->getMasterId(name())), 5310412Sandreas.hansson@arm.com m_checkTable_ptr(nullptr), 548932SBrad.Beckmann@amd.com m_num_cpus(p->num_cpus), 556899SN/A m_checks_to_complete(p->checks_to_complete), 566899SN/A m_deadlock_threshold(p->deadlock_threshold), 5710412Sandreas.hansson@arm.com m_num_writers(0), 5810412Sandreas.hansson@arm.com m_num_readers(0), 598184Ssomayeh@cs.wisc.edu m_wakeup_frequency(p->wakeup_frequency), 608932SBrad.Beckmann@amd.com m_check_flush(p->check_flush), 6111266SBrad.Beckmann@amd.com m_num_inst_only_ports(p->port_cpuInstPort_connection_count), 6211266SBrad.Beckmann@amd.com m_num_inst_data_ports(p->port_cpuInstDataPort_connection_count) 636899SN/A{ 647053SN/A m_checks_completed = 0; 656899SN/A 668932SBrad.Beckmann@amd.com // 678932SBrad.Beckmann@amd.com // Create the requested inst and data ports and place them on the 688932SBrad.Beckmann@amd.com // appropriate read and write port lists. The reason for the subtle 698932SBrad.Beckmann@amd.com // difference between inst and data ports vs. read and write ports is 708932SBrad.Beckmann@amd.com // from the tester's perspective, it only needs to know whether a port 718932SBrad.Beckmann@amd.com // supports reads (checks) or writes (actions). Meanwhile, the protocol 728932SBrad.Beckmann@amd.com // controllers have data ports (support read and writes) or inst ports 738932SBrad.Beckmann@amd.com // (support only reads). 748932SBrad.Beckmann@amd.com // Note: the inst ports are the lowest elements of the readPort vector, 758932SBrad.Beckmann@amd.com // then the data ports are added to the readPort vector 768932SBrad.Beckmann@amd.com // 7711266SBrad.Beckmann@amd.com int idx = 0; 788932SBrad.Beckmann@amd.com for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) { 798932SBrad.Beckmann@amd.com readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i), 8011266SBrad.Beckmann@amd.com this, i, idx)); 8111266SBrad.Beckmann@amd.com idx++; 8211266SBrad.Beckmann@amd.com } 8311266SBrad.Beckmann@amd.com for (int i = 0; i < p->port_cpuInstDataPort_connection_count; ++i) { 8411266SBrad.Beckmann@amd.com CpuPort *port = new CpuPort(csprintf("%s-instDataPort%d", name(), i), 8511266SBrad.Beckmann@amd.com this, i, idx); 8611266SBrad.Beckmann@amd.com readPorts.push_back(port); 8711266SBrad.Beckmann@amd.com writePorts.push_back(port); 8811266SBrad.Beckmann@amd.com idx++; 898932SBrad.Beckmann@amd.com } 908932SBrad.Beckmann@amd.com for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) { 918950Sandreas.hansson@arm.com CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i), 9211266SBrad.Beckmann@amd.com this, i, idx); 938932SBrad.Beckmann@amd.com readPorts.push_back(port); 948932SBrad.Beckmann@amd.com writePorts.push_back(port); 9511266SBrad.Beckmann@amd.com idx++; 968851Sandreas.hansson@arm.com } 978851Sandreas.hansson@arm.com 987053SN/A // add the check start event to the event queue 997053SN/A schedule(checkStartEvent, 1); 1006899SN/A} 1016899SN/A 1026899SN/ARubyTester::~RubyTester() 1036899SN/A{ 1047053SN/A delete m_checkTable_ptr; 1058932SBrad.Beckmann@amd.com // Only delete the readPorts since the writePorts are just a subset 1068932SBrad.Beckmann@amd.com for (int i = 0; i < readPorts.size(); i++) 1078932SBrad.Beckmann@amd.com delete readPorts[i]; 1086899SN/A} 1096899SN/A 1107053SN/Avoid 1117053SN/ARubyTester::init() 1126899SN/A{ 1138932SBrad.Beckmann@amd.com assert(writePorts.size() > 0 && readPorts.size() > 0); 1146899SN/A 1158932SBrad.Beckmann@amd.com m_last_progress_vector.resize(m_num_cpus); 1167053SN/A for (int i = 0; i < m_last_progress_vector.size(); i++) { 11710302Snilay@cs.wisc.edu m_last_progress_vector[i] = Cycles(0); 1187053SN/A } 1196899SN/A 1208932SBrad.Beckmann@amd.com m_num_writers = writePorts.size(); 1218932SBrad.Beckmann@amd.com m_num_readers = readPorts.size(); 12211266SBrad.Beckmann@amd.com assert(m_num_readers == m_num_cpus); 1236899SN/A 1248932SBrad.Beckmann@amd.com m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this); 1256899SN/A} 1266899SN/A 1279294Sandreas.hansson@arm.comBaseMasterPort & 1289294Sandreas.hansson@arm.comRubyTester::getMasterPort(const std::string &if_name, PortID idx) 1296899SN/A{ 13011266SBrad.Beckmann@amd.com if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" && 13111266SBrad.Beckmann@amd.com if_name != "cpuDataPort") { 1328922Swilliam.wang@arm.com // pass it along to our super class 1338922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1348922Swilliam.wang@arm.com } else { 1358932SBrad.Beckmann@amd.com if (if_name == "cpuInstPort") { 13611266SBrad.Beckmann@amd.com if (idx > m_num_inst_only_ports) { 13711266SBrad.Beckmann@amd.com panic("RubyTester::getMasterPort: unknown inst port %d\n", 1388932SBrad.Beckmann@amd.com idx); 1398932SBrad.Beckmann@amd.com } 1408932SBrad.Beckmann@amd.com // 14111266SBrad.Beckmann@amd.com // inst ports map to the lowest readPort elements 1428932SBrad.Beckmann@amd.com // 1438932SBrad.Beckmann@amd.com return *readPorts[idx]; 14411266SBrad.Beckmann@amd.com } else if (if_name == "cpuInstDataPort") { 14511266SBrad.Beckmann@amd.com if (idx > m_num_inst_data_ports) { 14611266SBrad.Beckmann@amd.com panic("RubyTester::getMasterPort: unknown inst+data port %d\n", 14711266SBrad.Beckmann@amd.com idx); 14811266SBrad.Beckmann@amd.com } 14911266SBrad.Beckmann@amd.com int read_idx = idx + m_num_inst_only_ports; 15011266SBrad.Beckmann@amd.com // 15111266SBrad.Beckmann@amd.com // inst+data ports map to the next readPort elements 15211266SBrad.Beckmann@amd.com // 15311266SBrad.Beckmann@amd.com return *readPorts[read_idx]; 1548932SBrad.Beckmann@amd.com } else { 1558932SBrad.Beckmann@amd.com assert(if_name == "cpuDataPort"); 1568932SBrad.Beckmann@amd.com // 15711266SBrad.Beckmann@amd.com // data only ports map to the final readPort elements 1588932SBrad.Beckmann@amd.com // 15911266SBrad.Beckmann@amd.com if (idx > (static_cast<int>(readPorts.size()) - 16011266SBrad.Beckmann@amd.com (m_num_inst_only_ports + m_num_inst_data_ports))) { 16111266SBrad.Beckmann@amd.com panic("RubyTester::getMasterPort: unknown data port %d\n", 1628932SBrad.Beckmann@amd.com idx); 1638932SBrad.Beckmann@amd.com } 16411266SBrad.Beckmann@amd.com int read_idx = idx + m_num_inst_only_ports + m_num_inst_data_ports; 1658932SBrad.Beckmann@amd.com return *readPorts[read_idx]; 1668922Swilliam.wang@arm.com } 16711266SBrad.Beckmann@amd.com // Note: currently the Ruby Tester does not support write only ports 16811266SBrad.Beckmann@amd.com // but that could easily be added here 1696899SN/A } 1706899SN/A} 1716899SN/A 1726899SN/Abool 1738975Sandreas.hansson@arm.comRubyTester::CpuPort::recvTimingResp(PacketPtr pkt) 1746899SN/A{ 1757053SN/A // retrieve the subblock and call hitCallback 1767053SN/A RubyTester::SenderState* senderState = 1777053SN/A safe_cast<RubyTester::SenderState*>(pkt->senderState); 1789542Sandreas.hansson@arm.com SubBlock& subblock = senderState->subBlock; 1796899SN/A 18011266SBrad.Beckmann@amd.com tester->hitCallback(globalIdx, &subblock); 1817053SN/A 1827053SN/A // Now that the tester has completed, delete the senderState 1837053SN/A // (includes sublock) and the packet, then return 1849542Sandreas.hansson@arm.com delete pkt->senderState; 1857053SN/A delete pkt->req; 1867053SN/A delete pkt; 1877053SN/A return true; 1886899SN/A} 1896899SN/A 1908950Sandreas.hansson@arm.combool 19111266SBrad.Beckmann@amd.comRubyTester::isInstOnlyCpuPort(int idx) 1928950Sandreas.hansson@arm.com{ 19311266SBrad.Beckmann@amd.com return idx < m_num_inst_only_ports; 19411266SBrad.Beckmann@amd.com} 19511266SBrad.Beckmann@amd.com 19611266SBrad.Beckmann@amd.combool 19711266SBrad.Beckmann@amd.comRubyTester::isInstDataCpuPort(int idx) 19811266SBrad.Beckmann@amd.com{ 19911266SBrad.Beckmann@amd.com return ((idx >= m_num_inst_only_ports) && 20011266SBrad.Beckmann@amd.com (idx < (m_num_inst_only_ports + m_num_inst_data_ports))); 2018950Sandreas.hansson@arm.com} 2028950Sandreas.hansson@arm.com 2038922Swilliam.wang@arm.comMasterPort* 2048932SBrad.Beckmann@amd.comRubyTester::getReadableCpuPort(int idx) 2056899SN/A{ 2068932SBrad.Beckmann@amd.com assert(idx >= 0 && idx < readPorts.size()); 2076899SN/A 2088932SBrad.Beckmann@amd.com return readPorts[idx]; 2098932SBrad.Beckmann@amd.com} 2108932SBrad.Beckmann@amd.com 2118932SBrad.Beckmann@amd.comMasterPort* 2128932SBrad.Beckmann@amd.comRubyTester::getWritableCpuPort(int idx) 2138932SBrad.Beckmann@amd.com{ 2148932SBrad.Beckmann@amd.com assert(idx >= 0 && idx < writePorts.size()); 2158932SBrad.Beckmann@amd.com 2168932SBrad.Beckmann@amd.com return writePorts[idx]; 2176899SN/A} 2186899SN/A 2197053SN/Avoid 2207053SN/ARubyTester::hitCallback(NodeID proc, SubBlock* data) 2216899SN/A{ 2227053SN/A // Mark that we made progress 2239475Snilay@cs.wisc.edu m_last_progress_vector[proc] = curCycle(); 2246899SN/A 22511266SBrad.Beckmann@amd.com DPRINTF(RubyTest, "completed request for proc: %d", proc); 22611266SBrad.Beckmann@amd.com DPRINTFR(RubyTest, " addr: 0x%x, size: %d, data: ", 2277053SN/A data->getAddress(), data->getSize()); 2287053SN/A for (int byte = 0; byte < data->getSize(); byte++) { 22911266SBrad.Beckmann@amd.com DPRINTFR(RubyTest, "%d ", data->getByte(byte)); 2307053SN/A } 23111266SBrad.Beckmann@amd.com DPRINTFR(RubyTest, "\n"); 2326899SN/A 2337053SN/A // This tells us our store has 'completed' or for a load gives us 2347053SN/A // back the data to make the check 2357053SN/A Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress()); 2367053SN/A assert(check_ptr != NULL); 2379475Snilay@cs.wisc.edu check_ptr->performCallback(proc, data, curCycle()); 2386899SN/A} 2396899SN/A 2407053SN/Avoid 2417053SN/ARubyTester::wakeup() 2427053SN/A{ 2437053SN/A if (m_checks_completed < m_checks_to_complete) { 2447053SN/A // Try to perform an action or check 2457053SN/A Check* check_ptr = m_checkTable_ptr->getRandomCheck(); 2467053SN/A assert(check_ptr != NULL); 2477053SN/A check_ptr->initiate(); 2487053SN/A 2497053SN/A checkForDeadlock(); 2507053SN/A 2517823Ssteve.reinhardt@amd.com schedule(checkStartEvent, curTick() + m_wakeup_frequency); 2527053SN/A } else { 2537053SN/A exitSimLoop("Ruby Tester completed"); 2547053SN/A } 2556899SN/A} 2566899SN/A 2577053SN/Avoid 2587053SN/ARubyTester::checkForDeadlock() 2596899SN/A{ 2607053SN/A int size = m_last_progress_vector.size(); 26110302Snilay@cs.wisc.edu Cycles current_time = curCycle(); 2627053SN/A for (int processor = 0; processor < size; processor++) { 2637053SN/A if ((current_time - m_last_progress_vector[processor]) > 2647053SN/A m_deadlock_threshold) { 2657805Snilay@cs.wisc.edu panic("Deadlock detected: current_time: %d last_progress_time: %d " 2667805Snilay@cs.wisc.edu "difference: %d processor: %d\n", 2677805Snilay@cs.wisc.edu current_time, m_last_progress_vector[processor], 2687805Snilay@cs.wisc.edu current_time - m_last_progress_vector[processor], processor); 2697053SN/A } 2706899SN/A } 2716899SN/A} 2726899SN/A 2737053SN/Avoid 2747055SN/ARubyTester::print(std::ostream& out) const 2756899SN/A{ 2767055SN/A out << "[RubyTester]" << std::endl; 2776899SN/A} 2786899SN/A 2796899SN/ARubyTester * 2806899SN/ARubyTesterParams::create() 2816899SN/A{ 2826899SN/A return new RubyTester(this); 2836899SN/A} 284