RubyTester.cc revision 11266
1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 15 * Copyright (c) 2009 Advanced Micro Devices, Inc. 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42#include "base/misc.hh" 43#include "cpu/testers/rubytest/Check.hh" 44#include "cpu/testers/rubytest/RubyTester.hh" 45#include "debug/RubyTest.hh" 46#include "mem/ruby/common/SubBlock.hh" 47#include "sim/sim_exit.hh" 48#include "sim/system.hh" 49 50RubyTester::RubyTester(const Params *p) 51 : MemObject(p), checkStartEvent(this), 52 _masterId(p->system->getMasterId(name())), 53 m_checkTable_ptr(nullptr), 54 m_num_cpus(p->num_cpus), 55 m_checks_to_complete(p->checks_to_complete), 56 m_deadlock_threshold(p->deadlock_threshold), 57 m_num_writers(0), 58 m_num_readers(0), 59 m_wakeup_frequency(p->wakeup_frequency), 60 m_check_flush(p->check_flush), 61 m_num_inst_only_ports(p->port_cpuInstPort_connection_count), 62 m_num_inst_data_ports(p->port_cpuInstDataPort_connection_count) 63{ 64 m_checks_completed = 0; 65 66 // 67 // Create the requested inst and data ports and place them on the 68 // appropriate read and write port lists. The reason for the subtle 69 // difference between inst and data ports vs. read and write ports is 70 // from the tester's perspective, it only needs to know whether a port 71 // supports reads (checks) or writes (actions). Meanwhile, the protocol 72 // controllers have data ports (support read and writes) or inst ports 73 // (support only reads). 74 // Note: the inst ports are the lowest elements of the readPort vector, 75 // then the data ports are added to the readPort vector 76 // 77 int idx = 0; 78 for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) { 79 readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i), 80 this, i, idx)); 81 idx++; 82 } 83 for (int i = 0; i < p->port_cpuInstDataPort_connection_count; ++i) { 84 CpuPort *port = new CpuPort(csprintf("%s-instDataPort%d", name(), i), 85 this, i, idx); 86 readPorts.push_back(port); 87 writePorts.push_back(port); 88 idx++; 89 } 90 for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) { 91 CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i), 92 this, i, idx); 93 readPorts.push_back(port); 94 writePorts.push_back(port); 95 idx++; 96 } 97 98 // add the check start event to the event queue 99 schedule(checkStartEvent, 1); 100} 101 102RubyTester::~RubyTester() 103{ 104 delete m_checkTable_ptr; 105 // Only delete the readPorts since the writePorts are just a subset 106 for (int i = 0; i < readPorts.size(); i++) 107 delete readPorts[i]; 108} 109 110void 111RubyTester::init() 112{ 113 assert(writePorts.size() > 0 && readPorts.size() > 0); 114 115 m_last_progress_vector.resize(m_num_cpus); 116 for (int i = 0; i < m_last_progress_vector.size(); i++) { 117 m_last_progress_vector[i] = Cycles(0); 118 } 119 120 m_num_writers = writePorts.size(); 121 m_num_readers = readPorts.size(); 122 assert(m_num_readers == m_num_cpus); 123 124 m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this); 125} 126 127BaseMasterPort & 128RubyTester::getMasterPort(const std::string &if_name, PortID idx) 129{ 130 if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" && 131 if_name != "cpuDataPort") { 132 // pass it along to our super class 133 return MemObject::getMasterPort(if_name, idx); 134 } else { 135 if (if_name == "cpuInstPort") { 136 if (idx > m_num_inst_only_ports) { 137 panic("RubyTester::getMasterPort: unknown inst port %d\n", 138 idx); 139 } 140 // 141 // inst ports map to the lowest readPort elements 142 // 143 return *readPorts[idx]; 144 } else if (if_name == "cpuInstDataPort") { 145 if (idx > m_num_inst_data_ports) { 146 panic("RubyTester::getMasterPort: unknown inst+data port %d\n", 147 idx); 148 } 149 int read_idx = idx + m_num_inst_only_ports; 150 // 151 // inst+data ports map to the next readPort elements 152 // 153 return *readPorts[read_idx]; 154 } else { 155 assert(if_name == "cpuDataPort"); 156 // 157 // data only ports map to the final readPort elements 158 // 159 if (idx > (static_cast<int>(readPorts.size()) - 160 (m_num_inst_only_ports + m_num_inst_data_ports))) { 161 panic("RubyTester::getMasterPort: unknown data port %d\n", 162 idx); 163 } 164 int read_idx = idx + m_num_inst_only_ports + m_num_inst_data_ports; 165 return *readPorts[read_idx]; 166 } 167 // Note: currently the Ruby Tester does not support write only ports 168 // but that could easily be added here 169 } 170} 171 172bool 173RubyTester::CpuPort::recvTimingResp(PacketPtr pkt) 174{ 175 // retrieve the subblock and call hitCallback 176 RubyTester::SenderState* senderState = 177 safe_cast<RubyTester::SenderState*>(pkt->senderState); 178 SubBlock& subblock = senderState->subBlock; 179 180 tester->hitCallback(globalIdx, &subblock); 181 182 // Now that the tester has completed, delete the senderState 183 // (includes sublock) and the packet, then return 184 delete pkt->senderState; 185 delete pkt->req; 186 delete pkt; 187 return true; 188} 189 190bool 191RubyTester::isInstOnlyCpuPort(int idx) 192{ 193 return idx < m_num_inst_only_ports; 194} 195 196bool 197RubyTester::isInstDataCpuPort(int idx) 198{ 199 return ((idx >= m_num_inst_only_ports) && 200 (idx < (m_num_inst_only_ports + m_num_inst_data_ports))); 201} 202 203MasterPort* 204RubyTester::getReadableCpuPort(int idx) 205{ 206 assert(idx >= 0 && idx < readPorts.size()); 207 208 return readPorts[idx]; 209} 210 211MasterPort* 212RubyTester::getWritableCpuPort(int idx) 213{ 214 assert(idx >= 0 && idx < writePorts.size()); 215 216 return writePorts[idx]; 217} 218 219void 220RubyTester::hitCallback(NodeID proc, SubBlock* data) 221{ 222 // Mark that we made progress 223 m_last_progress_vector[proc] = curCycle(); 224 225 DPRINTF(RubyTest, "completed request for proc: %d", proc); 226 DPRINTFR(RubyTest, " addr: 0x%x, size: %d, data: ", 227 data->getAddress(), data->getSize()); 228 for (int byte = 0; byte < data->getSize(); byte++) { 229 DPRINTFR(RubyTest, "%d ", data->getByte(byte)); 230 } 231 DPRINTFR(RubyTest, "\n"); 232 233 // This tells us our store has 'completed' or for a load gives us 234 // back the data to make the check 235 Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress()); 236 assert(check_ptr != NULL); 237 check_ptr->performCallback(proc, data, curCycle()); 238} 239 240void 241RubyTester::wakeup() 242{ 243 if (m_checks_completed < m_checks_to_complete) { 244 // Try to perform an action or check 245 Check* check_ptr = m_checkTable_ptr->getRandomCheck(); 246 assert(check_ptr != NULL); 247 check_ptr->initiate(); 248 249 checkForDeadlock(); 250 251 schedule(checkStartEvent, curTick() + m_wakeup_frequency); 252 } else { 253 exitSimLoop("Ruby Tester completed"); 254 } 255} 256 257void 258RubyTester::checkForDeadlock() 259{ 260 int size = m_last_progress_vector.size(); 261 Cycles current_time = curCycle(); 262 for (int processor = 0; processor < size; processor++) { 263 if ((current_time - m_last_progress_vector[processor]) > 264 m_deadlock_threshold) { 265 panic("Deadlock detected: current_time: %d last_progress_time: %d " 266 "difference: %d processor: %d\n", 267 current_time, m_last_progress_vector[processor], 268 current_time - m_last_progress_vector[processor], processor); 269 } 270 } 271} 272 273void 274RubyTester::print(std::ostream& out) const 275{ 276 out << "[RubyTester]" << std::endl; 277} 278 279RubyTester * 280RubyTesterParams::create() 281{ 282 return new RubyTester(this); 283} 284