memtest.hh revision 3187
18504SN/A/* 28504SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 38504SN/A * All rights reserved. 49885Sstever@gmail.com * 59885Sstever@gmail.com * Redistribution and use in source and binary forms, with or without 68504SN/A * modification, are permitted provided that the following conditions are 710451Snilay@cs.wisc.edu * met: redistributions of source code must retain the above copyright 89901Sandreas@sandberg.pp.se * notice, this list of conditions and the following disclaimer; 99901Sandreas@sandberg.pp.se * redistributions in binary form must reproduce the above copyright 109901Sandreas@sandberg.pp.se * notice, this list of conditions and the following disclaimer in the 118504SN/A * documentation and/or other materials provided with the distribution; 128504SN/A * neither the name of the copyright holders nor the names of its 139885Sstever@gmail.com * contributors may be used to endorse or promote products derived from 148504SN/A * this software without specific prior written permission. 158504SN/A * 169885Sstever@gmail.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179885Sstever@gmail.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188504SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198504SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208504SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218504SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228504SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238504SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248504SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259885Sstever@gmail.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269885Sstever@gmail.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710451Snilay@cs.wisc.edu * 2810451Snilay@cs.wisc.edu * Authors: Erik Hallnor 298504SN/A * Steve Reinhardt 308504SN/A */ 318504SN/A 3210451Snilay@cs.wisc.edu#ifndef __CPU_MEMTEST_MEMTEST_HH__ 338504SN/A#define __CPU_MEMTEST_MEMTEST_HH__ 348504SN/A 358504SN/A#include <set> 368504SN/A 378504SN/A#include "base/statistics.hh" 3810451Snilay@cs.wisc.edu//#include "mem/functional/functional.hh" 398504SN/A//#include "mem/mem_interface.hh" 408504SN/A#include "sim/eventq.hh" 418504SN/A#include "sim/sim_exit.hh" 428504SN/A#include "sim/sim_object.hh" 438504SN/A#include "sim/stats.hh" 448504SN/A#include "mem/mem_object.hh" 458504SN/A#include "mem/port.hh" 468504SN/A 478504SN/Aclass Packet; 4810451Snilay@cs.wisc.educlass MemTest : public MemObject 498504SN/A{ 508504SN/A public: 518504SN/A 528504SN/A MemTest(const std::string &name, 538504SN/A// MemInterface *_cache_interface, 548504SN/A// PhysicalMemory *main_mem, 558504SN/A// PhysicalMemory *check_mem, 568504SN/A unsigned _memorySize, 578504SN/A unsigned _percentReads, 588504SN/A// unsigned _percentCopies, 598504SN/A unsigned _percentUncacheable, 6010451Snilay@cs.wisc.edu unsigned _progressInterval, 618504SN/A unsigned _percentSourceUnaligned, 628504SN/A unsigned _percentDestUnaligned, 638504SN/A Addr _traceAddr, 648504SN/A Counter _max_loads); 658504SN/A 668504SN/A virtual void init(); 678504SN/A 688504SN/A // register statistics 698504SN/A virtual void regStats(); 708504SN/A 718504SN/A inline Tick cycles(int numCycles) const { return numCycles; } 728504SN/A 738504SN/A // main simulation loop (one cycle) 748504SN/A void tick(); 758504SN/A 768504SN/A virtual Port *getPort(const std::string &if_name, int idx = -1); 778504SN/A 788504SN/A protected: 798504SN/A class TickEvent : public Event 808504SN/A { 818504SN/A private: 828504SN/A MemTest *cpu; 838504SN/A public: 848504SN/A TickEvent(MemTest *c) 858504SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {} 868504SN/A void process() {cpu->tick();} 878504SN/A virtual const char *description() { return "tick event"; } 888504SN/A }; 898504SN/A 908504SN/A TickEvent tickEvent; 918504SN/A class CpuPort : public Port 928504SN/A { 938504SN/A 948504SN/A MemTest *memtest; 958504SN/A 968504SN/A public: 978504SN/A 988504SN/A CpuPort(const std::string &_name, MemTest *_memtest) 998504SN/A : Port(_name), memtest(_memtest) 1008504SN/A { } 1018504SN/A 1028504SN/A protected: 1038504SN/A 1048504SN/A virtual bool recvTiming(Packet *pkt); 1058504SN/A 1068504SN/A virtual Tick recvAtomic(Packet *pkt); 1078504SN/A 1088504SN/A virtual void recvFunctional(Packet *pkt); 1098504SN/A 1108504SN/A virtual void recvStatusChange(Status status); 1118504SN/A 1128504SN/A virtual void recvRetry(); 1138504SN/A 1148504SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 1158504SN/A AddrRangeList &snoop) 1168504SN/A { resp.clear(); snoop.clear(); } 1178504SN/A }; 1188504SN/A 1198504SN/A CpuPort cachePort; 1208504SN/A CpuPort funcPort; 1218504SN/A 1228504SN/A class MemTestSenderState : public Packet::SenderState 1238504SN/A { 1248504SN/A public: 1258504SN/A /** Constructor. */ 1268504SN/A MemTestSenderState(uint8_t *_data) 1278504SN/A : data(_data) 1288504SN/A { } 1298504SN/A 1308504SN/A // Hold onto data pointer 1318504SN/A uint8_t *data; 1328504SN/A }; 1338504SN/A 1348504SN/A// Request *dataReq; 1358504SN/A Packet *retryPkt; 1368504SN/A// MemInterface *cacheInterface; 1378504SN/A// PhysicalMemory *mainMem; 1388504SN/A// PhysicalMemory *checkMem; 1398504SN/A// SimpleThread *thread; 1408504SN/A 14110451Snilay@cs.wisc.edu bool accessRetry; 14210451Snilay@cs.wisc.edu 143 unsigned size; // size of testing memory region 144 145 unsigned percentReads; // target percentage of read accesses 146// unsigned percentCopies; // target percentage of copy accesses 147 unsigned percentUncacheable; 148 149 int id; 150 151 std::set<unsigned> outstandingAddrs; 152 153 unsigned blockSize; 154 155 Addr blockAddrMask; 156 157 Addr blockAddr(Addr addr) 158 { 159 return (addr & ~blockAddrMask); 160 } 161 162 Addr traceBlockAddr; 163 164 Addr baseAddr1; // fix this to option 165 Addr baseAddr2; // fix this to option 166 Addr uncacheAddr; 167 168 unsigned progressInterval; // frequency of progress reports 169 Tick nextProgressMessage; // access # for next progress report 170 171 unsigned percentSourceUnaligned; 172 unsigned percentDestUnaligned; 173 174 Tick noResponseCycles; 175 176 uint64_t numReads; 177 uint64_t maxLoads; 178 Stats::Scalar<> numReadsStat; 179 Stats::Scalar<> numWritesStat; 180 Stats::Scalar<> numCopiesStat; 181 182 // called by MemCompleteEvent::process() 183 void completeRequest(Packet *pkt); 184 185 void doRetry(); 186 187 friend class MemCompleteEvent; 188}; 189 190#endif // __CPU_MEMTEST_MEMTEST_HH__ 191 192 193 194