memtest.hh revision 3187 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Steve Reinhardt
30 */
31
32#ifndef __CPU_MEMTEST_MEMTEST_HH__
33#define __CPU_MEMTEST_MEMTEST_HH__
34
35#include <set>
36
37#include "base/statistics.hh"
38//#include "mem/functional/functional.hh"
39//#include "mem/mem_interface.hh"
40#include "sim/eventq.hh"
41#include "sim/sim_exit.hh"
42#include "sim/sim_object.hh"
43#include "sim/stats.hh"
44#include "mem/mem_object.hh"
45#include "mem/port.hh"
46
47class Packet;
48class MemTest : public MemObject
49{
50  public:
51
52    MemTest(const std::string &name,
53//	    MemInterface *_cache_interface,
54//	    PhysicalMemory *main_mem,
55//	    PhysicalMemory *check_mem,
56            unsigned _memorySize,
57            unsigned _percentReads,
58//	    unsigned _percentCopies,
59            unsigned _percentUncacheable,
60            unsigned _progressInterval,
61            unsigned _percentSourceUnaligned,
62            unsigned _percentDestUnaligned,
63            Addr _traceAddr,
64            Counter _max_loads);
65
66    virtual void init();
67
68    // register statistics
69    virtual void regStats();
70
71    inline Tick cycles(int numCycles) const { return numCycles; }
72
73    // main simulation loop (one cycle)
74    void tick();
75
76    virtual Port *getPort(const std::string &if_name, int idx = -1);
77
78  protected:
79    class TickEvent : public Event
80    {
81      private:
82        MemTest *cpu;
83      public:
84        TickEvent(MemTest *c)
85            : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {}
86        void process() {cpu->tick();}
87        virtual const char *description() { return "tick event"; }
88    };
89
90    TickEvent tickEvent;
91    class CpuPort : public Port
92    {
93
94        MemTest *memtest;
95
96      public:
97
98        CpuPort(const std::string &_name, MemTest *_memtest)
99            : Port(_name), memtest(_memtest)
100        { }
101
102      protected:
103
104        virtual bool recvTiming(Packet *pkt);
105
106        virtual Tick recvAtomic(Packet *pkt);
107
108        virtual void recvFunctional(Packet *pkt);
109
110        virtual void recvStatusChange(Status status);
111
112        virtual void recvRetry();
113
114        virtual void getDeviceAddressRanges(AddrRangeList &resp,
115            AddrRangeList &snoop)
116        { resp.clear(); snoop.clear(); }
117    };
118
119    CpuPort cachePort;
120    CpuPort funcPort;
121
122    class MemTestSenderState : public Packet::SenderState
123    {
124      public:
125        /** Constructor. */
126        MemTestSenderState(uint8_t *_data)
127            : data(_data)
128        { }
129
130        // Hold onto data pointer
131        uint8_t *data;
132    };
133
134//    Request *dataReq;
135    Packet  *retryPkt;
136//    MemInterface *cacheInterface;
137//    PhysicalMemory *mainMem;
138//    PhysicalMemory *checkMem;
139//    SimpleThread *thread;
140
141    bool accessRetry;
142
143    unsigned size;		// size of testing memory region
144
145    unsigned percentReads;	// target percentage of read accesses
146//    unsigned percentCopies;	// target percentage of copy accesses
147    unsigned percentUncacheable;
148
149    int id;
150
151    std::set<unsigned> outstandingAddrs;
152
153    unsigned blockSize;
154
155    Addr blockAddrMask;
156
157    Addr blockAddr(Addr addr)
158    {
159        return (addr & ~blockAddrMask);
160    }
161
162    Addr traceBlockAddr;
163
164    Addr baseAddr1;		// fix this to option
165    Addr baseAddr2;		// fix this to option
166    Addr uncacheAddr;
167
168    unsigned progressInterval;	// frequency of progress reports
169    Tick nextProgressMessage;	// access # for next progress report
170
171    unsigned percentSourceUnaligned;
172    unsigned percentDestUnaligned;
173
174    Tick noResponseCycles;
175
176    uint64_t numReads;
177    uint64_t maxLoads;
178    Stats::Scalar<> numReadsStat;
179    Stats::Scalar<> numWritesStat;
180    Stats::Scalar<> numCopiesStat;
181
182    // called by MemCompleteEvent::process()
183    void completeRequest(Packet *pkt);
184
185    void doRetry();
186
187    friend class MemCompleteEvent;
188};
189
190#endif // __CPU_MEMTEST_MEMTEST_HH__
191
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