MemTest.py revision 4486
16145SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan
26386SN/A# All rights reserved.
37553SN/A#
46386SN/A# Redistribution and use in source and binary forms, with or without
56386SN/A# modification, are permitted provided that the following conditions are
66386SN/A# met: redistributions of source code must retain the above copyright
76386SN/A# notice, this list of conditions and the following disclaimer;
86386SN/A# redistributions in binary form must reproduce the above copyright
96386SN/A# notice, this list of conditions and the following disclaimer in the
106386SN/A# documentation and/or other materials provided with the distribution;
116386SN/A# neither the name of the copyright holders nor the names of its
126386SN/A# contributors may be used to endorse or promote products derived from
136386SN/A# this software without specific prior written permission.
146386SN/A#
156386SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
166386SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
176386SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
186386SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
196386SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
206386SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
216386SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
226386SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
236386SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
246386SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
256386SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
266386SN/A#
276386SN/A# Authors: Nathan Binkert
286386SN/A
296145SN/Afrom m5.SimObject import SimObject
3011793Sbrandon.potter@amd.comfrom m5.params import *
3111793Sbrandon.potter@amd.comfrom m5.proxy import *
3210348Sandreas.hansson@arm.comfrom m5 import build_env
337632SBrad.Beckmann@amd.com
347632SBrad.Beckmann@amd.comclass MemTest(SimObject):
358232Snate@binkert.org    type = 'MemTest'
366145SN/A    max_loads = Param.Counter("number of loads to execute")
377553SN/A    atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")
389365Snilay@cs.wisc.edu    memory_size = Param.Int(65536, "memory size")
399365Snilay@cs.wisc.edu    percent_dest_unaligned = Param.Percent(50,
409365Snilay@cs.wisc.edu        "percent of copy dest address that are unaligned")
416145SN/A    percent_reads = Param.Percent(65, "target read percentage")
427553SN/A    percent_source_unaligned = Param.Percent(50,
437553SN/A        "percent of copy source address that are unaligned")
447553SN/A    percent_functional = Param.Percent(50, "percent of access that are functional")
456145SN/A    percent_uncacheable = Param.Percent(10,
466145SN/A        "target uncacheable percentage")
477553SN/A    progress_interval = Param.Counter(1000000,
486145SN/A        "progress report interval (in accesses)")
496145SN/A    trace_addr = Param.Addr(0, "address to trace")
506145SN/A
517553SN/A    test = Port("Port to the memory system to test")
527553SN/A    functional = Port("Port to the functional memory used for verification")
536145SN/A