RubyDirectedTester.cc revision 7553
18504SN/A/*
28504SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
38504SN/A * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
48825Snilay@cs.wisc.edu * All rights reserved.
58504SN/A *
68504SN/A * Redistribution and use in source and binary forms, with or without
78504SN/A * modification, are permitted provided that the following conditions are
88504SN/A * met: redistributions of source code must retain the above copyright
98504SN/A * notice, this list of conditions and the following disclaimer;
108504SN/A * redistributions in binary form must reproduce the above copyright
119348SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the
128504SN/A * documentation and/or other materials provided with the distribution;
138504SN/A * neither the name of the copyright holders nor the names of its
149348SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from
158504SN/A * this software without specific prior written permission.
168504SN/A *
178504SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
188504SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
199620Snilay@cs.wisc.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
208504SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
218504SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
229449SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
238504SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
248673SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
258504SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
268504SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
278504SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
288504SN/A */
298504SN/A
308504SN/A#include "cpu/directedtest/RubyDirectedTester.hh"
318504SN/A#include "cpu/directedtest/DirectedGenerator.hh"
328504SN/A#include "mem/ruby/eventqueue/RubyEventQueue.hh"
338504SN/A#include "sim/sim_exit.hh"
348504SN/A
358963Sgblack@eecs.umich.eduRubyDirectedTester::RubyDirectedTester(const Params *p)
368504SN/A  : MemObject(p), directedStartEvent(this),
378504SN/A    m_requests_to_complete(p->requests_to_complete),
388504SN/A    generator(p->generator)
398504SN/A{
408504SN/A    m_requests_completed = 0;
418504SN/A
428504SN/A    // add the check start event to the event queue
438504SN/A    schedule(directedStartEvent, 1);
448504SN/A}
458504SN/A
468504SN/ARubyDirectedTester::~RubyDirectedTester()
478504SN/A{
488504SN/A    for (int i = 0; i < ports.size(); i++)
498504SN/A        delete ports[i];
508504SN/A}
518504SN/A
528504SN/Avoid
538504SN/ARubyDirectedTester::init()
548835SAli.Saidi@ARM.com{
558835SAli.Saidi@ARM.com    assert(ports.size() > 0);
569348SAli.Saidi@ARM.com    generator->setDirectedTester(this);
578835SAli.Saidi@ARM.com}
588835SAli.Saidi@ARM.com
598835SAli.Saidi@ARM.comPort *
608835SAli.Saidi@ARM.comRubyDirectedTester::getPort(const std::string &if_name, int idx)
618963Sgblack@eecs.umich.edu{
628963Sgblack@eecs.umich.edu    if (if_name != "cpuPort") {
638835SAli.Saidi@ARM.com        panic("RubyDirectedTester::getPort: unknown port %s requested", if_name);
648504SN/A    }
658504SN/A
669348SAli.Saidi@ARM.com    if (idx >= (int)ports.size()) {
678504SN/A        ports.resize(idx + 1);
688721SN/A    }
698721SN/A
708721SN/A    if (ports[idx] != NULL) {
718963Sgblack@eecs.umich.edu        panic("RubyDirectedTester::getPort: port %d already assigned", idx);
728963Sgblack@eecs.umich.edu    }
738504SN/A
748504SN/A    CpuPort *port = new CpuPort(csprintf("%s-port%d", name(), idx), this, idx);
758504SN/A
769481Snilay@cs.wisc.edu    ports[idx] = port;
778504SN/A    return port;
788504SN/A}
798504SN/A
808504SN/ATick
818504SN/ARubyDirectedTester::CpuPort::recvAtomic(PacketPtr pkt)
828504SN/A{
838504SN/A    panic("RubyDirectedTester::CpuPort::recvAtomic() not implemented!\n");
848504SN/A    return 0;
859481Snilay@cs.wisc.edu}
868504SN/A
878504SN/Abool
888504SN/ARubyDirectedTester::CpuPort::recvTiming(PacketPtr pkt)
898504SN/A{
908504SN/A    tester->hitCallback(idx, pkt->getAddr());
918504SN/A
928504SN/A    //
938504SN/A    // Now that the tester has completed, delete the packet, then return
948504SN/A    //
958504SN/A    delete pkt->req;
968504SN/A    delete pkt;
978504SN/A    return true;
988504SN/A}
998504SN/A
1008504SN/APort*
1018504SN/ARubyDirectedTester::getCpuPort(int idx)
1028504SN/A{
1038504SN/A    assert(idx >= 0 && idx < ports.size());
1048504SN/A
1058504SN/A    return ports[idx];
1068504SN/A}
1078504SN/A
1088504SN/Avoid
1098504SN/ARubyDirectedTester::hitCallback(NodeID proc, Addr addr)
1108504SN/A{
1118504SN/A    DPRINTF(DirectedTest,
1128504SN/A            "completed request for proc: %d addr: 0x%x\n",
1138504SN/A            proc,
1148504SN/A            addr);
1159348SAli.Saidi@ARM.com
1168504SN/A    generator->performCallback(proc, addr);
1178504SN/A    schedule(directedStartEvent, curTick);
1188504SN/A}
1198504SN/A
1208504SN/Avoid
1218504SN/ARubyDirectedTester::wakeup()
1228504SN/A{
1238728SN/A    if (m_requests_completed < m_requests_to_complete) {
1248504SN/A        if (!generator->initiate()) {
1258504SN/A            schedule(directedStartEvent, curTick + 1);
1268504SN/A        }
1278504SN/A    } else {
1288504SN/A        exitSimLoop("Ruby DirectedTester completed");
1298504SN/A    }
1308504SN/A}
1318504SN/A
1328504SN/ARubyDirectedTester *
1338504SN/ARubyDirectedTesterParams::create()
1348504SN/A{
1358504SN/A    return new RubyDirectedTester(this);
1368504SN/A}
1378504SN/A