simple_thread.hh revision 13905
12SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Steve Reinhardt 422665SN/A * Nathan Binkert 432SN/A */ 442SN/A 452683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 462683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 472SN/A 489020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 4912406Sgabeblack@google.com#include "arch/generic/tlb.hh" 506313Sgblack@eecs.umich.edu#include "arch/isa.hh" 512190SN/A#include "arch/isa_traits.hh" 526329Sgblack@eecs.umich.edu#include "arch/registers.hh" 536316Sgblack@eecs.umich.edu#include "arch/types.hh" 546216Snate@binkert.org#include "base/types.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 562680SN/A#include "cpu/thread_context.hh" 572683Sktlim@umich.edu#include "cpu/thread_state.hh" 589920Syasuko.eckert@amd.com#include "debug/CCRegs.hh" 598232Snate@binkert.org#include "debug/FloatRegs.hh" 608232Snate@binkert.org#include "debug/IntRegs.hh" 6113610Sgiacomo.gabrielli@arm.com#include "debug/VecPredRegs.hh" 6212109SRekai.GonzalezAlberquilla@arm.com#include "debug/VecRegs.hh" 638777Sgblack@eecs.umich.edu#include "mem/page_table.hh" 642395SN/A#include "mem/request.hh" 652190SN/A#include "sim/byteswap.hh" 662188SN/A#include "sim/eventq.hh" 678777Sgblack@eecs.umich.edu#include "sim/process.hh" 68217SN/A#include "sim/serialize.hh" 698777Sgblack@eecs.umich.edu#include "sim/system.hh" 702SN/A 712SN/Aclass BaseCPU; 728887Sgeoffrey.blake@arm.comclass CheckerCPU; 731070SN/A 741917SN/Aclass FunctionProfile; 751917SN/Aclass ProfileNode; 762521SN/A 7713905Sgabeblack@google.comnamespace Kernel { 7813905Sgabeblack@google.com class Statistics; 798902Sandreas.hansson@arm.com} 802330SN/A 812683Sktlim@umich.edu/** 822683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 832683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 8413865Sgabeblack@google.com * ThreadContext interface and adds to the ThreadState object by adding all 852683Sktlim@umich.edu * the objects needed for simple functional execution, including a 862683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 872683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 882683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 892683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 902683Sktlim@umich.edu * all the necessary state for full architecture-level functional 912683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 922683Sktlim@umich.edu * examples. 932683Sktlim@umich.edu */ 942SN/A 9513865Sgabeblack@google.comclass SimpleThread : public ThreadState, public ThreadContext 962SN/A{ 972107SN/A protected: 982107SN/A typedef TheISA::MachInst MachInst; 9912109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 10012109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 10113610Sgiacomo.gabrielli@arm.com using VecPredRegContainer = TheISA::VecPredRegContainer; 1022SN/A public: 1032680SN/A typedef ThreadContext::Status Status; 1042SN/A 1052190SN/A protected: 10613557Sgabeblack@google.com RegVal floatRegs[TheISA::NumFloatRegs]; 10713557Sgabeblack@google.com RegVal intRegs[TheISA::NumIntRegs]; 10812109SRekai.GonzalezAlberquilla@arm.com VecRegContainer vecRegs[TheISA::NumVecRegs]; 10913610Sgiacomo.gabrielli@arm.com VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs]; 1109920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 11113622Sgabeblack@google.com RegVal ccRegs[TheISA::NumCCRegs]; 1129920Syasuko.eckert@amd.com#endif 1139384SAndreas.Sandberg@arm.com TheISA::ISA *const isa; // one "instance" of the current ISA. 1142SN/A 1157720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1166324Sgblack@eecs.umich.edu 1177597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1187597Sminkyu.jeong@arm.com bool predicate; 1197597Sminkyu.jeong@arm.com 1202190SN/A public: 1218357Sksewell@umich.edu std::string name() const 1228357Sksewell@umich.edu { 12313865Sgabeblack@google.com return csprintf("%s.[tid:%i]", baseCpu->name(), threadId()); 1248357Sksewell@umich.edu } 1258357Sksewell@umich.edu 1262378SN/A System *system; 1272400SN/A 12812406Sgabeblack@google.com BaseTLB *itb; 12912406Sgabeblack@google.com BaseTLB *dtb; 1302SN/A 1319020Sgblack@eecs.umich.edu TheISA::Decoder decoder; 1328541Sgblack@eecs.umich.edu 1332683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1348793Sgblack@eecs.umich.edu // FS 1352683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 13612406Sgabeblack@google.com BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, 1372683Sktlim@umich.edu bool use_kernel_stats = true); 1388793Sgblack@eecs.umich.edu // SE 1398820Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 14012406Sgabeblack@google.com Process *_process, BaseTLB *_itb, BaseTLB *_dtb, 1419384SAndreas.Sandberg@arm.com TheISA::ISA *_isa); 1422862Sktlim@umich.edu 14313865Sgabeblack@google.com virtual ~SimpleThread() {} 1442SN/A 14513865Sgabeblack@google.com void takeOverFrom(ThreadContext *oldContext) override; 146180SN/A 14713865Sgabeblack@google.com void regStats(const std::string &name) override; 1482SN/A 1492862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1502862Sktlim@umich.edu 15111168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 15211168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1539461Snilay@cs.wisc.edu void startup(); 154217SN/A 1552683Sktlim@umich.edu /*************************************************************** 1562683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1575891Sgblack@eecs.umich.edu * state. 1582683Sktlim@umich.edu **************************************************************/ 1592190SN/A 1602683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1612683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1622683Sktlim@umich.edu * CPU. 1632683Sktlim@umich.edu */ 16413865Sgabeblack@google.com ThreadContext *getTC() { return this; } 1652190SN/A 1665358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1675358Sgblack@eecs.umich.edu { 1685358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1695358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1705358Sgblack@eecs.umich.edu } 1715358Sgblack@eecs.umich.edu 1725358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1735358Sgblack@eecs.umich.edu { 1745358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1755358Sgblack@eecs.umich.edu } 1765358Sgblack@eecs.umich.edu 1775358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1785358Sgblack@eecs.umich.edu { 1795358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1805358Sgblack@eecs.umich.edu } 1815358Sgblack@eecs.umich.edu 18213865Sgabeblack@google.com void dumpFuncProfile() override; 1832521SN/A 1845702Ssaidi@eecs.umich.edu Fault hwrei(); 1855702Ssaidi@eecs.umich.edu 1865702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1875702Ssaidi@eecs.umich.edu 1882683Sktlim@umich.edu /******************************************* 1892683Sktlim@umich.edu * ThreadContext interface functions. 1902683Sktlim@umich.edu ******************************************/ 1912683Sktlim@umich.edu 19213865Sgabeblack@google.com BaseCPU *getCpuPtr() override { return baseCpu; } 1932683Sktlim@umich.edu 19413865Sgabeblack@google.com int cpuId() const override { return ThreadState::cpuId(); } 19513865Sgabeblack@google.com uint32_t socketId() const override { return ThreadState::socketId(); } 19613865Sgabeblack@google.com int threadId() const override { return ThreadState::threadId(); } 19713865Sgabeblack@google.com void setThreadId(int id) override { ThreadState::setThreadId(id); } 19813865Sgabeblack@google.com ContextID contextId() const override { return ThreadState::contextId(); } 19913865Sgabeblack@google.com void setContextId(ContextID id) override { ThreadState::setContextId(id); } 2002683Sktlim@umich.edu 20113865Sgabeblack@google.com BaseTLB *getITBPtr() override { return itb; } 2022683Sktlim@umich.edu 20313865Sgabeblack@google.com BaseTLB *getDTBPtr() override { return dtb; } 2048733Sgeoffrey.blake@arm.com 20513865Sgabeblack@google.com CheckerCPU *getCheckerCpuPtr() override { return NULL; } 20613693Sgiacomo.gabrielli@arm.com 20713865Sgabeblack@google.com TheISA::ISA *getIsaPtr() override { return isa; } 2088541Sgblack@eecs.umich.edu 20913865Sgabeblack@google.com TheISA::Decoder *getDecoderPtr() override { return &decoder; } 2104997Sgblack@eecs.umich.edu 21113865Sgabeblack@google.com System *getSystemPtr() override { return system; } 2122683Sktlim@umich.edu 21313905Sgabeblack@google.com Kernel::Statistics * 21413875SAndrea.Mondelli@ucf.edu getKernelStats() override 21513865Sgabeblack@google.com { 21613865Sgabeblack@google.com return ThreadState::getKernelStats(); 21713865Sgabeblack@google.com } 21813865Sgabeblack@google.com 21913875SAndrea.Mondelli@ucf.edu PortProxy &getPhysProxy() override { return ThreadState::getPhysProxy(); } 22013865Sgabeblack@google.com FSTranslatingPortProxy & 22113875SAndrea.Mondelli@ucf.edu getVirtProxy() override 22213865Sgabeblack@google.com { 22313865Sgabeblack@google.com return ThreadState::getVirtProxy(); 22413865Sgabeblack@google.com } 22513865Sgabeblack@google.com 22613875SAndrea.Mondelli@ucf.edu void initMemProxies(ThreadContext *tc) override 22713875SAndrea.Mondelli@ucf.edu { 22813875SAndrea.Mondelli@ucf.edu ThreadState::initMemProxies(tc); 22913875SAndrea.Mondelli@ucf.edu } 23013875SAndrea.Mondelli@ucf.edu 23113865Sgabeblack@google.com SETranslatingPortProxy & 23213875SAndrea.Mondelli@ucf.edu getMemProxy() override 23313865Sgabeblack@google.com { 23413865Sgabeblack@google.com return ThreadState::getMemProxy(); 23513865Sgabeblack@google.com } 23613865Sgabeblack@google.com 23713875SAndrea.Mondelli@ucf.edu Process *getProcessPtr() override { return ThreadState::getProcessPtr(); } 23813865Sgabeblack@google.com void setProcessPtr(Process *p) override { ThreadState::setProcessPtr(p); } 23913865Sgabeblack@google.com 24013865Sgabeblack@google.com Status status() const override { return _status; } 24113865Sgabeblack@google.com 24213865Sgabeblack@google.com void setStatus(Status newStatus) override { _status = newStatus; } 2432683Sktlim@umich.edu 24410407Smitch.hayenga@arm.com /// Set the status to Active. 24513865Sgabeblack@google.com void activate() override; 2462683Sktlim@umich.edu 2472683Sktlim@umich.edu /// Set the status to Suspended. 24813865Sgabeblack@google.com void suspend() override; 2492683Sktlim@umich.edu 2502683Sktlim@umich.edu /// Set the status to Halted. 25113865Sgabeblack@google.com void halt() override; 2522683Sktlim@umich.edu 25313865Sgabeblack@google.com EndQuiesceEvent * 25413865Sgabeblack@google.com getQuiesceEvent() override 25513865Sgabeblack@google.com { 25613865Sgabeblack@google.com return ThreadState::getQuiesceEvent(); 25713865Sgabeblack@google.com } 2582190SN/A 25913865Sgabeblack@google.com Tick 26013865Sgabeblack@google.com readLastActivate() override 26113865Sgabeblack@google.com { 26213865Sgabeblack@google.com return ThreadState::readLastActivate(); 26313865Sgabeblack@google.com } 26413865Sgabeblack@google.com Tick 26513865Sgabeblack@google.com readLastSuspend() override 26613865Sgabeblack@google.com { 26713865Sgabeblack@google.com return ThreadState::readLastSuspend(); 26813865Sgabeblack@google.com } 26913865Sgabeblack@google.com 27013865Sgabeblack@google.com void profileClear() override { ThreadState::profileClear(); } 27113865Sgabeblack@google.com void profileSample() override { ThreadState::profileSample(); } 27213865Sgabeblack@google.com 27313865Sgabeblack@google.com void copyArchRegs(ThreadContext *tc) override; 27413865Sgabeblack@google.com 27513865Sgabeblack@google.com void clearArchRegs() override 2766315Sgblack@eecs.umich.edu { 2777720Sgblack@eecs.umich.edu _pcState = 0; 2786316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 27913501Sgabeblack@google.com memset(floatRegs, 0, sizeof(floatRegs)); 28012109SRekai.GonzalezAlberquilla@arm.com for (int i = 0; i < TheISA::NumVecRegs; i++) { 28112109SRekai.GonzalezAlberquilla@arm.com vecRegs[i].zero(); 28212109SRekai.GonzalezAlberquilla@arm.com } 28313610Sgiacomo.gabrielli@arm.com for (int i = 0; i < TheISA::NumVecPredRegs; i++) { 28413610Sgiacomo.gabrielli@arm.com vecPredRegs[i].reset(); 28513610Sgiacomo.gabrielli@arm.com } 2869920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 2879920Syasuko.eckert@amd.com memset(ccRegs, 0, sizeof(ccRegs)); 2889920Syasuko.eckert@amd.com#endif 2899384SAndreas.Sandberg@arm.com isa->clear(); 2906315Sgblack@eecs.umich.edu } 2912190SN/A 2922SN/A // 2932SN/A // New accessors for new decoder. 2942SN/A // 29513557Sgabeblack@google.com RegVal 29613865Sgabeblack@google.com readIntReg(RegIndex reg_idx) const override 2972SN/A { 2989384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 2996323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 3009426SAndreas.Sandberg@ARM.com uint64_t regVal(readIntRegFlat(flatIndex)); 3017601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 3027601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 3036418Sgblack@eecs.umich.edu return regVal; 3042SN/A } 3052SN/A 30613557Sgabeblack@google.com RegVal 30713865Sgabeblack@google.com readFloatReg(RegIndex reg_idx) const override 3082455SN/A { 3099384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 3106323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 31113611Sgabeblack@google.com RegVal regVal(readFloatRegFlat(flatIndex)); 31213501Sgabeblack@google.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 31313501Sgabeblack@google.com reg_idx, flatIndex, regVal); 3147341Sgblack@eecs.umich.edu return regVal; 3152SN/A } 3162SN/A 31712109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& 31813865Sgabeblack@google.com readVecReg(const RegId& reg) const override 31912109SRekai.GonzalezAlberquilla@arm.com { 32012109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 32112109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 32212109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& regVal = readVecRegFlat(flatIndex); 32312109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 32413610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, regVal.print()); 32512109SRekai.GonzalezAlberquilla@arm.com return regVal; 32612109SRekai.GonzalezAlberquilla@arm.com } 32712109SRekai.GonzalezAlberquilla@arm.com 32812109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& 32913865Sgabeblack@google.com getWritableVecReg(const RegId& reg) override 33012109SRekai.GonzalezAlberquilla@arm.com { 33112109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 33212109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 33312109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 33412109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 33513610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, regVal.print()); 33612109SRekai.GonzalezAlberquilla@arm.com return regVal; 33712109SRekai.GonzalezAlberquilla@arm.com } 33812109SRekai.GonzalezAlberquilla@arm.com 33912109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 34012109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 34112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector <T> operand. */ 34212109SRekai.GonzalezAlberquilla@arm.com template <typename T> 34312109SRekai.GonzalezAlberquilla@arm.com VecLaneT<T, true> 34412109SRekai.GonzalezAlberquilla@arm.com readVecLane(const RegId& reg) const 34512109SRekai.GonzalezAlberquilla@arm.com { 34612109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 34712109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 34812109SRekai.GonzalezAlberquilla@arm.com auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex()); 34912109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 35012109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, reg.elemIndex(), regVal); 35112109SRekai.GonzalezAlberquilla@arm.com return regVal; 35212109SRekai.GonzalezAlberquilla@arm.com } 35312109SRekai.GonzalezAlberquilla@arm.com 35412109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 35512109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 35613865Sgabeblack@google.com readVec8BitLaneReg(const RegId ®) const override 35713865Sgabeblack@google.com { 35813865Sgabeblack@google.com return readVecLane<uint8_t>(reg); 35913865Sgabeblack@google.com } 36012109SRekai.GonzalezAlberquilla@arm.com 36112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 36212109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 36313865Sgabeblack@google.com readVec16BitLaneReg(const RegId ®) const override 36413865Sgabeblack@google.com { 36513865Sgabeblack@google.com return readVecLane<uint16_t>(reg); 36613865Sgabeblack@google.com } 36712109SRekai.GonzalezAlberquilla@arm.com 36812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 36912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 37013865Sgabeblack@google.com readVec32BitLaneReg(const RegId ®) const override 37113865Sgabeblack@google.com { 37213865Sgabeblack@google.com return readVecLane<uint32_t>(reg); 37313865Sgabeblack@google.com } 37412109SRekai.GonzalezAlberquilla@arm.com 37512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 37612109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 37713865Sgabeblack@google.com readVec64BitLaneReg(const RegId ®) const override 37813865Sgabeblack@google.com { 37913865Sgabeblack@google.com return readVecLane<uint64_t>(reg); 38013865Sgabeblack@google.com } 38112109SRekai.GonzalezAlberquilla@arm.com 38212109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 38312109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 38413865Sgabeblack@google.com void 38513865Sgabeblack@google.com setVecLaneT(const RegId ®, const LD &val) 38612109SRekai.GonzalezAlberquilla@arm.com { 38712109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 38812109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 38912109SRekai.GonzalezAlberquilla@arm.com setVecLaneFlat(flatIndex, reg.elemIndex(), val); 39012109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n", 39112109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, reg.elemIndex(), val); 39212109SRekai.GonzalezAlberquilla@arm.com } 39313865Sgabeblack@google.com virtual void 39413865Sgabeblack@google.com setVecLane(const RegId ®, const LaneData<LaneSize::Byte> &val) override 39513865Sgabeblack@google.com { 39613865Sgabeblack@google.com return setVecLaneT(reg, val); 39713865Sgabeblack@google.com } 39813865Sgabeblack@google.com virtual void 39913865Sgabeblack@google.com setVecLane(const RegId ®, 40013865Sgabeblack@google.com const LaneData<LaneSize::TwoByte> &val) override 40113865Sgabeblack@google.com { 40213865Sgabeblack@google.com return setVecLaneT(reg, val); 40313865Sgabeblack@google.com } 40413865Sgabeblack@google.com virtual void 40513865Sgabeblack@google.com setVecLane(const RegId ®, 40613865Sgabeblack@google.com const LaneData<LaneSize::FourByte> &val) override 40713865Sgabeblack@google.com { 40813865Sgabeblack@google.com return setVecLaneT(reg, val); 40913865Sgabeblack@google.com } 41013865Sgabeblack@google.com virtual void 41113865Sgabeblack@google.com setVecLane(const RegId ®, 41213865Sgabeblack@google.com const LaneData<LaneSize::EightByte> &val) override 41313865Sgabeblack@google.com { 41413865Sgabeblack@google.com return setVecLaneT(reg, val); 41513865Sgabeblack@google.com } 41612109SRekai.GonzalezAlberquilla@arm.com /** @} */ 41712109SRekai.GonzalezAlberquilla@arm.com 41813865Sgabeblack@google.com const VecElem & 41913865Sgabeblack@google.com readVecElem(const RegId ®) const override 42012109SRekai.GonzalezAlberquilla@arm.com { 42112109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecElemIndex(reg.index()); 42212109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 42312109SRekai.GonzalezAlberquilla@arm.com const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 42412109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 42512109SRekai.GonzalezAlberquilla@arm.com " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 42612109SRekai.GonzalezAlberquilla@arm.com return regVal; 42712109SRekai.GonzalezAlberquilla@arm.com } 42812109SRekai.GonzalezAlberquilla@arm.com 42913865Sgabeblack@google.com const VecPredRegContainer & 43013865Sgabeblack@google.com readVecPredReg(const RegId ®) const override 43113610Sgiacomo.gabrielli@arm.com { 43213610Sgiacomo.gabrielli@arm.com int flatIndex = isa->flattenVecPredIndex(reg.index()); 43313610Sgiacomo.gabrielli@arm.com assert(flatIndex < TheISA::NumVecPredRegs); 43413610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex); 43513610Sgiacomo.gabrielli@arm.com DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n", 43613610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, regVal.print()); 43713610Sgiacomo.gabrielli@arm.com return regVal; 43813610Sgiacomo.gabrielli@arm.com } 43913610Sgiacomo.gabrielli@arm.com 44013865Sgabeblack@google.com VecPredRegContainer & 44113865Sgabeblack@google.com getWritableVecPredReg(const RegId ®) override 44213610Sgiacomo.gabrielli@arm.com { 44313610Sgiacomo.gabrielli@arm.com int flatIndex = isa->flattenVecPredIndex(reg.index()); 44413610Sgiacomo.gabrielli@arm.com assert(flatIndex < TheISA::NumVecPredRegs); 44513610Sgiacomo.gabrielli@arm.com VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex); 44613610Sgiacomo.gabrielli@arm.com DPRINTF(VecPredRegs, 44713610Sgiacomo.gabrielli@arm.com "Reading predicate reg %d (%d) as %s for modify.\n", 44813610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, regVal.print()); 44913610Sgiacomo.gabrielli@arm.com return regVal; 45013610Sgiacomo.gabrielli@arm.com } 45112109SRekai.GonzalezAlberquilla@arm.com 45213622Sgabeblack@google.com RegVal 45313865Sgabeblack@google.com readCCReg(RegIndex reg_idx) const override 4549920Syasuko.eckert@amd.com { 4559920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 4569920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 45710338SCurtis.Dunham@arm.com assert(0 <= flatIndex); 4589920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 4599920Syasuko.eckert@amd.com uint64_t regVal(readCCRegFlat(flatIndex)); 4609920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 4619920Syasuko.eckert@amd.com reg_idx, flatIndex, regVal); 4629920Syasuko.eckert@amd.com return regVal; 4639920Syasuko.eckert@amd.com#else 4649920Syasuko.eckert@amd.com panic("Tried to read a CC register."); 4659920Syasuko.eckert@amd.com return 0; 4669920Syasuko.eckert@amd.com#endif 4679920Syasuko.eckert@amd.com } 4689920Syasuko.eckert@amd.com 46913557Sgabeblack@google.com void 47013865Sgabeblack@google.com setIntReg(RegIndex reg_idx, RegVal val) override 4712SN/A { 4729384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 4736323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 4747601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 4757601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 4769426SAndreas.Sandberg@ARM.com setIntRegFlat(flatIndex, val); 4772SN/A } 4782SN/A 47913557Sgabeblack@google.com void 48013865Sgabeblack@google.com setFloatReg(RegIndex reg_idx, RegVal val) override 4812455SN/A { 4829384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 4836323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 4848733Sgeoffrey.blake@arm.com // XXX: Fix array out of bounds compiler error for gem5.fast 4858733Sgeoffrey.blake@arm.com // when checkercpu enabled 4868733Sgeoffrey.blake@arm.com if (flatIndex < TheISA::NumFloatRegs) 48713611Sgabeblack@google.com setFloatRegFlat(flatIndex, val); 48813501Sgabeblack@google.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 48913501Sgabeblack@google.com reg_idx, flatIndex, val); 4902SN/A } 4912SN/A 49213557Sgabeblack@google.com void 49313865Sgabeblack@google.com setVecReg(const RegId ®, const VecRegContainer &val) override 49412109SRekai.GonzalezAlberquilla@arm.com { 49512109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 49612109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 49712109SRekai.GonzalezAlberquilla@arm.com setVecRegFlat(flatIndex, val); 49812109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 49912109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, val.print()); 50012109SRekai.GonzalezAlberquilla@arm.com } 50112109SRekai.GonzalezAlberquilla@arm.com 50213557Sgabeblack@google.com void 50313865Sgabeblack@google.com setVecElem(const RegId ®, const VecElem &val) override 50412109SRekai.GonzalezAlberquilla@arm.com { 50512109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecElemIndex(reg.index()); 50612109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 50712109SRekai.GonzalezAlberquilla@arm.com setVecElemFlat(flatIndex, reg.elemIndex(), val); 50812109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 50912109SRekai.GonzalezAlberquilla@arm.com " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 51012109SRekai.GonzalezAlberquilla@arm.com } 51112109SRekai.GonzalezAlberquilla@arm.com 51213557Sgabeblack@google.com void 51313865Sgabeblack@google.com setVecPredReg(const RegId ®, const VecPredRegContainer &val) override 51413610Sgiacomo.gabrielli@arm.com { 51513610Sgiacomo.gabrielli@arm.com int flatIndex = isa->flattenVecPredIndex(reg.index()); 51613610Sgiacomo.gabrielli@arm.com assert(flatIndex < TheISA::NumVecPredRegs); 51713610Sgiacomo.gabrielli@arm.com setVecPredRegFlat(flatIndex, val); 51813610Sgiacomo.gabrielli@arm.com DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n", 51913610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, val.print()); 52013610Sgiacomo.gabrielli@arm.com } 52113610Sgiacomo.gabrielli@arm.com 52213610Sgiacomo.gabrielli@arm.com void 52313865Sgabeblack@google.com setCCReg(RegIndex reg_idx, RegVal val) override 5249920Syasuko.eckert@amd.com { 5259920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 5269920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 5279920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 5289920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 5299920Syasuko.eckert@amd.com reg_idx, flatIndex, val); 5309920Syasuko.eckert@amd.com setCCRegFlat(flatIndex, val); 5319920Syasuko.eckert@amd.com#else 5329920Syasuko.eckert@amd.com panic("Tried to set a CC register."); 5339920Syasuko.eckert@amd.com#endif 5349920Syasuko.eckert@amd.com } 5359920Syasuko.eckert@amd.com 53613865Sgabeblack@google.com TheISA::PCState pcState() const override { return _pcState; } 53713865Sgabeblack@google.com void pcState(const TheISA::PCState &val) override { _pcState = val; } 5382SN/A 5397720Sgblack@eecs.umich.edu void 54013865Sgabeblack@google.com pcStateNoRecord(const TheISA::PCState &val) override 5412190SN/A { 5427720Sgblack@eecs.umich.edu _pcState = val; 5432190SN/A } 5442190SN/A 54513865Sgabeblack@google.com Addr instAddr() const override { return _pcState.instAddr(); } 54613865Sgabeblack@google.com Addr nextInstAddr() const override { return _pcState.nextInstAddr(); } 54713865Sgabeblack@google.com MicroPC microPC() const override { return _pcState.microPC(); } 54813865Sgabeblack@google.com bool readPredicate() const { return predicate; } 54913865Sgabeblack@google.com void setPredicate(bool val) { predicate = val; } 5507597Sminkyu.jeong@arm.com 55113557Sgabeblack@google.com RegVal 55213865Sgabeblack@google.com readMiscRegNoEffect(RegIndex misc_reg) const override 5534172Ssaidi@eecs.umich.edu { 5549384SAndreas.Sandberg@arm.com return isa->readMiscRegNoEffect(misc_reg); 5554172Ssaidi@eecs.umich.edu } 5564172Ssaidi@eecs.umich.edu 55713557Sgabeblack@google.com RegVal 55813865Sgabeblack@google.com readMiscReg(RegIndex misc_reg) override 5592SN/A { 56013865Sgabeblack@google.com return isa->readMiscReg(misc_reg, this); 5612SN/A } 5622SN/A 5636221Snate@binkert.org void 56413865Sgabeblack@google.com setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override 5652SN/A { 5669384SAndreas.Sandberg@arm.com return isa->setMiscRegNoEffect(misc_reg, val); 5672SN/A } 5682SN/A 5696221Snate@binkert.org void 57013865Sgabeblack@google.com setMiscReg(RegIndex misc_reg, RegVal val) override 5712SN/A { 57213865Sgabeblack@google.com return isa->setMiscReg(misc_reg, val, this); 5736313Sgblack@eecs.umich.edu } 5746313Sgblack@eecs.umich.edu 57512106SRekai.GonzalezAlberquilla@arm.com RegId 57613865Sgabeblack@google.com flattenRegId(const RegId& regId) const override 5776313Sgblack@eecs.umich.edu { 57812106SRekai.GonzalezAlberquilla@arm.com return isa->flattenRegId(regId); 57910033SAli.Saidi@ARM.com } 58010033SAli.Saidi@ARM.com 58113865Sgabeblack@google.com unsigned readStCondFailures() const override { return storeCondFailures; } 5822190SN/A 58313557Sgabeblack@google.com void 58413865Sgabeblack@google.com setStCondFailures(unsigned sc_failures) override 5852SN/A { 58613865Sgabeblack@google.com storeCondFailures = sc_failures; 5872SN/A } 5889426SAndreas.Sandberg@ARM.com 58913865Sgabeblack@google.com Counter 59013865Sgabeblack@google.com readFuncExeInst() const override 59113865Sgabeblack@google.com { 59213865Sgabeblack@google.com return ThreadState::readFuncExeInst(); 59313865Sgabeblack@google.com } 5949426SAndreas.Sandberg@ARM.com 59513865Sgabeblack@google.com void 59613865Sgabeblack@google.com syscall(int64_t callnum, Fault *fault) override 59713865Sgabeblack@google.com { 59813865Sgabeblack@google.com process->syscall(callnum, this, fault); 59913865Sgabeblack@google.com } 60013865Sgabeblack@google.com 60113865Sgabeblack@google.com RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; } 60213865Sgabeblack@google.com void 60313865Sgabeblack@google.com setIntRegFlat(RegIndex idx, RegVal val) override 60413865Sgabeblack@google.com { 60513865Sgabeblack@google.com intRegs[idx] = val; 60613865Sgabeblack@google.com } 60713865Sgabeblack@google.com 60813865Sgabeblack@google.com RegVal 60913865Sgabeblack@google.com readFloatRegFlat(RegIndex idx) const override 61013865Sgabeblack@google.com { 61113865Sgabeblack@google.com return floatRegs[idx]; 61213865Sgabeblack@google.com } 61313865Sgabeblack@google.com void 61413865Sgabeblack@google.com setFloatRegFlat(RegIndex idx, RegVal val) override 61513865Sgabeblack@google.com { 61613865Sgabeblack@google.com floatRegs[idx] = val; 61713865Sgabeblack@google.com } 6189426SAndreas.Sandberg@ARM.com 61913557Sgabeblack@google.com const VecRegContainer & 62013865Sgabeblack@google.com readVecRegFlat(RegIndex reg) const override 62112109SRekai.GonzalezAlberquilla@arm.com { 62212109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg]; 62312109SRekai.GonzalezAlberquilla@arm.com } 62412109SRekai.GonzalezAlberquilla@arm.com 62513557Sgabeblack@google.com VecRegContainer & 62613865Sgabeblack@google.com getWritableVecRegFlat(RegIndex reg) override 62712109SRekai.GonzalezAlberquilla@arm.com { 62812109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg]; 62912109SRekai.GonzalezAlberquilla@arm.com } 63012109SRekai.GonzalezAlberquilla@arm.com 63113557Sgabeblack@google.com void 63213865Sgabeblack@google.com setVecRegFlat(RegIndex reg, const VecRegContainer &val) override 63312109SRekai.GonzalezAlberquilla@arm.com { 63412109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg] = val; 63512109SRekai.GonzalezAlberquilla@arm.com } 63612109SRekai.GonzalezAlberquilla@arm.com 63712109SRekai.GonzalezAlberquilla@arm.com template <typename T> 63813557Sgabeblack@google.com VecLaneT<T, true> 63913865Sgabeblack@google.com readVecLaneFlat(RegIndex reg, int lId) const 64012109SRekai.GonzalezAlberquilla@arm.com { 64112109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg].laneView<T>(lId); 64212109SRekai.GonzalezAlberquilla@arm.com } 64312109SRekai.GonzalezAlberquilla@arm.com 64412109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 64513557Sgabeblack@google.com void 64613865Sgabeblack@google.com setVecLaneFlat(RegIndex reg, int lId, const LD &val) 64712109SRekai.GonzalezAlberquilla@arm.com { 64812109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 64912109SRekai.GonzalezAlberquilla@arm.com } 65012109SRekai.GonzalezAlberquilla@arm.com 65113557Sgabeblack@google.com const VecElem & 65213865Sgabeblack@google.com readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override 65312109SRekai.GonzalezAlberquilla@arm.com { 65412109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 65512109SRekai.GonzalezAlberquilla@arm.com } 65612109SRekai.GonzalezAlberquilla@arm.com 65713557Sgabeblack@google.com void 65813865Sgabeblack@google.com setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex, 65913865Sgabeblack@google.com const VecElem &val) override 66012109SRekai.GonzalezAlberquilla@arm.com { 66112109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 66212109SRekai.GonzalezAlberquilla@arm.com } 66312109SRekai.GonzalezAlberquilla@arm.com 66413865Sgabeblack@google.com const VecPredRegContainer & 66513865Sgabeblack@google.com readVecPredRegFlat(RegIndex reg) const override 66613610Sgiacomo.gabrielli@arm.com { 66713610Sgiacomo.gabrielli@arm.com return vecPredRegs[reg]; 66813610Sgiacomo.gabrielli@arm.com } 66913610Sgiacomo.gabrielli@arm.com 67013865Sgabeblack@google.com VecPredRegContainer & 67113865Sgabeblack@google.com getWritableVecPredRegFlat(RegIndex reg) override 67213610Sgiacomo.gabrielli@arm.com { 67313610Sgiacomo.gabrielli@arm.com return vecPredRegs[reg]; 67413610Sgiacomo.gabrielli@arm.com } 67513610Sgiacomo.gabrielli@arm.com 67613865Sgabeblack@google.com void 67713865Sgabeblack@google.com setVecPredRegFlat(RegIndex reg, const VecPredRegContainer &val) override 67813610Sgiacomo.gabrielli@arm.com { 67913610Sgiacomo.gabrielli@arm.com vecPredRegs[reg] = val; 68013610Sgiacomo.gabrielli@arm.com } 68113610Sgiacomo.gabrielli@arm.com 6829920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 68313865Sgabeblack@google.com RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; } 68413865Sgabeblack@google.com void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; } 6859920Syasuko.eckert@amd.com#else 68613865Sgabeblack@google.com RegVal 68713865Sgabeblack@google.com readCCRegFlat(RegIndex idx) const override 68813865Sgabeblack@google.com { 68913865Sgabeblack@google.com panic("readCCRegFlat w/no CC regs!\n"); 69013865Sgabeblack@google.com } 6919920Syasuko.eckert@amd.com 69213865Sgabeblack@google.com void 69313865Sgabeblack@google.com setCCRegFlat(RegIndex idx, RegVal val) override 69413865Sgabeblack@google.com { 69513865Sgabeblack@google.com panic("setCCRegFlat w/no CC regs!\n"); 69613865Sgabeblack@google.com } 6979920Syasuko.eckert@amd.com#endif 6982SN/A}; 6992SN/A 7002SN/A 7012190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 702