simple_thread.hh revision 13905
1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2001-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 */ 44 45#ifndef __CPU_SIMPLE_THREAD_HH__ 46#define __CPU_SIMPLE_THREAD_HH__ 47 48#include "arch/decoder.hh" 49#include "arch/generic/tlb.hh" 50#include "arch/isa.hh" 51#include "arch/isa_traits.hh" 52#include "arch/registers.hh" 53#include "arch/types.hh" 54#include "base/types.hh" 55#include "config/the_isa.hh" 56#include "cpu/thread_context.hh" 57#include "cpu/thread_state.hh" 58#include "debug/CCRegs.hh" 59#include "debug/FloatRegs.hh" 60#include "debug/IntRegs.hh" 61#include "debug/VecPredRegs.hh" 62#include "debug/VecRegs.hh" 63#include "mem/page_table.hh" 64#include "mem/request.hh" 65#include "sim/byteswap.hh" 66#include "sim/eventq.hh" 67#include "sim/process.hh" 68#include "sim/serialize.hh" 69#include "sim/system.hh" 70 71class BaseCPU; 72class CheckerCPU; 73 74class FunctionProfile; 75class ProfileNode; 76 77namespace Kernel { 78 class Statistics; 79} 80 81/** 82 * The SimpleThread object provides a combination of the ThreadState 83 * object and the ThreadContext interface. It implements the 84 * ThreadContext interface and adds to the ThreadState object by adding all 85 * the objects needed for simple functional execution, including a 86 * simple architectural register file, and pointers to the ITB and DTB 87 * in full system mode. For CPU models that do not need more advanced 88 * ways to hold state (i.e. a separate physical register file, or 89 * separate fetch and commit PC's), this SimpleThread class provides 90 * all the necessary state for full architecture-level functional 91 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 92 * examples. 93 */ 94 95class SimpleThread : public ThreadState, public ThreadContext 96{ 97 protected: 98 typedef TheISA::MachInst MachInst; 99 using VecRegContainer = TheISA::VecRegContainer; 100 using VecElem = TheISA::VecElem; 101 using VecPredRegContainer = TheISA::VecPredRegContainer; 102 public: 103 typedef ThreadContext::Status Status; 104 105 protected: 106 RegVal floatRegs[TheISA::NumFloatRegs]; 107 RegVal intRegs[TheISA::NumIntRegs]; 108 VecRegContainer vecRegs[TheISA::NumVecRegs]; 109 VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs]; 110#ifdef ISA_HAS_CC_REGS 111 RegVal ccRegs[TheISA::NumCCRegs]; 112#endif 113 TheISA::ISA *const isa; // one "instance" of the current ISA. 114 115 TheISA::PCState _pcState; 116 117 /** Did this instruction execute or is it predicated false */ 118 bool predicate; 119 120 public: 121 std::string name() const 122 { 123 return csprintf("%s.[tid:%i]", baseCpu->name(), threadId()); 124 } 125 126 System *system; 127 128 BaseTLB *itb; 129 BaseTLB *dtb; 130 131 TheISA::Decoder decoder; 132 133 // constructor: initialize SimpleThread from given process structure 134 // FS 135 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 136 BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, 137 bool use_kernel_stats = true); 138 // SE 139 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 140 Process *_process, BaseTLB *_itb, BaseTLB *_dtb, 141 TheISA::ISA *_isa); 142 143 virtual ~SimpleThread() {} 144 145 void takeOverFrom(ThreadContext *oldContext) override; 146 147 void regStats(const std::string &name) override; 148 149 void copyState(ThreadContext *oldContext); 150 151 void serialize(CheckpointOut &cp) const override; 152 void unserialize(CheckpointIn &cp) override; 153 void startup(); 154 155 /*************************************************************** 156 * SimpleThread functions to provide CPU with access to various 157 * state. 158 **************************************************************/ 159 160 /** Returns the pointer to this SimpleThread's ThreadContext. Used 161 * when a ThreadContext must be passed to objects outside of the 162 * CPU. 163 */ 164 ThreadContext *getTC() { return this; } 165 166 void demapPage(Addr vaddr, uint64_t asn) 167 { 168 itb->demapPage(vaddr, asn); 169 dtb->demapPage(vaddr, asn); 170 } 171 172 void demapInstPage(Addr vaddr, uint64_t asn) 173 { 174 itb->demapPage(vaddr, asn); 175 } 176 177 void demapDataPage(Addr vaddr, uint64_t asn) 178 { 179 dtb->demapPage(vaddr, asn); 180 } 181 182 void dumpFuncProfile() override; 183 184 Fault hwrei(); 185 186 bool simPalCheck(int palFunc); 187 188 /******************************************* 189 * ThreadContext interface functions. 190 ******************************************/ 191 192 BaseCPU *getCpuPtr() override { return baseCpu; } 193 194 int cpuId() const override { return ThreadState::cpuId(); } 195 uint32_t socketId() const override { return ThreadState::socketId(); } 196 int threadId() const override { return ThreadState::threadId(); } 197 void setThreadId(int id) override { ThreadState::setThreadId(id); } 198 ContextID contextId() const override { return ThreadState::contextId(); } 199 void setContextId(ContextID id) override { ThreadState::setContextId(id); } 200 201 BaseTLB *getITBPtr() override { return itb; } 202 203 BaseTLB *getDTBPtr() override { return dtb; } 204 205 CheckerCPU *getCheckerCpuPtr() override { return NULL; } 206 207 TheISA::ISA *getIsaPtr() override { return isa; } 208 209 TheISA::Decoder *getDecoderPtr() override { return &decoder; } 210 211 System *getSystemPtr() override { return system; } 212 213 Kernel::Statistics * 214 getKernelStats() override 215 { 216 return ThreadState::getKernelStats(); 217 } 218 219 PortProxy &getPhysProxy() override { return ThreadState::getPhysProxy(); } 220 FSTranslatingPortProxy & 221 getVirtProxy() override 222 { 223 return ThreadState::getVirtProxy(); 224 } 225 226 void initMemProxies(ThreadContext *tc) override 227 { 228 ThreadState::initMemProxies(tc); 229 } 230 231 SETranslatingPortProxy & 232 getMemProxy() override 233 { 234 return ThreadState::getMemProxy(); 235 } 236 237 Process *getProcessPtr() override { return ThreadState::getProcessPtr(); } 238 void setProcessPtr(Process *p) override { ThreadState::setProcessPtr(p); } 239 240 Status status() const override { return _status; } 241 242 void setStatus(Status newStatus) override { _status = newStatus; } 243 244 /// Set the status to Active. 245 void activate() override; 246 247 /// Set the status to Suspended. 248 void suspend() override; 249 250 /// Set the status to Halted. 251 void halt() override; 252 253 EndQuiesceEvent * 254 getQuiesceEvent() override 255 { 256 return ThreadState::getQuiesceEvent(); 257 } 258 259 Tick 260 readLastActivate() override 261 { 262 return ThreadState::readLastActivate(); 263 } 264 Tick 265 readLastSuspend() override 266 { 267 return ThreadState::readLastSuspend(); 268 } 269 270 void profileClear() override { ThreadState::profileClear(); } 271 void profileSample() override { ThreadState::profileSample(); } 272 273 void copyArchRegs(ThreadContext *tc) override; 274 275 void clearArchRegs() override 276 { 277 _pcState = 0; 278 memset(intRegs, 0, sizeof(intRegs)); 279 memset(floatRegs, 0, sizeof(floatRegs)); 280 for (int i = 0; i < TheISA::NumVecRegs; i++) { 281 vecRegs[i].zero(); 282 } 283 for (int i = 0; i < TheISA::NumVecPredRegs; i++) { 284 vecPredRegs[i].reset(); 285 } 286#ifdef ISA_HAS_CC_REGS 287 memset(ccRegs, 0, sizeof(ccRegs)); 288#endif 289 isa->clear(); 290 } 291 292 // 293 // New accessors for new decoder. 294 // 295 RegVal 296 readIntReg(RegIndex reg_idx) const override 297 { 298 int flatIndex = isa->flattenIntIndex(reg_idx); 299 assert(flatIndex < TheISA::NumIntRegs); 300 uint64_t regVal(readIntRegFlat(flatIndex)); 301 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 302 reg_idx, flatIndex, regVal); 303 return regVal; 304 } 305 306 RegVal 307 readFloatReg(RegIndex reg_idx) const override 308 { 309 int flatIndex = isa->flattenFloatIndex(reg_idx); 310 assert(flatIndex < TheISA::NumFloatRegs); 311 RegVal regVal(readFloatRegFlat(flatIndex)); 312 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 313 reg_idx, flatIndex, regVal); 314 return regVal; 315 } 316 317 const VecRegContainer& 318 readVecReg(const RegId& reg) const override 319 { 320 int flatIndex = isa->flattenVecIndex(reg.index()); 321 assert(flatIndex < TheISA::NumVecRegs); 322 const VecRegContainer& regVal = readVecRegFlat(flatIndex); 323 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 324 reg.index(), flatIndex, regVal.print()); 325 return regVal; 326 } 327 328 VecRegContainer& 329 getWritableVecReg(const RegId& reg) override 330 { 331 int flatIndex = isa->flattenVecIndex(reg.index()); 332 assert(flatIndex < TheISA::NumVecRegs); 333 VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 334 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 335 reg.index(), flatIndex, regVal.print()); 336 return regVal; 337 } 338 339 /** Vector Register Lane Interfaces. */ 340 /** @{ */ 341 /** Reads source vector <T> operand. */ 342 template <typename T> 343 VecLaneT<T, true> 344 readVecLane(const RegId& reg) const 345 { 346 int flatIndex = isa->flattenVecIndex(reg.index()); 347 assert(flatIndex < TheISA::NumVecRegs); 348 auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex()); 349 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 350 reg.index(), flatIndex, reg.elemIndex(), regVal); 351 return regVal; 352 } 353 354 /** Reads source vector 8bit operand. */ 355 virtual ConstVecLane8 356 readVec8BitLaneReg(const RegId ®) const override 357 { 358 return readVecLane<uint8_t>(reg); 359 } 360 361 /** Reads source vector 16bit operand. */ 362 virtual ConstVecLane16 363 readVec16BitLaneReg(const RegId ®) const override 364 { 365 return readVecLane<uint16_t>(reg); 366 } 367 368 /** Reads source vector 32bit operand. */ 369 virtual ConstVecLane32 370 readVec32BitLaneReg(const RegId ®) const override 371 { 372 return readVecLane<uint32_t>(reg); 373 } 374 375 /** Reads source vector 64bit operand. */ 376 virtual ConstVecLane64 377 readVec64BitLaneReg(const RegId ®) const override 378 { 379 return readVecLane<uint64_t>(reg); 380 } 381 382 /** Write a lane of the destination vector register. */ 383 template <typename LD> 384 void 385 setVecLaneT(const RegId ®, const LD &val) 386 { 387 int flatIndex = isa->flattenVecIndex(reg.index()); 388 assert(flatIndex < TheISA::NumVecRegs); 389 setVecLaneFlat(flatIndex, reg.elemIndex(), val); 390 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n", 391 reg.index(), flatIndex, reg.elemIndex(), val); 392 } 393 virtual void 394 setVecLane(const RegId ®, const LaneData<LaneSize::Byte> &val) override 395 { 396 return setVecLaneT(reg, val); 397 } 398 virtual void 399 setVecLane(const RegId ®, 400 const LaneData<LaneSize::TwoByte> &val) override 401 { 402 return setVecLaneT(reg, val); 403 } 404 virtual void 405 setVecLane(const RegId ®, 406 const LaneData<LaneSize::FourByte> &val) override 407 { 408 return setVecLaneT(reg, val); 409 } 410 virtual void 411 setVecLane(const RegId ®, 412 const LaneData<LaneSize::EightByte> &val) override 413 { 414 return setVecLaneT(reg, val); 415 } 416 /** @} */ 417 418 const VecElem & 419 readVecElem(const RegId ®) const override 420 { 421 int flatIndex = isa->flattenVecElemIndex(reg.index()); 422 assert(flatIndex < TheISA::NumVecRegs); 423 const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 424 DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 425 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 426 return regVal; 427 } 428 429 const VecPredRegContainer & 430 readVecPredReg(const RegId ®) const override 431 { 432 int flatIndex = isa->flattenVecPredIndex(reg.index()); 433 assert(flatIndex < TheISA::NumVecPredRegs); 434 const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex); 435 DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n", 436 reg.index(), flatIndex, regVal.print()); 437 return regVal; 438 } 439 440 VecPredRegContainer & 441 getWritableVecPredReg(const RegId ®) override 442 { 443 int flatIndex = isa->flattenVecPredIndex(reg.index()); 444 assert(flatIndex < TheISA::NumVecPredRegs); 445 VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex); 446 DPRINTF(VecPredRegs, 447 "Reading predicate reg %d (%d) as %s for modify.\n", 448 reg.index(), flatIndex, regVal.print()); 449 return regVal; 450 } 451 452 RegVal 453 readCCReg(RegIndex reg_idx) const override 454 { 455#ifdef ISA_HAS_CC_REGS 456 int flatIndex = isa->flattenCCIndex(reg_idx); 457 assert(0 <= flatIndex); 458 assert(flatIndex < TheISA::NumCCRegs); 459 uint64_t regVal(readCCRegFlat(flatIndex)); 460 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 461 reg_idx, flatIndex, regVal); 462 return regVal; 463#else 464 panic("Tried to read a CC register."); 465 return 0; 466#endif 467 } 468 469 void 470 setIntReg(RegIndex reg_idx, RegVal val) override 471 { 472 int flatIndex = isa->flattenIntIndex(reg_idx); 473 assert(flatIndex < TheISA::NumIntRegs); 474 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 475 reg_idx, flatIndex, val); 476 setIntRegFlat(flatIndex, val); 477 } 478 479 void 480 setFloatReg(RegIndex reg_idx, RegVal val) override 481 { 482 int flatIndex = isa->flattenFloatIndex(reg_idx); 483 assert(flatIndex < TheISA::NumFloatRegs); 484 // XXX: Fix array out of bounds compiler error for gem5.fast 485 // when checkercpu enabled 486 if (flatIndex < TheISA::NumFloatRegs) 487 setFloatRegFlat(flatIndex, val); 488 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 489 reg_idx, flatIndex, val); 490 } 491 492 void 493 setVecReg(const RegId ®, const VecRegContainer &val) override 494 { 495 int flatIndex = isa->flattenVecIndex(reg.index()); 496 assert(flatIndex < TheISA::NumVecRegs); 497 setVecRegFlat(flatIndex, val); 498 DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 499 reg.index(), flatIndex, val.print()); 500 } 501 502 void 503 setVecElem(const RegId ®, const VecElem &val) override 504 { 505 int flatIndex = isa->flattenVecElemIndex(reg.index()); 506 assert(flatIndex < TheISA::NumVecRegs); 507 setVecElemFlat(flatIndex, reg.elemIndex(), val); 508 DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 509 " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 510 } 511 512 void 513 setVecPredReg(const RegId ®, const VecPredRegContainer &val) override 514 { 515 int flatIndex = isa->flattenVecPredIndex(reg.index()); 516 assert(flatIndex < TheISA::NumVecPredRegs); 517 setVecPredRegFlat(flatIndex, val); 518 DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n", 519 reg.index(), flatIndex, val.print()); 520 } 521 522 void 523 setCCReg(RegIndex reg_idx, RegVal val) override 524 { 525#ifdef ISA_HAS_CC_REGS 526 int flatIndex = isa->flattenCCIndex(reg_idx); 527 assert(flatIndex < TheISA::NumCCRegs); 528 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 529 reg_idx, flatIndex, val); 530 setCCRegFlat(flatIndex, val); 531#else 532 panic("Tried to set a CC register."); 533#endif 534 } 535 536 TheISA::PCState pcState() const override { return _pcState; } 537 void pcState(const TheISA::PCState &val) override { _pcState = val; } 538 539 void 540 pcStateNoRecord(const TheISA::PCState &val) override 541 { 542 _pcState = val; 543 } 544 545 Addr instAddr() const override { return _pcState.instAddr(); } 546 Addr nextInstAddr() const override { return _pcState.nextInstAddr(); } 547 MicroPC microPC() const override { return _pcState.microPC(); } 548 bool readPredicate() const { return predicate; } 549 void setPredicate(bool val) { predicate = val; } 550 551 RegVal 552 readMiscRegNoEffect(RegIndex misc_reg) const override 553 { 554 return isa->readMiscRegNoEffect(misc_reg); 555 } 556 557 RegVal 558 readMiscReg(RegIndex misc_reg) override 559 { 560 return isa->readMiscReg(misc_reg, this); 561 } 562 563 void 564 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override 565 { 566 return isa->setMiscRegNoEffect(misc_reg, val); 567 } 568 569 void 570 setMiscReg(RegIndex misc_reg, RegVal val) override 571 { 572 return isa->setMiscReg(misc_reg, val, this); 573 } 574 575 RegId 576 flattenRegId(const RegId& regId) const override 577 { 578 return isa->flattenRegId(regId); 579 } 580 581 unsigned readStCondFailures() const override { return storeCondFailures; } 582 583 void 584 setStCondFailures(unsigned sc_failures) override 585 { 586 storeCondFailures = sc_failures; 587 } 588 589 Counter 590 readFuncExeInst() const override 591 { 592 return ThreadState::readFuncExeInst(); 593 } 594 595 void 596 syscall(int64_t callnum, Fault *fault) override 597 { 598 process->syscall(callnum, this, fault); 599 } 600 601 RegVal readIntRegFlat(RegIndex idx) const override { return intRegs[idx]; } 602 void 603 setIntRegFlat(RegIndex idx, RegVal val) override 604 { 605 intRegs[idx] = val; 606 } 607 608 RegVal 609 readFloatRegFlat(RegIndex idx) const override 610 { 611 return floatRegs[idx]; 612 } 613 void 614 setFloatRegFlat(RegIndex idx, RegVal val) override 615 { 616 floatRegs[idx] = val; 617 } 618 619 const VecRegContainer & 620 readVecRegFlat(RegIndex reg) const override 621 { 622 return vecRegs[reg]; 623 } 624 625 VecRegContainer & 626 getWritableVecRegFlat(RegIndex reg) override 627 { 628 return vecRegs[reg]; 629 } 630 631 void 632 setVecRegFlat(RegIndex reg, const VecRegContainer &val) override 633 { 634 vecRegs[reg] = val; 635 } 636 637 template <typename T> 638 VecLaneT<T, true> 639 readVecLaneFlat(RegIndex reg, int lId) const 640 { 641 return vecRegs[reg].laneView<T>(lId); 642 } 643 644 template <typename LD> 645 void 646 setVecLaneFlat(RegIndex reg, int lId, const LD &val) 647 { 648 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 649 } 650 651 const VecElem & 652 readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override 653 { 654 return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 655 } 656 657 void 658 setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex, 659 const VecElem &val) override 660 { 661 vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 662 } 663 664 const VecPredRegContainer & 665 readVecPredRegFlat(RegIndex reg) const override 666 { 667 return vecPredRegs[reg]; 668 } 669 670 VecPredRegContainer & 671 getWritableVecPredRegFlat(RegIndex reg) override 672 { 673 return vecPredRegs[reg]; 674 } 675 676 void 677 setVecPredRegFlat(RegIndex reg, const VecPredRegContainer &val) override 678 { 679 vecPredRegs[reg] = val; 680 } 681 682#ifdef ISA_HAS_CC_REGS 683 RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; } 684 void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; } 685#else 686 RegVal 687 readCCRegFlat(RegIndex idx) const override 688 { 689 panic("readCCRegFlat w/no CC regs!\n"); 690 } 691 692 void 693 setCCRegFlat(RegIndex idx, RegVal val) override 694 { 695 panic("setCCRegFlat w/no CC regs!\n"); 696 } 697#endif 698}; 699 700 701#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 702