simple_thread.cc revision 8820
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302665SN/A * Lisa Hsu 312665SN/A * Kevin Lim 322SN/A */ 332SN/A 342SN/A#include <string> 352SN/A 362465SN/A#include "arch/isa_traits.hh" 373565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 385529Snate@binkert.org#include "arch/stacktrace.hh" 398777Sgblack@eecs.umich.edu#include "arch/utility.hh" 401917SN/A#include "base/callback.hh" 411070SN/A#include "base/cprintf.hh" 421917SN/A#include "base/output.hh" 432188SN/A#include "base/trace.hh" 448777Sgblack@eecs.umich.edu#include "config/the_isa.hh" 458777Sgblack@eecs.umich.edu#include "cpu/base.hh" 461917SN/A#include "cpu/profile.hh" 472290SN/A#include "cpu/quiesce_event.hh" 488777Sgblack@eecs.umich.edu#include "cpu/simple_thread.hh" 498777Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 508706Sandreas.hansson@arm.com#include "mem/fs_translating_port_proxy.hh" 518799Sgblack@eecs.umich.edu#include "mem/se_translating_port_proxy.hh" 528809Sgblack@eecs.umich.edu#include "params/BaseCPU.hh" 538793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 548777Sgblack@eecs.umich.edu#include "sim/process.hh" 551070SN/A#include "sim/serialize.hh" 561917SN/A#include "sim/sim_exit.hh" 572519SN/A#include "sim/system.hh" 582SN/A 592SN/Ausing namespace std; 602SN/A 612SN/A// constructor 628820Sgblack@eecs.umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 638820Sgblack@eecs.umich.edu Process *_process, TheISA::TLB *_itb, 648820Sgblack@eecs.umich.edu TheISA::TLB *_dtb) 658820Sgblack@eecs.umich.edu : ThreadState(_cpu, _thread_num, _process), system(_sys), itb(_itb), 668820Sgblack@eecs.umich.edu dtb(_dtb) 678766Sgblack@eecs.umich.edu{ 688766Sgblack@eecs.umich.edu clearArchRegs(); 698766Sgblack@eecs.umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 708766Sgblack@eecs.umich.edu} 712683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 726022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 732683Sktlim@umich.edu bool use_kernel_stats) 748809Sgblack@eecs.umich.edu : ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb) 752SN/A{ 762683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 772190SN/A 782680SN/A quiesceEvent = new EndQuiesceEvent(tc); 792290SN/A 806316Sgblack@eecs.umich.edu clearArchRegs(); 811917SN/A 828735Sandreas.hanson@arm.com if (baseCpu->params()->profile) { 831982SN/A profile = new FunctionProfile(system->kernelSymtab); 841917SN/A Callback *cb = 852683Sktlim@umich.edu new MakeCallback<SimpleThread, 862683Sktlim@umich.edu &SimpleThread::dumpFuncProfile>(this); 871917SN/A registerExitCallback(cb); 881917SN/A } 891917SN/A 901917SN/A // let's fill with a dummy node for now so we don't get a segfault 911917SN/A // on the first cycle when there's no node available. 921917SN/A static ProfileNode dummyNode; 931917SN/A profileNode = &dummyNode; 941917SN/A profilePC = 3; 952521SN/A 965482Snate@binkert.org if (use_kernel_stats) 973548Sgblack@eecs.umich.edu kernelStats = new TheISA::Kernel::Statistics(system); 982SN/A} 992862Sktlim@umich.edu 1002864Sktlim@umich.eduSimpleThread::SimpleThread() 1016331Sgblack@eecs.umich.edu : ThreadState(NULL, -1, NULL) 1022190SN/A{ 1032683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1042190SN/A} 1052190SN/A 1062683Sktlim@umich.eduSimpleThread::~SimpleThread() 1071070SN/A{ 1082680SN/A delete tc; 1091070SN/A} 1101070SN/A 1111917SN/Avoid 1122683Sktlim@umich.eduSimpleThread::takeOverFrom(ThreadContext *oldContext) 113180SN/A{ 114180SN/A // some things should already be set up 1158793Sgblack@eecs.umich.edu if (FullSystem) 1168793Sgblack@eecs.umich.edu assert(system == oldContext->getSystemPtr()); 1172235SN/A assert(process == oldContext->getProcessPtr()); 118180SN/A 1192862Sktlim@umich.edu copyState(oldContext); 1208793Sgblack@eecs.umich.edu if (FullSystem) { 1218793Sgblack@eecs.umich.edu EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1228793Sgblack@eecs.umich.edu if (quiesce) { 1238793Sgblack@eecs.umich.edu // Point the quiesce event's TC at this TC so that it wakes up 1248793Sgblack@eecs.umich.edu // the proper CPU. 1258793Sgblack@eecs.umich.edu quiesce->tc = tc; 1268793Sgblack@eecs.umich.edu } 1278793Sgblack@eecs.umich.edu if (quiesceEvent) { 1288793Sgblack@eecs.umich.edu quiesceEvent->tc = tc; 1298793Sgblack@eecs.umich.edu } 1308793Sgblack@eecs.umich.edu 1318793Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 1328793Sgblack@eecs.umich.edu if (stats) { 1338793Sgblack@eecs.umich.edu kernelStats = stats; 1348793Sgblack@eecs.umich.edu } 1352313SN/A } 136180SN/A 137180SN/A storeCondFailures = 0; 138180SN/A 1396029Ssteve.reinhardt@amd.com oldContext->setStatus(ThreadContext::Halted); 140180SN/A} 141180SN/A 1422SN/Avoid 1432864Sktlim@umich.eduSimpleThread::copyTC(ThreadContext *context) 1442864Sktlim@umich.edu{ 1452864Sktlim@umich.edu copyState(context); 1462864Sktlim@umich.edu 1478793Sgblack@eecs.umich.edu if (FullSystem) { 1488793Sgblack@eecs.umich.edu EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 1498793Sgblack@eecs.umich.edu if (quiesce) { 1508793Sgblack@eecs.umich.edu quiesceEvent = quiesce; 1518793Sgblack@eecs.umich.edu } 1528793Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = context->getKernelStats(); 1538793Sgblack@eecs.umich.edu if (stats) { 1548793Sgblack@eecs.umich.edu kernelStats = stats; 1558793Sgblack@eecs.umich.edu } 1562864Sktlim@umich.edu } 1572864Sktlim@umich.edu} 1582864Sktlim@umich.edu 1592864Sktlim@umich.eduvoid 1602862Sktlim@umich.eduSimpleThread::copyState(ThreadContext *oldContext) 1612862Sktlim@umich.edu{ 1622862Sktlim@umich.edu // copy over functional state 1632862Sktlim@umich.edu _status = oldContext->status(); 1642862Sktlim@umich.edu copyArchRegs(oldContext); 1658793Sgblack@eecs.umich.edu if (FullSystem) 1668793Sgblack@eecs.umich.edu funcExeInst = oldContext->readFuncExeInst(); 1675714Shsul@eecs.umich.edu 1685715Shsul@eecs.umich.edu _threadId = oldContext->threadId(); 1695714Shsul@eecs.umich.edu _contextId = oldContext->contextId(); 1702862Sktlim@umich.edu} 1712862Sktlim@umich.edu 1722862Sktlim@umich.eduvoid 1732683Sktlim@umich.eduSimpleThread::serialize(ostream &os) 174217SN/A{ 1752862Sktlim@umich.edu ThreadState::serialize(os); 1766315Sgblack@eecs.umich.edu SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 1776316Sgblack@eecs.umich.edu SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 1787720Sgblack@eecs.umich.edu _pcState.serialize(os); 179223SN/A // thread_num and cpu_id are deterministic from the config 1806677SBrad.Beckmann@amd.com 1816677SBrad.Beckmann@amd.com // 1826677SBrad.Beckmann@amd.com // Now must serialize all the ISA dependent state 1836677SBrad.Beckmann@amd.com // 1848735Sandreas.hanson@arm.com isa.serialize(baseCpu, os); 185217SN/A} 186217SN/A 187217SN/A 188217SN/Avoid 1892683Sktlim@umich.eduSimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 190217SN/A{ 1912862Sktlim@umich.edu ThreadState::unserialize(cp, section); 1926315Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); 1936316Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); 1947720Sgblack@eecs.umich.edu _pcState.unserialize(cp, section); 195223SN/A // thread_num and cpu_id are deterministic from the config 1966677SBrad.Beckmann@amd.com 1976677SBrad.Beckmann@amd.com // 1986677SBrad.Beckmann@amd.com // Now must unserialize all the ISA dependent state 1996677SBrad.Beckmann@amd.com // 2008735Sandreas.hanson@arm.com isa.unserialize(baseCpu, cp, section); 201217SN/A} 202217SN/A 2032683Sktlim@umich.eduvoid 2042683Sktlim@umich.eduSimpleThread::dumpFuncProfile() 2052683Sktlim@umich.edu{ 2068735Sandreas.hanson@arm.com std::ostream *os = simout.create(csprintf("profile.%s.dat", 2078735Sandreas.hanson@arm.com baseCpu->name())); 2082683Sktlim@umich.edu profile->dump(tc, *os); 2092683Sktlim@umich.edu} 210217SN/A 211217SN/Avoid 2122683Sktlim@umich.eduSimpleThread::activate(int delay) 2132SN/A{ 2142680SN/A if (status() == ThreadContext::Active) 2152SN/A return; 2162SN/A 2177823Ssteve.reinhardt@amd.com lastActivate = curTick(); 2182188SN/A 2194400Srdreslin@umich.edu// if (status() == ThreadContext::Unallocated) { 2205715Shsul@eecs.umich.edu// cpu->activateWhenReady(_threadId); 2215543Ssaidi@eecs.umich.edu// return; 2224400Srdreslin@umich.edu// } 2232290SN/A 2242680SN/A _status = ThreadContext::Active; 2252290SN/A 2262290SN/A // status() == Suspended 2278735Sandreas.hanson@arm.com baseCpu->activateContext(_threadId, delay); 228393SN/A} 229393SN/A 230393SN/Avoid 2312683Sktlim@umich.eduSimpleThread::suspend() 232393SN/A{ 2332680SN/A if (status() == ThreadContext::Suspended) 234393SN/A return; 235393SN/A 2367823Ssteve.reinhardt@amd.com lastActivate = curTick(); 2377823Ssteve.reinhardt@amd.com lastSuspend = curTick(); 2382680SN/A _status = ThreadContext::Suspended; 2398735Sandreas.hanson@arm.com baseCpu->suspendContext(_threadId); 2402SN/A} 2412SN/A 242393SN/A 243393SN/Avoid 2442683Sktlim@umich.eduSimpleThread::halt() 245393SN/A{ 2462680SN/A if (status() == ThreadContext::Halted) 247393SN/A return; 248393SN/A 2492680SN/A _status = ThreadContext::Halted; 2508735Sandreas.hanson@arm.com baseCpu->haltContext(_threadId); 251393SN/A} 252393SN/A 253393SN/A 254393SN/Avoid 2552683Sktlim@umich.eduSimpleThread::regStats(const string &name) 2562SN/A{ 2578793Sgblack@eecs.umich.edu if (FullSystem && kernelStats) 2582341SN/A kernelStats->regStats(name + ".kern"); 2592SN/A} 260716SN/A 261716SN/Avoid 2622683Sktlim@umich.eduSimpleThread::copyArchRegs(ThreadContext *src_tc) 2632190SN/A{ 2642680SN/A TheISA::copyRegs(src_tc, tc); 2652190SN/A} 2662190SN/A 267