timing.cc revision 3201
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 322623SN/A#include "arch/utility.hh" 332623SN/A#include "cpu/exetrace.hh" 342623SN/A#include "cpu/simple/timing.hh" 352623SN/A#include "mem/packet_impl.hh" 362623SN/A#include "sim/builder.hh" 372901Ssaidi@eecs.umich.edu#include "sim/system.hh" 382623SN/A 392623SN/Ausing namespace std; 402623SN/Ausing namespace TheISA; 412623SN/A 422856Srdreslin@umich.eduPort * 432856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 442856Srdreslin@umich.edu{ 452856Srdreslin@umich.edu if (if_name == "dcache_port") 462856Srdreslin@umich.edu return &dcachePort; 472856Srdreslin@umich.edu else if (if_name == "icache_port") 482856Srdreslin@umich.edu return &icachePort; 492856Srdreslin@umich.edu else 502856Srdreslin@umich.edu panic("No Such Port\n"); 512856Srdreslin@umich.edu} 522623SN/A 532623SN/Avoid 542623SN/ATimingSimpleCPU::init() 552623SN/A{ 562623SN/A BaseCPU::init(); 572623SN/A#if FULL_SYSTEM 582680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 592680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 602623SN/A 612623SN/A // initialize CPU, including PC 622680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 632623SN/A } 642623SN/A#endif 652623SN/A} 662623SN/A 672623SN/ATick 682630SN/ATimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 692623SN/A{ 702623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 712623SN/A return curTick; 722623SN/A} 732623SN/A 742623SN/Avoid 752630SN/ATimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 762623SN/A{ 773184Srdreslin@umich.edu //No internal storage to update, jusst return 783184Srdreslin@umich.edu return; 792623SN/A} 802623SN/A 812623SN/Avoid 822623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 832623SN/A{ 842631SN/A if (status == RangeChange) 852631SN/A return; 862631SN/A 872623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 882623SN/A} 892623SN/A 902948Ssaidi@eecs.umich.edu 912948Ssaidi@eecs.umich.eduvoid 922948Ssaidi@eecs.umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t) 932948Ssaidi@eecs.umich.edu{ 942948Ssaidi@eecs.umich.edu pkt = _pkt; 952948Ssaidi@eecs.umich.edu Event::schedule(t); 962948Ssaidi@eecs.umich.edu} 972948Ssaidi@eecs.umich.edu 982623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 993170Sstever@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), 1003170Sstever@eecs.umich.edu cpu_id(p->cpu_id) 1012623SN/A{ 1022623SN/A _status = Idle; 1032623SN/A ifetch_pkt = dcache_pkt = NULL; 1042839Sktlim@umich.edu drainEvent = NULL; 1052867Sktlim@umich.edu fetchEvent = NULL; 1062901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1072623SN/A} 1082623SN/A 1092623SN/A 1102623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1112623SN/A{ 1122623SN/A} 1132623SN/A 1142623SN/Avoid 1152623SN/ATimingSimpleCPU::serialize(ostream &os) 1162623SN/A{ 1172915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1182915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1192623SN/A BaseSimpleCPU::serialize(os); 1202623SN/A} 1212623SN/A 1222623SN/Avoid 1232623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1242623SN/A{ 1252915Sktlim@umich.edu SimObject::State so_state; 1262915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1272623SN/A BaseSimpleCPU::unserialize(cp, section); 1282798Sktlim@umich.edu} 1292798Sktlim@umich.edu 1302901Ssaidi@eecs.umich.eduunsigned int 1312839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1322798Sktlim@umich.edu{ 1332839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1342798Sktlim@umich.edu // an access to complete. 1352798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1362901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1372901Ssaidi@eecs.umich.edu return 0; 1382798Sktlim@umich.edu } else { 1392839Sktlim@umich.edu changeState(SimObject::Draining); 1402839Sktlim@umich.edu drainEvent = drain_event; 1412901Ssaidi@eecs.umich.edu return 1; 1422798Sktlim@umich.edu } 1432623SN/A} 1442623SN/A 1452623SN/Avoid 1462798Sktlim@umich.eduTimingSimpleCPU::resume() 1472623SN/A{ 1482798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1493201Shsul@eecs.umich.edu assert(system->getMemoryMode() == System::Timing); 1503201Shsul@eecs.umich.edu 1512867Sktlim@umich.edu // Delete the old event if it existed. 1522867Sktlim@umich.edu if (fetchEvent) { 1532915Sktlim@umich.edu if (fetchEvent->scheduled()) 1542915Sktlim@umich.edu fetchEvent->deschedule(); 1552915Sktlim@umich.edu 1562867Sktlim@umich.edu delete fetchEvent; 1572867Sktlim@umich.edu } 1582867Sktlim@umich.edu 1592867Sktlim@umich.edu fetchEvent = 1602867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 1612867Sktlim@umich.edu fetchEvent->schedule(curTick); 1622623SN/A } 1632798Sktlim@umich.edu 1642901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1652798Sktlim@umich.edu} 1662798Sktlim@umich.edu 1672798Sktlim@umich.eduvoid 1682798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1692798Sktlim@umich.edu{ 1702798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1712798Sktlim@umich.edu _status = SwitchedOut; 1722867Sktlim@umich.edu 1732867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1742867Sktlim@umich.edu // we'll need to cancel it. 1752867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1762867Sktlim@umich.edu fetchEvent->deschedule(); 1772623SN/A} 1782623SN/A 1792623SN/A 1802623SN/Avoid 1812623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1822623SN/A{ 1832623SN/A BaseCPU::takeOverFrom(oldCPU); 1842623SN/A 1852680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1862623SN/A // running and schedule its tick event. 1872680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1882680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1892680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1902623SN/A _status = Running; 1912623SN/A break; 1922623SN/A } 1932623SN/A } 1943201Shsul@eecs.umich.edu 1953201Shsul@eecs.umich.edu if (_status != Running) { 1963201Shsul@eecs.umich.edu _status = Idle; 1973201Shsul@eecs.umich.edu } 1982623SN/A} 1992623SN/A 2002623SN/A 2012623SN/Avoid 2022623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 2032623SN/A{ 2042623SN/A assert(thread_num == 0); 2052683Sktlim@umich.edu assert(thread); 2062623SN/A 2072623SN/A assert(_status == Idle); 2082623SN/A 2092623SN/A notIdleFraction++; 2102623SN/A _status = Running; 2112623SN/A // kick things off by initiating the fetch of the next instruction 2122867Sktlim@umich.edu fetchEvent = 2132867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 2142867Sktlim@umich.edu fetchEvent->schedule(curTick + cycles(delay)); 2152623SN/A} 2162623SN/A 2172623SN/A 2182623SN/Avoid 2192623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2202623SN/A{ 2212623SN/A assert(thread_num == 0); 2222683Sktlim@umich.edu assert(thread); 2232623SN/A 2242644Sstever@eecs.umich.edu assert(_status == Running); 2252623SN/A 2262644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2272644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2282623SN/A 2292623SN/A notIdleFraction--; 2302623SN/A _status = Idle; 2312623SN/A} 2322623SN/A 2332623SN/A 2342623SN/Atemplate <class T> 2352623SN/AFault 2362623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2372623SN/A{ 2383169Sstever@eecs.umich.edu Request *req = 2393169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2403170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 2412623SN/A 2422623SN/A if (traceData) { 2433169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2442623SN/A } 2452623SN/A 2462623SN/A // translate to physical address 2473169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2482623SN/A 2492623SN/A // Now do the access. 2502623SN/A if (fault == NoFault) { 2513169Sstever@eecs.umich.edu Packet *pkt = 2523169Sstever@eecs.umich.edu new Packet(req, Packet::ReadReq, Packet::Broadcast); 2533169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2542623SN/A 2553169Sstever@eecs.umich.edu if (!dcachePort.sendTiming(pkt)) { 2562623SN/A _status = DcacheRetry; 2573169Sstever@eecs.umich.edu dcache_pkt = pkt; 2582623SN/A } else { 2592623SN/A _status = DcacheWaitResponse; 2603169Sstever@eecs.umich.edu // memory system takes ownership of packet 2612623SN/A dcache_pkt = NULL; 2622623SN/A } 2632623SN/A } 2642623SN/A 2652623SN/A // This will need a new way to tell if it has a dcache attached. 2663172Sstever@eecs.umich.edu if (req->isUncacheable()) 2672623SN/A recordEvent("Uncached Read"); 2682623SN/A 2692623SN/A return fault; 2702623SN/A} 2712623SN/A 2722623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2732623SN/A 2742623SN/Atemplate 2752623SN/AFault 2762623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 2772623SN/A 2782623SN/Atemplate 2792623SN/AFault 2802623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 2812623SN/A 2822623SN/Atemplate 2832623SN/AFault 2842623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 2852623SN/A 2862623SN/Atemplate 2872623SN/AFault 2882623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 2892623SN/A 2902623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 2912623SN/A 2922623SN/Atemplate<> 2932623SN/AFault 2942623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 2952623SN/A{ 2962623SN/A return read(addr, *(uint64_t*)&data, flags); 2972623SN/A} 2982623SN/A 2992623SN/Atemplate<> 3002623SN/AFault 3012623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 3022623SN/A{ 3032623SN/A return read(addr, *(uint32_t*)&data, flags); 3042623SN/A} 3052623SN/A 3062623SN/A 3072623SN/Atemplate<> 3082623SN/AFault 3092623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3102623SN/A{ 3112623SN/A return read(addr, (uint32_t&)data, flags); 3122623SN/A} 3132623SN/A 3142623SN/A 3152623SN/Atemplate <class T> 3162623SN/AFault 3172623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3182623SN/A{ 3193169Sstever@eecs.umich.edu Request *req = 3203169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3213170Sstever@eecs.umich.edu cpu_id, /* thread ID */ 0); 3222623SN/A 3232623SN/A // translate to physical address 3243169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3253169Sstever@eecs.umich.edu 3262623SN/A // Now do the access. 3272623SN/A if (fault == NoFault) { 3283169Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 3293169Sstever@eecs.umich.edu dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 3303169Sstever@eecs.umich.edu dcache_pkt->allocate(); 3313169Sstever@eecs.umich.edu dcache_pkt->set(data); 3322623SN/A 3333170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3343170Sstever@eecs.umich.edu 3353170Sstever@eecs.umich.edu if (req->isLocked()) { 3363170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3373170Sstever@eecs.umich.edu } 3383170Sstever@eecs.umich.edu 3393170Sstever@eecs.umich.edu if (do_access) { 3403170Sstever@eecs.umich.edu if (!dcachePort.sendTiming(dcache_pkt)) { 3413170Sstever@eecs.umich.edu _status = DcacheRetry; 3423170Sstever@eecs.umich.edu } else { 3433170Sstever@eecs.umich.edu _status = DcacheWaitResponse; 3443170Sstever@eecs.umich.edu // memory system takes ownership of packet 3453170Sstever@eecs.umich.edu dcache_pkt = NULL; 3463170Sstever@eecs.umich.edu } 3472623SN/A } 3482623SN/A } 3492623SN/A 3502623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3513172Sstever@eecs.umich.edu if (req->isUncacheable()) 3522623SN/A recordEvent("Uncached Write"); 3532623SN/A 3542623SN/A // If the write needs to have a fault on the access, consider calling 3552623SN/A // changeStatus() and changing it to "bad addr write" or something. 3562623SN/A return fault; 3572623SN/A} 3582623SN/A 3592623SN/A 3602623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3612623SN/Atemplate 3622623SN/AFault 3632623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 3642623SN/A unsigned flags, uint64_t *res); 3652623SN/A 3662623SN/Atemplate 3672623SN/AFault 3682623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 3692623SN/A unsigned flags, uint64_t *res); 3702623SN/A 3712623SN/Atemplate 3722623SN/AFault 3732623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 3742623SN/A unsigned flags, uint64_t *res); 3752623SN/A 3762623SN/Atemplate 3772623SN/AFault 3782623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 3792623SN/A unsigned flags, uint64_t *res); 3802623SN/A 3812623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3822623SN/A 3832623SN/Atemplate<> 3842623SN/AFault 3852623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 3862623SN/A{ 3872623SN/A return write(*(uint64_t*)&data, addr, flags, res); 3882623SN/A} 3892623SN/A 3902623SN/Atemplate<> 3912623SN/AFault 3922623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 3932623SN/A{ 3942623SN/A return write(*(uint32_t*)&data, addr, flags, res); 3952623SN/A} 3962623SN/A 3972623SN/A 3982623SN/Atemplate<> 3992623SN/AFault 4002623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4012623SN/A{ 4022623SN/A return write((uint32_t)data, addr, flags, res); 4032623SN/A} 4042623SN/A 4052623SN/A 4062623SN/Avoid 4072623SN/ATimingSimpleCPU::fetch() 4082623SN/A{ 4092631SN/A checkForInterrupts(); 4102631SN/A 4112663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 4123170Sstever@eecs.umich.edu ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0); 4132662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4142623SN/A 4152641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 4162623SN/A ifetch_pkt->dataStatic(&inst); 4172623SN/A 4182623SN/A if (fault == NoFault) { 4192630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 4202623SN/A // Need to wait for retry 4212623SN/A _status = IcacheRetry; 4222623SN/A } else { 4232623SN/A // Need to wait for cache to respond 4242623SN/A _status = IcacheWaitResponse; 4252623SN/A // ownership of packet transferred to memory system 4262623SN/A ifetch_pkt = NULL; 4272623SN/A } 4282623SN/A } else { 4292644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 4302644Sstever@eecs.umich.edu advanceInst(fault); 4312623SN/A } 4322623SN/A} 4332623SN/A 4342623SN/A 4352623SN/Avoid 4362644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 4372623SN/A{ 4382623SN/A advancePC(fault); 4392623SN/A 4402631SN/A if (_status == Running) { 4412631SN/A // kick off fetch of next instruction... callback from icache 4422631SN/A // response will cause that instruction to be executed, 4432631SN/A // keeping the CPU running. 4442631SN/A fetch(); 4452631SN/A } 4462623SN/A} 4472623SN/A 4482623SN/A 4492623SN/Avoid 4502644Sstever@eecs.umich.eduTimingSimpleCPU::completeIfetch(Packet *pkt) 4512623SN/A{ 4522623SN/A // received a response from the icache: execute the received 4532623SN/A // instruction 4542644Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 4552623SN/A assert(_status == IcacheWaitResponse); 4562798Sktlim@umich.edu 4572623SN/A _status = Running; 4582644Sstever@eecs.umich.edu 4592644Sstever@eecs.umich.edu delete pkt->req; 4602644Sstever@eecs.umich.edu delete pkt; 4612644Sstever@eecs.umich.edu 4622839Sktlim@umich.edu if (getState() == SimObject::Draining) { 4632839Sktlim@umich.edu completeDrain(); 4642798Sktlim@umich.edu return; 4652798Sktlim@umich.edu } 4662798Sktlim@umich.edu 4672623SN/A preExecute(); 4682644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 4692623SN/A // load or store: just send to dcache 4702623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 4713170Sstever@eecs.umich.edu if (_status != Running) { 4723170Sstever@eecs.umich.edu // instruction will complete in dcache response callback 4733170Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse || _status == DcacheRetry); 4743170Sstever@eecs.umich.edu assert(fault == NoFault); 4752644Sstever@eecs.umich.edu } else { 4763170Sstever@eecs.umich.edu if (fault == NoFault) { 4773170Sstever@eecs.umich.edu // early fail on store conditional: complete now 4783170Sstever@eecs.umich.edu assert(dcache_pkt != NULL); 4793170Sstever@eecs.umich.edu fault = curStaticInst->completeAcc(dcache_pkt, this, 4803170Sstever@eecs.umich.edu traceData); 4813170Sstever@eecs.umich.edu delete dcache_pkt->req; 4823170Sstever@eecs.umich.edu delete dcache_pkt; 4833170Sstever@eecs.umich.edu dcache_pkt = NULL; 4843170Sstever@eecs.umich.edu } 4852644Sstever@eecs.umich.edu postExecute(); 4862644Sstever@eecs.umich.edu advanceInst(fault); 4872644Sstever@eecs.umich.edu } 4882623SN/A } else { 4892623SN/A // non-memory instruction: execute completely now 4902623SN/A Fault fault = curStaticInst->execute(this, traceData); 4912644Sstever@eecs.umich.edu postExecute(); 4922644Sstever@eecs.umich.edu advanceInst(fault); 4932623SN/A } 4942623SN/A} 4952623SN/A 4962948Ssaidi@eecs.umich.eduvoid 4972948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 4982948Ssaidi@eecs.umich.edu{ 4992948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 5002948Ssaidi@eecs.umich.edu} 5012623SN/A 5022623SN/Abool 5032630SN/ATimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 5042623SN/A{ 5053170Sstever@eecs.umich.edu // delay processing of returned data until next CPU clock edge 5062948Ssaidi@eecs.umich.edu Tick time = pkt->req->getTime(); 5072948Ssaidi@eecs.umich.edu while (time < curTick) 5082948Ssaidi@eecs.umich.edu time += lat; 5092948Ssaidi@eecs.umich.edu 5102948Ssaidi@eecs.umich.edu if (time == curTick) 5112948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 5122948Ssaidi@eecs.umich.edu else 5132948Ssaidi@eecs.umich.edu tickEvent.schedule(pkt, time); 5142948Ssaidi@eecs.umich.edu 5152623SN/A return true; 5162623SN/A} 5172623SN/A 5182657Ssaidi@eecs.umich.eduvoid 5192623SN/ATimingSimpleCPU::IcachePort::recvRetry() 5202623SN/A{ 5212623SN/A // we shouldn't get a retry unless we have a packet that we're 5222623SN/A // waiting to transmit 5232623SN/A assert(cpu->ifetch_pkt != NULL); 5242623SN/A assert(cpu->_status == IcacheRetry); 5252623SN/A Packet *tmp = cpu->ifetch_pkt; 5262657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 5272657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 5282657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 5292657Ssaidi@eecs.umich.edu } 5302623SN/A} 5312623SN/A 5322623SN/Avoid 5332623SN/ATimingSimpleCPU::completeDataAccess(Packet *pkt) 5342623SN/A{ 5352623SN/A // received a response from the dcache: complete the load or store 5362623SN/A // instruction 5372641Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 5382623SN/A assert(_status == DcacheWaitResponse); 5392623SN/A _status = Running; 5402623SN/A 5412623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 5422623SN/A 5433170Sstever@eecs.umich.edu if (pkt->isRead() && pkt->req->isLocked()) { 5443170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, pkt->req); 5453170Sstever@eecs.umich.edu } 5463170Sstever@eecs.umich.edu 5472644Sstever@eecs.umich.edu delete pkt->req; 5482644Sstever@eecs.umich.edu delete pkt; 5492644Sstever@eecs.umich.edu 5503201Shsul@eecs.umich.edu if (getState() == SimObject::Draining) { 5513201Shsul@eecs.umich.edu advancePC(fault); 5523201Shsul@eecs.umich.edu completeDrain(); 5533201Shsul@eecs.umich.edu 5543201Shsul@eecs.umich.edu return; 5553201Shsul@eecs.umich.edu } 5563201Shsul@eecs.umich.edu 5572644Sstever@eecs.umich.edu postExecute(); 5582644Sstever@eecs.umich.edu advanceInst(fault); 5592623SN/A} 5602623SN/A 5612623SN/A 5622798Sktlim@umich.eduvoid 5632839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 5642798Sktlim@umich.edu{ 5652839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 5662901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 5672839Sktlim@umich.edu drainEvent->process(); 5682798Sktlim@umich.edu} 5692623SN/A 5702623SN/Abool 5712630SN/ATimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 5722623SN/A{ 5733170Sstever@eecs.umich.edu // delay processing of returned data until next CPU clock edge 5742948Ssaidi@eecs.umich.edu Tick time = pkt->req->getTime(); 5752948Ssaidi@eecs.umich.edu while (time < curTick) 5762948Ssaidi@eecs.umich.edu time += lat; 5772948Ssaidi@eecs.umich.edu 5782948Ssaidi@eecs.umich.edu if (time == curTick) 5792948Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 5802948Ssaidi@eecs.umich.edu else 5812948Ssaidi@eecs.umich.edu tickEvent.schedule(pkt, time); 5822948Ssaidi@eecs.umich.edu 5832948Ssaidi@eecs.umich.edu return true; 5842948Ssaidi@eecs.umich.edu} 5852948Ssaidi@eecs.umich.edu 5862948Ssaidi@eecs.umich.eduvoid 5872948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 5882948Ssaidi@eecs.umich.edu{ 5892630SN/A cpu->completeDataAccess(pkt); 5902623SN/A} 5912623SN/A 5922657Ssaidi@eecs.umich.eduvoid 5932623SN/ATimingSimpleCPU::DcachePort::recvRetry() 5942623SN/A{ 5952623SN/A // we shouldn't get a retry unless we have a packet that we're 5962623SN/A // waiting to transmit 5972623SN/A assert(cpu->dcache_pkt != NULL); 5982623SN/A assert(cpu->_status == DcacheRetry); 5992623SN/A Packet *tmp = cpu->dcache_pkt; 6002657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 6012657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 6023170Sstever@eecs.umich.edu // memory system takes ownership of packet 6032657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 6042657Ssaidi@eecs.umich.edu } 6052623SN/A} 6062623SN/A 6072623SN/A 6082623SN/A//////////////////////////////////////////////////////////////////////// 6092623SN/A// 6102623SN/A// TimingSimpleCPU Simulation Object 6112623SN/A// 6122623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6132623SN/A 6142623SN/A Param<Counter> max_insts_any_thread; 6152623SN/A Param<Counter> max_insts_all_threads; 6162623SN/A Param<Counter> max_loads_any_thread; 6172623SN/A Param<Counter> max_loads_all_threads; 6183119Sktlim@umich.edu Param<Tick> progress_interval; 6192623SN/A SimObjectParam<MemObject *> mem; 6202901Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 6213170Sstever@eecs.umich.edu Param<int> cpu_id; 6222623SN/A 6232623SN/A#if FULL_SYSTEM 6242623SN/A SimObjectParam<AlphaITB *> itb; 6252623SN/A SimObjectParam<AlphaDTB *> dtb; 6262623SN/A Param<Tick> profile; 6272623SN/A#else 6282623SN/A SimObjectParam<Process *> workload; 6292623SN/A#endif // FULL_SYSTEM 6302623SN/A 6312623SN/A Param<int> clock; 6322623SN/A 6332623SN/A Param<bool> defer_registration; 6342623SN/A Param<int> width; 6352623SN/A Param<bool> function_trace; 6362623SN/A Param<Tick> function_trace_start; 6372623SN/A Param<bool> simulate_stalls; 6382623SN/A 6392623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6402623SN/A 6412623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6422623SN/A 6432623SN/A INIT_PARAM(max_insts_any_thread, 6442623SN/A "terminate when any thread reaches this inst count"), 6452623SN/A INIT_PARAM(max_insts_all_threads, 6462623SN/A "terminate when all threads have reached this inst count"), 6472623SN/A INIT_PARAM(max_loads_any_thread, 6482623SN/A "terminate when any thread reaches this load count"), 6492623SN/A INIT_PARAM(max_loads_all_threads, 6502623SN/A "terminate when all threads have reached this load count"), 6513119Sktlim@umich.edu INIT_PARAM(progress_interval, "Progress interval"), 6522623SN/A INIT_PARAM(mem, "memory"), 6532901Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object"), 6543170Sstever@eecs.umich.edu INIT_PARAM(cpu_id, "processor ID"), 6552623SN/A 6562623SN/A#if FULL_SYSTEM 6572623SN/A INIT_PARAM(itb, "Instruction TLB"), 6582623SN/A INIT_PARAM(dtb, "Data TLB"), 6592623SN/A INIT_PARAM(profile, ""), 6602623SN/A#else 6612623SN/A INIT_PARAM(workload, "processes to run"), 6622623SN/A#endif // FULL_SYSTEM 6632623SN/A 6642623SN/A INIT_PARAM(clock, "clock speed"), 6652623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 6662623SN/A INIT_PARAM(width, "cpu width"), 6672623SN/A INIT_PARAM(function_trace, "Enable function trace"), 6682623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 6692623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 6702623SN/A 6712623SN/AEND_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6722623SN/A 6732623SN/A 6742623SN/ACREATE_SIM_OBJECT(TimingSimpleCPU) 6752623SN/A{ 6762623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 6772623SN/A params->name = getInstanceName(); 6782623SN/A params->numberOfThreads = 1; 6792623SN/A params->max_insts_any_thread = max_insts_any_thread; 6802623SN/A params->max_insts_all_threads = max_insts_all_threads; 6812623SN/A params->max_loads_any_thread = max_loads_any_thread; 6822623SN/A params->max_loads_all_threads = max_loads_all_threads; 6833119Sktlim@umich.edu params->progress_interval = progress_interval; 6842623SN/A params->deferRegistration = defer_registration; 6852623SN/A params->clock = clock; 6862623SN/A params->functionTrace = function_trace; 6872623SN/A params->functionTraceStart = function_trace_start; 6882623SN/A params->mem = mem; 6892901Ssaidi@eecs.umich.edu params->system = system; 6903170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 6912623SN/A 6922623SN/A#if FULL_SYSTEM 6932623SN/A params->itb = itb; 6942623SN/A params->dtb = dtb; 6952623SN/A params->profile = profile; 6962623SN/A#else 6972623SN/A params->process = workload; 6982623SN/A#endif 6992623SN/A 7002623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 7012623SN/A return cpu; 7022623SN/A} 7032623SN/A 7042623SN/AREGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 7052623SN/A 706