timing.cc revision 3169
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#include "arch/utility.hh" 322623SN/A#include "cpu/exetrace.hh" 332623SN/A#include "cpu/simple/timing.hh" 342623SN/A#include "mem/packet_impl.hh" 352623SN/A#include "sim/builder.hh" 362901Ssaidi@eecs.umich.edu#include "sim/system.hh" 372623SN/A 382623SN/Ausing namespace std; 392623SN/Ausing namespace TheISA; 402623SN/A 412856Srdreslin@umich.eduPort * 422856Srdreslin@umich.eduTimingSimpleCPU::getPort(const std::string &if_name, int idx) 432856Srdreslin@umich.edu{ 442856Srdreslin@umich.edu if (if_name == "dcache_port") 452856Srdreslin@umich.edu return &dcachePort; 462856Srdreslin@umich.edu else if (if_name == "icache_port") 472856Srdreslin@umich.edu return &icachePort; 482856Srdreslin@umich.edu else 492856Srdreslin@umich.edu panic("No Such Port\n"); 502856Srdreslin@umich.edu} 512623SN/A 522623SN/Avoid 532623SN/ATimingSimpleCPU::init() 542623SN/A{ 552623SN/A BaseCPU::init(); 562623SN/A#if FULL_SYSTEM 572680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 582680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 592623SN/A 602623SN/A // initialize CPU, including PC 612680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 622623SN/A } 632623SN/A#endif 642623SN/A} 652623SN/A 662623SN/ATick 672630SN/ATimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 682623SN/A{ 692623SN/A panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 702623SN/A return curTick; 712623SN/A} 722623SN/A 732623SN/Avoid 742630SN/ATimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 752623SN/A{ 762623SN/A panic("TimingSimpleCPU doesn't expect recvFunctional callback!"); 772623SN/A} 782623SN/A 792623SN/Avoid 802623SN/ATimingSimpleCPU::CpuPort::recvStatusChange(Status status) 812623SN/A{ 822631SN/A if (status == RangeChange) 832631SN/A return; 842631SN/A 852623SN/A panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 862623SN/A} 872623SN/A 882948Ssaidi@eecs.umich.edu 892948Ssaidi@eecs.umich.eduvoid 902948Ssaidi@eecs.umich.eduTimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t) 912948Ssaidi@eecs.umich.edu{ 922948Ssaidi@eecs.umich.edu pkt = _pkt; 932948Ssaidi@eecs.umich.edu Event::schedule(t); 942948Ssaidi@eecs.umich.edu} 952948Ssaidi@eecs.umich.edu 962623SN/ATimingSimpleCPU::TimingSimpleCPU(Params *p) 972948Ssaidi@eecs.umich.edu : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock) 982623SN/A{ 992623SN/A _status = Idle; 1002623SN/A ifetch_pkt = dcache_pkt = NULL; 1012839Sktlim@umich.edu drainEvent = NULL; 1022867Sktlim@umich.edu fetchEvent = NULL; 1032901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1042623SN/A} 1052623SN/A 1062623SN/A 1072623SN/ATimingSimpleCPU::~TimingSimpleCPU() 1082623SN/A{ 1092623SN/A} 1102623SN/A 1112623SN/Avoid 1122623SN/ATimingSimpleCPU::serialize(ostream &os) 1132623SN/A{ 1142915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1152915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1162623SN/A BaseSimpleCPU::serialize(os); 1172623SN/A} 1182623SN/A 1192623SN/Avoid 1202623SN/ATimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1212623SN/A{ 1222915Sktlim@umich.edu SimObject::State so_state; 1232915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1242623SN/A BaseSimpleCPU::unserialize(cp, section); 1252798Sktlim@umich.edu} 1262798Sktlim@umich.edu 1272901Ssaidi@eecs.umich.eduunsigned int 1282839Sktlim@umich.eduTimingSimpleCPU::drain(Event *drain_event) 1292798Sktlim@umich.edu{ 1302839Sktlim@umich.edu // TimingSimpleCPU is ready to drain if it's not waiting for 1312798Sktlim@umich.edu // an access to complete. 1322798Sktlim@umich.edu if (status() == Idle || status() == Running || status() == SwitchedOut) { 1332901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 1342901Ssaidi@eecs.umich.edu return 0; 1352798Sktlim@umich.edu } else { 1362839Sktlim@umich.edu changeState(SimObject::Draining); 1372839Sktlim@umich.edu drainEvent = drain_event; 1382901Ssaidi@eecs.umich.edu return 1; 1392798Sktlim@umich.edu } 1402623SN/A} 1412623SN/A 1422623SN/Avoid 1432798Sktlim@umich.eduTimingSimpleCPU::resume() 1442623SN/A{ 1452798Sktlim@umich.edu if (_status != SwitchedOut && _status != Idle) { 1462867Sktlim@umich.edu // Delete the old event if it existed. 1472867Sktlim@umich.edu if (fetchEvent) { 1482915Sktlim@umich.edu if (fetchEvent->scheduled()) 1492915Sktlim@umich.edu fetchEvent->deschedule(); 1502915Sktlim@umich.edu 1512867Sktlim@umich.edu delete fetchEvent; 1522867Sktlim@umich.edu } 1532867Sktlim@umich.edu 1542867Sktlim@umich.edu fetchEvent = 1552867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 1562867Sktlim@umich.edu fetchEvent->schedule(curTick); 1572623SN/A } 1582798Sktlim@umich.edu 1592901Ssaidi@eecs.umich.edu assert(system->getMemoryMode() == System::Timing); 1602901Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1612798Sktlim@umich.edu} 1622798Sktlim@umich.edu 1632798Sktlim@umich.eduvoid 1642798Sktlim@umich.eduTimingSimpleCPU::switchOut() 1652798Sktlim@umich.edu{ 1662798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1672798Sktlim@umich.edu _status = SwitchedOut; 1682867Sktlim@umich.edu 1692867Sktlim@umich.edu // If we've been scheduled to resume but are then told to switch out, 1702867Sktlim@umich.edu // we'll need to cancel it. 1712867Sktlim@umich.edu if (fetchEvent && fetchEvent->scheduled()) 1722867Sktlim@umich.edu fetchEvent->deschedule(); 1732623SN/A} 1742623SN/A 1752623SN/A 1762623SN/Avoid 1772623SN/ATimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1782623SN/A{ 1792623SN/A BaseCPU::takeOverFrom(oldCPU); 1802623SN/A 1812680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1822623SN/A // running and schedule its tick event. 1832680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 1842680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1852680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1862623SN/A _status = Running; 1872623SN/A break; 1882623SN/A } 1892623SN/A } 1902623SN/A} 1912623SN/A 1922623SN/A 1932623SN/Avoid 1942623SN/ATimingSimpleCPU::activateContext(int thread_num, int delay) 1952623SN/A{ 1962623SN/A assert(thread_num == 0); 1972683Sktlim@umich.edu assert(thread); 1982623SN/A 1992623SN/A assert(_status == Idle); 2002623SN/A 2012623SN/A notIdleFraction++; 2022623SN/A _status = Running; 2032623SN/A // kick things off by initiating the fetch of the next instruction 2042867Sktlim@umich.edu fetchEvent = 2052867Sktlim@umich.edu new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 2062867Sktlim@umich.edu fetchEvent->schedule(curTick + cycles(delay)); 2072623SN/A} 2082623SN/A 2092623SN/A 2102623SN/Avoid 2112623SN/ATimingSimpleCPU::suspendContext(int thread_num) 2122623SN/A{ 2132623SN/A assert(thread_num == 0); 2142683Sktlim@umich.edu assert(thread); 2152623SN/A 2162644Sstever@eecs.umich.edu assert(_status == Running); 2172623SN/A 2182644Sstever@eecs.umich.edu // just change status to Idle... if status != Running, 2192644Sstever@eecs.umich.edu // completeInst() will not initiate fetch of next instruction. 2202623SN/A 2212623SN/A notIdleFraction--; 2222623SN/A _status = Idle; 2232623SN/A} 2242623SN/A 2252623SN/A 2262623SN/Atemplate <class T> 2272623SN/AFault 2282623SN/ATimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 2292623SN/A{ 2303169Sstever@eecs.umich.edu Request *req = 2313169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 2323169Sstever@eecs.umich.edu /* CPU ID */ 0, /* thread ID */ 0); 2332623SN/A 2342623SN/A if (traceData) { 2353169Sstever@eecs.umich.edu traceData->setAddr(req->getVaddr()); 2362623SN/A } 2372623SN/A 2382623SN/A // translate to physical address 2393169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2402623SN/A 2412623SN/A // Now do the access. 2422623SN/A if (fault == NoFault) { 2433169Sstever@eecs.umich.edu Packet *pkt = 2443169Sstever@eecs.umich.edu new Packet(req, Packet::ReadReq, Packet::Broadcast); 2453169Sstever@eecs.umich.edu pkt->dataDynamic<T>(new T); 2462623SN/A 2473169Sstever@eecs.umich.edu if (!dcachePort.sendTiming(pkt)) { 2482623SN/A _status = DcacheRetry; 2493169Sstever@eecs.umich.edu dcache_pkt = pkt; 2502623SN/A } else { 2512623SN/A _status = DcacheWaitResponse; 2523169Sstever@eecs.umich.edu // memory system takes ownership of packet 2532623SN/A dcache_pkt = NULL; 2542623SN/A } 2552623SN/A } 2562623SN/A 2572623SN/A // This will need a new way to tell if it has a dcache attached. 2583169Sstever@eecs.umich.edu if (req->getFlags() & UNCACHEABLE) 2592623SN/A recordEvent("Uncached Read"); 2602623SN/A 2612623SN/A return fault; 2622623SN/A} 2632623SN/A 2642623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2652623SN/A 2662623SN/Atemplate 2672623SN/AFault 2682623SN/ATimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 2692623SN/A 2702623SN/Atemplate 2712623SN/AFault 2722623SN/ATimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 2732623SN/A 2742623SN/Atemplate 2752623SN/AFault 2762623SN/ATimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 2772623SN/A 2782623SN/Atemplate 2792623SN/AFault 2802623SN/ATimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 2812623SN/A 2822623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 2832623SN/A 2842623SN/Atemplate<> 2852623SN/AFault 2862623SN/ATimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 2872623SN/A{ 2882623SN/A return read(addr, *(uint64_t*)&data, flags); 2892623SN/A} 2902623SN/A 2912623SN/Atemplate<> 2922623SN/AFault 2932623SN/ATimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 2942623SN/A{ 2952623SN/A return read(addr, *(uint32_t*)&data, flags); 2962623SN/A} 2972623SN/A 2982623SN/A 2992623SN/Atemplate<> 3002623SN/AFault 3012623SN/ATimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3022623SN/A{ 3032623SN/A return read(addr, (uint32_t&)data, flags); 3042623SN/A} 3052623SN/A 3062623SN/A 3072623SN/Atemplate <class T> 3082623SN/AFault 3092623SN/ATimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3102623SN/A{ 3113169Sstever@eecs.umich.edu Request *req = 3123169Sstever@eecs.umich.edu new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 3133169Sstever@eecs.umich.edu /* CPU ID */ 0, /* thread ID */ 0); 3142623SN/A 3152623SN/A // translate to physical address 3163169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3173169Sstever@eecs.umich.edu 3182623SN/A // Now do the access. 3192623SN/A if (fault == NoFault) { 3203169Sstever@eecs.umich.edu assert(dcache_pkt == NULL); 3213169Sstever@eecs.umich.edu dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 3223169Sstever@eecs.umich.edu dcache_pkt->allocate(); 3233169Sstever@eecs.umich.edu dcache_pkt->set(data); 3242623SN/A 3253169Sstever@eecs.umich.edu if (!dcachePort.sendTiming(dcache_pkt)) { 3262623SN/A _status = DcacheRetry; 3272623SN/A } else { 3282623SN/A _status = DcacheWaitResponse; 3293169Sstever@eecs.umich.edu // memory system takes ownership of packet 3302623SN/A dcache_pkt = NULL; 3312623SN/A } 3322623SN/A } 3332623SN/A 3342623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3353169Sstever@eecs.umich.edu if (req->getFlags() & UNCACHEABLE) 3362623SN/A recordEvent("Uncached Write"); 3372623SN/A 3382623SN/A // If the write needs to have a fault on the access, consider calling 3392623SN/A // changeStatus() and changing it to "bad addr write" or something. 3402623SN/A return fault; 3412623SN/A} 3422623SN/A 3432623SN/A 3442623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3452623SN/Atemplate 3462623SN/AFault 3472623SN/ATimingSimpleCPU::write(uint64_t data, Addr addr, 3482623SN/A unsigned flags, uint64_t *res); 3492623SN/A 3502623SN/Atemplate 3512623SN/AFault 3522623SN/ATimingSimpleCPU::write(uint32_t data, Addr addr, 3532623SN/A unsigned flags, uint64_t *res); 3542623SN/A 3552623SN/Atemplate 3562623SN/AFault 3572623SN/ATimingSimpleCPU::write(uint16_t data, Addr addr, 3582623SN/A unsigned flags, uint64_t *res); 3592623SN/A 3602623SN/Atemplate 3612623SN/AFault 3622623SN/ATimingSimpleCPU::write(uint8_t data, Addr addr, 3632623SN/A unsigned flags, uint64_t *res); 3642623SN/A 3652623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3662623SN/A 3672623SN/Atemplate<> 3682623SN/AFault 3692623SN/ATimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 3702623SN/A{ 3712623SN/A return write(*(uint64_t*)&data, addr, flags, res); 3722623SN/A} 3732623SN/A 3742623SN/Atemplate<> 3752623SN/AFault 3762623SN/ATimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 3772623SN/A{ 3782623SN/A return write(*(uint32_t*)&data, addr, flags, res); 3792623SN/A} 3802623SN/A 3812623SN/A 3822623SN/Atemplate<> 3832623SN/AFault 3842623SN/ATimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 3852623SN/A{ 3862623SN/A return write((uint32_t)data, addr, flags, res); 3872623SN/A} 3882623SN/A 3892623SN/A 3902623SN/Avoid 3912623SN/ATimingSimpleCPU::fetch() 3922623SN/A{ 3932631SN/A checkForInterrupts(); 3942631SN/A 3952663Sstever@eecs.umich.edu // need to fill in CPU & thread IDs here 3962663Sstever@eecs.umich.edu Request *ifetch_req = new Request(); 3972835Srdreslin@umich.edu ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 3982662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 3992623SN/A 4002641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 4012623SN/A ifetch_pkt->dataStatic(&inst); 4022623SN/A 4032623SN/A if (fault == NoFault) { 4042630SN/A if (!icachePort.sendTiming(ifetch_pkt)) { 4052623SN/A // Need to wait for retry 4062623SN/A _status = IcacheRetry; 4072623SN/A } else { 4082623SN/A // Need to wait for cache to respond 4092623SN/A _status = IcacheWaitResponse; 4102623SN/A // ownership of packet transferred to memory system 4112623SN/A ifetch_pkt = NULL; 4122623SN/A } 4132623SN/A } else { 4142644Sstever@eecs.umich.edu // fetch fault: advance directly to next instruction (fault handler) 4152644Sstever@eecs.umich.edu advanceInst(fault); 4162623SN/A } 4172623SN/A} 4182623SN/A 4192623SN/A 4202623SN/Avoid 4212644Sstever@eecs.umich.eduTimingSimpleCPU::advanceInst(Fault fault) 4222623SN/A{ 4232623SN/A advancePC(fault); 4242623SN/A 4252631SN/A if (_status == Running) { 4262631SN/A // kick off fetch of next instruction... callback from icache 4272631SN/A // response will cause that instruction to be executed, 4282631SN/A // keeping the CPU running. 4292631SN/A fetch(); 4302631SN/A } 4312623SN/A} 4322623SN/A 4332623SN/A 4342623SN/Avoid 4352644Sstever@eecs.umich.eduTimingSimpleCPU::completeIfetch(Packet *pkt) 4362623SN/A{ 4372623SN/A // received a response from the icache: execute the received 4382623SN/A // instruction 4392644Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 4402623SN/A assert(_status == IcacheWaitResponse); 4412798Sktlim@umich.edu 4422623SN/A _status = Running; 4432644Sstever@eecs.umich.edu 4442644Sstever@eecs.umich.edu delete pkt->req; 4452644Sstever@eecs.umich.edu delete pkt; 4462644Sstever@eecs.umich.edu 4472839Sktlim@umich.edu if (getState() == SimObject::Draining) { 4482839Sktlim@umich.edu completeDrain(); 4492798Sktlim@umich.edu return; 4502798Sktlim@umich.edu } 4512798Sktlim@umich.edu 4522623SN/A preExecute(); 4532644Sstever@eecs.umich.edu if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 4542623SN/A // load or store: just send to dcache 4552623SN/A Fault fault = curStaticInst->initiateAcc(this, traceData); 4562644Sstever@eecs.umich.edu if (fault == NoFault) { 4572644Sstever@eecs.umich.edu // successfully initiated access: instruction will 4582644Sstever@eecs.umich.edu // complete in dcache response callback 4592644Sstever@eecs.umich.edu assert(_status == DcacheWaitResponse); 4602644Sstever@eecs.umich.edu } else { 4612644Sstever@eecs.umich.edu // fault: complete now to invoke fault handler 4622644Sstever@eecs.umich.edu postExecute(); 4632644Sstever@eecs.umich.edu advanceInst(fault); 4642644Sstever@eecs.umich.edu } 4652623SN/A } else { 4662623SN/A // non-memory instruction: execute completely now 4672623SN/A Fault fault = curStaticInst->execute(this, traceData); 4682644Sstever@eecs.umich.edu postExecute(); 4692644Sstever@eecs.umich.edu advanceInst(fault); 4702623SN/A } 4712623SN/A} 4722623SN/A 4732948Ssaidi@eecs.umich.eduvoid 4742948Ssaidi@eecs.umich.eduTimingSimpleCPU::IcachePort::ITickEvent::process() 4752948Ssaidi@eecs.umich.edu{ 4762948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 4772948Ssaidi@eecs.umich.edu} 4782623SN/A 4792623SN/Abool 4802630SN/ATimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 4812623SN/A{ 4822948Ssaidi@eecs.umich.edu // These next few lines could be replaced with something faster 4832948Ssaidi@eecs.umich.edu // who knows what though 4842948Ssaidi@eecs.umich.edu Tick time = pkt->req->getTime(); 4852948Ssaidi@eecs.umich.edu while (time < curTick) 4862948Ssaidi@eecs.umich.edu time += lat; 4872948Ssaidi@eecs.umich.edu 4882948Ssaidi@eecs.umich.edu if (time == curTick) 4892948Ssaidi@eecs.umich.edu cpu->completeIfetch(pkt); 4902948Ssaidi@eecs.umich.edu else 4912948Ssaidi@eecs.umich.edu tickEvent.schedule(pkt, time); 4922948Ssaidi@eecs.umich.edu 4932623SN/A return true; 4942623SN/A} 4952623SN/A 4962657Ssaidi@eecs.umich.eduvoid 4972623SN/ATimingSimpleCPU::IcachePort::recvRetry() 4982623SN/A{ 4992623SN/A // we shouldn't get a retry unless we have a packet that we're 5002623SN/A // waiting to transmit 5012623SN/A assert(cpu->ifetch_pkt != NULL); 5022623SN/A assert(cpu->_status == IcacheRetry); 5032623SN/A Packet *tmp = cpu->ifetch_pkt; 5042657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 5052657Ssaidi@eecs.umich.edu cpu->_status = IcacheWaitResponse; 5062657Ssaidi@eecs.umich.edu cpu->ifetch_pkt = NULL; 5072657Ssaidi@eecs.umich.edu } 5082623SN/A} 5092623SN/A 5102623SN/Avoid 5112623SN/ATimingSimpleCPU::completeDataAccess(Packet *pkt) 5122623SN/A{ 5132623SN/A // received a response from the dcache: complete the load or store 5142623SN/A // instruction 5152641Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 5162623SN/A assert(_status == DcacheWaitResponse); 5172623SN/A _status = Running; 5182623SN/A 5192839Sktlim@umich.edu if (getState() == SimObject::Draining) { 5202839Sktlim@umich.edu completeDrain(); 5212798Sktlim@umich.edu 5222798Sktlim@umich.edu delete pkt->req; 5232798Sktlim@umich.edu delete pkt; 5242798Sktlim@umich.edu 5252798Sktlim@umich.edu return; 5262798Sktlim@umich.edu } 5272798Sktlim@umich.edu 5282623SN/A Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 5292623SN/A 5302644Sstever@eecs.umich.edu delete pkt->req; 5312644Sstever@eecs.umich.edu delete pkt; 5322644Sstever@eecs.umich.edu 5332644Sstever@eecs.umich.edu postExecute(); 5342644Sstever@eecs.umich.edu advanceInst(fault); 5352623SN/A} 5362623SN/A 5372623SN/A 5382798Sktlim@umich.eduvoid 5392839Sktlim@umich.eduTimingSimpleCPU::completeDrain() 5402798Sktlim@umich.edu{ 5412839Sktlim@umich.edu DPRINTF(Config, "Done draining\n"); 5422901Ssaidi@eecs.umich.edu changeState(SimObject::Drained); 5432839Sktlim@umich.edu drainEvent->process(); 5442798Sktlim@umich.edu} 5452623SN/A 5462623SN/Abool 5472630SN/ATimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 5482623SN/A{ 5492948Ssaidi@eecs.umich.edu Tick time = pkt->req->getTime(); 5502948Ssaidi@eecs.umich.edu while (time < curTick) 5512948Ssaidi@eecs.umich.edu time += lat; 5522948Ssaidi@eecs.umich.edu 5532948Ssaidi@eecs.umich.edu if (time == curTick) 5542948Ssaidi@eecs.umich.edu cpu->completeDataAccess(pkt); 5552948Ssaidi@eecs.umich.edu else 5562948Ssaidi@eecs.umich.edu tickEvent.schedule(pkt, time); 5572948Ssaidi@eecs.umich.edu 5582948Ssaidi@eecs.umich.edu return true; 5592948Ssaidi@eecs.umich.edu} 5602948Ssaidi@eecs.umich.edu 5612948Ssaidi@eecs.umich.eduvoid 5622948Ssaidi@eecs.umich.eduTimingSimpleCPU::DcachePort::DTickEvent::process() 5632948Ssaidi@eecs.umich.edu{ 5642630SN/A cpu->completeDataAccess(pkt); 5652623SN/A} 5662623SN/A 5672657Ssaidi@eecs.umich.eduvoid 5682623SN/ATimingSimpleCPU::DcachePort::recvRetry() 5692623SN/A{ 5702623SN/A // we shouldn't get a retry unless we have a packet that we're 5712623SN/A // waiting to transmit 5722623SN/A assert(cpu->dcache_pkt != NULL); 5732623SN/A assert(cpu->_status == DcacheRetry); 5742623SN/A Packet *tmp = cpu->dcache_pkt; 5752657Ssaidi@eecs.umich.edu if (sendTiming(tmp)) { 5762657Ssaidi@eecs.umich.edu cpu->_status = DcacheWaitResponse; 5772657Ssaidi@eecs.umich.edu cpu->dcache_pkt = NULL; 5782657Ssaidi@eecs.umich.edu } 5792623SN/A} 5802623SN/A 5812623SN/A 5822623SN/A//////////////////////////////////////////////////////////////////////// 5832623SN/A// 5842623SN/A// TimingSimpleCPU Simulation Object 5852623SN/A// 5862623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 5872623SN/A 5882623SN/A Param<Counter> max_insts_any_thread; 5892623SN/A Param<Counter> max_insts_all_threads; 5902623SN/A Param<Counter> max_loads_any_thread; 5912623SN/A Param<Counter> max_loads_all_threads; 5923119Sktlim@umich.edu Param<Tick> progress_interval; 5932623SN/A SimObjectParam<MemObject *> mem; 5942901Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 5952623SN/A 5962623SN/A#if FULL_SYSTEM 5972623SN/A SimObjectParam<AlphaITB *> itb; 5982623SN/A SimObjectParam<AlphaDTB *> dtb; 5992623SN/A Param<int> cpu_id; 6002623SN/A Param<Tick> profile; 6012623SN/A#else 6022623SN/A SimObjectParam<Process *> workload; 6032623SN/A#endif // FULL_SYSTEM 6042623SN/A 6052623SN/A Param<int> clock; 6062623SN/A 6072623SN/A Param<bool> defer_registration; 6082623SN/A Param<int> width; 6092623SN/A Param<bool> function_trace; 6102623SN/A Param<Tick> function_trace_start; 6112623SN/A Param<bool> simulate_stalls; 6122623SN/A 6132623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6142623SN/A 6152623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6162623SN/A 6172623SN/A INIT_PARAM(max_insts_any_thread, 6182623SN/A "terminate when any thread reaches this inst count"), 6192623SN/A INIT_PARAM(max_insts_all_threads, 6202623SN/A "terminate when all threads have reached this inst count"), 6212623SN/A INIT_PARAM(max_loads_any_thread, 6222623SN/A "terminate when any thread reaches this load count"), 6232623SN/A INIT_PARAM(max_loads_all_threads, 6242623SN/A "terminate when all threads have reached this load count"), 6253119Sktlim@umich.edu INIT_PARAM(progress_interval, "Progress interval"), 6262623SN/A INIT_PARAM(mem, "memory"), 6272901Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object"), 6282623SN/A 6292623SN/A#if FULL_SYSTEM 6302623SN/A INIT_PARAM(itb, "Instruction TLB"), 6312623SN/A INIT_PARAM(dtb, "Data TLB"), 6322623SN/A INIT_PARAM(cpu_id, "processor ID"), 6332623SN/A INIT_PARAM(profile, ""), 6342623SN/A#else 6352623SN/A INIT_PARAM(workload, "processes to run"), 6362623SN/A#endif // FULL_SYSTEM 6372623SN/A 6382623SN/A INIT_PARAM(clock, "clock speed"), 6392623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 6402623SN/A INIT_PARAM(width, "cpu width"), 6412623SN/A INIT_PARAM(function_trace, "Enable function trace"), 6422623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 6432623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 6442623SN/A 6452623SN/AEND_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 6462623SN/A 6472623SN/A 6482623SN/ACREATE_SIM_OBJECT(TimingSimpleCPU) 6492623SN/A{ 6502623SN/A TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 6512623SN/A params->name = getInstanceName(); 6522623SN/A params->numberOfThreads = 1; 6532623SN/A params->max_insts_any_thread = max_insts_any_thread; 6542623SN/A params->max_insts_all_threads = max_insts_all_threads; 6552623SN/A params->max_loads_any_thread = max_loads_any_thread; 6562623SN/A params->max_loads_all_threads = max_loads_all_threads; 6573119Sktlim@umich.edu params->progress_interval = progress_interval; 6582623SN/A params->deferRegistration = defer_registration; 6592623SN/A params->clock = clock; 6602623SN/A params->functionTrace = function_trace; 6612623SN/A params->functionTraceStart = function_trace_start; 6622623SN/A params->mem = mem; 6632901Ssaidi@eecs.umich.edu params->system = system; 6642623SN/A 6652623SN/A#if FULL_SYSTEM 6662623SN/A params->itb = itb; 6672623SN/A params->dtb = dtb; 6682623SN/A params->cpu_id = cpu_id; 6692623SN/A params->profile = profile; 6702623SN/A#else 6712623SN/A params->process = workload; 6722623SN/A#endif 6732623SN/A 6742623SN/A TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 6752623SN/A return cpu; 6762623SN/A} 6772623SN/A 6782623SN/AREGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 6792623SN/A 680