base.hh revision 11303
12SN/A/*
211147Smitch.hayenga@arm.com * Copyright (c) 2011-2012,2015 ARM Limited
39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc.
48733Sgeoffrey.blake@arm.com * All rights reserved
58733Sgeoffrey.blake@arm.com *
68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall
78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual
88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating
98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software
108733Sgeoffrey.blake@arm.com * licensed hereunder.  You may use the software subject to the license
118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated
128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software,
138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form.
148733Sgeoffrey.blake@arm.com *
151762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
162SN/A * All rights reserved.
172SN/A *
182SN/A * Redistribution and use in source and binary forms, with or without
192SN/A * modification, are permitted provided that the following conditions are
202SN/A * met: redistributions of source code must retain the above copyright
212SN/A * notice, this list of conditions and the following disclaimer;
222SN/A * redistributions in binary form must reproduce the above copyright
232SN/A * notice, this list of conditions and the following disclaimer in the
242SN/A * documentation and/or other materials provided with the distribution;
252SN/A * neither the name of the copyright holders nor the names of its
262SN/A * contributors may be used to endorse or promote products derived from
272SN/A * this software without specific prior written permission.
282SN/A *
292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402665Ssaidi@eecs.umich.edu *
412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
422665Ssaidi@eecs.umich.edu *          Dave Greene
432665Ssaidi@eecs.umich.edu *          Nathan Binkert
442SN/A */
452SN/A
462623SN/A#ifndef __CPU_SIMPLE_BASE_HH__
472623SN/A#define __CPU_SIMPLE_BASE_HH__
482SN/A
491354SN/A#include "base/statistics.hh"
506658Snate@binkert.org#include "config/the_isa.hh"
511717SN/A#include "cpu/base.hh"
528887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh"
5310319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh"
548229Snate@binkert.org#include "cpu/pc_event.hh"
552683Sktlim@umich.edu#include "cpu/simple_thread.hh"
561354SN/A#include "cpu/static_inst.hh"
572387SN/A#include "mem/packet.hh"
582387SN/A#include "mem/port.hh"
592387SN/A#include "mem/request.hh"
6056SN/A#include "sim/eventq.hh"
618779Sgblack@eecs.umich.edu#include "sim/full_system.hh"
625348Ssaidi@eecs.umich.edu#include "sim/system.hh"
632SN/A
642SN/A// forward declarations
658779Sgblack@eecs.umich.educlass Checkpoint;
668779Sgblack@eecs.umich.educlass Process;
672SN/Aclass Processor;
688779Sgblack@eecs.umich.educlass ThreadContext;
692SN/A
704182Sgblack@eecs.umich.edunamespace TheISA
714182Sgblack@eecs.umich.edu{
728779Sgblack@eecs.umich.edu    class DTB;
738779Sgblack@eecs.umich.edu    class ITB;
744182Sgblack@eecs.umich.edu}
752SN/A
762SN/Anamespace Trace {
772SN/A    class InstRecord;
782SN/A}
792SN/A
808737Skoansin.tan@gmail.comstruct BaseSimpleCPUParams;
8110061Sandreas@sandberg.pp.seclass BPredUnit;
8211147Smitch.hayenga@arm.comclass SimpleExecContext;
832420SN/A
8411147Smitch.hayenga@arm.comclass BaseSimpleCPU : public BaseCPU
852SN/A{
862107SN/A  protected:
8711147Smitch.hayenga@arm.com    ThreadID curThread;
8810061Sandreas@sandberg.pp.se    BPredUnit *branchPred;
8910061Sandreas@sandberg.pp.se
9011147Smitch.hayenga@arm.com    void checkPcEventQueue();
9111147Smitch.hayenga@arm.com    void swapActiveThread();
922SN/A
931400SN/A  public:
945529Snate@binkert.org    BaseSimpleCPU(BaseSimpleCPUParams *params);
952623SN/A    virtual ~BaseSimpleCPU();
9611168Sandreas.hansson@arm.com    void wakeup(ThreadID tid) override;
9711169Sandreas.hansson@arm.com    void init() override;
981400SN/A  public:
9911147Smitch.hayenga@arm.com    Trace::InstRecord *traceData;
1008733Sgeoffrey.blake@arm.com    CheckerCPU *checker;
1018887Sgeoffrey.blake@arm.com
10211147Smitch.hayenga@arm.com    std::vector<SimpleExecContext*> threadInfo;
10311147Smitch.hayenga@arm.com    std::list<ThreadID> activeThreads;
10411147Smitch.hayenga@arm.com
10511147Smitch.hayenga@arm.com    /** Current instruction */
10611147Smitch.hayenga@arm.com    TheISA::MachInst inst;
10711147Smitch.hayenga@arm.com    StaticInstPtr curStaticInst;
10811147Smitch.hayenga@arm.com    StaticInstPtr curMacroStaticInst;
10911147Smitch.hayenga@arm.com
1105169Ssaidi@eecs.umich.edu  protected:
1115496Ssaidi@eecs.umich.edu    enum Status {
1125496Ssaidi@eecs.umich.edu        Idle,
1135496Ssaidi@eecs.umich.edu        Running,
1148276SAli.Saidi@ARM.com        Faulting,
1155894Sgblack@eecs.umich.edu        ITBWaitResponse,
1165496Ssaidi@eecs.umich.edu        IcacheRetry,
1175496Ssaidi@eecs.umich.edu        IcacheWaitResponse,
1185496Ssaidi@eecs.umich.edu        IcacheWaitSwitch,
1195894Sgblack@eecs.umich.edu        DTBWaitResponse,
1205496Ssaidi@eecs.umich.edu        DcacheRetry,
1215496Ssaidi@eecs.umich.edu        DcacheWaitResponse,
1225496Ssaidi@eecs.umich.edu        DcacheWaitSwitch,
1235496Ssaidi@eecs.umich.edu    };
1245496Ssaidi@eecs.umich.edu
1255496Ssaidi@eecs.umich.edu    Status _status;
1265496Ssaidi@eecs.umich.edu
1275169Ssaidi@eecs.umich.edu  public:
1282SN/A    Addr dbg_vtophys(Addr addr);
1292SN/A
1304377Sgblack@eecs.umich.edu
1312623SN/A    void checkForInterrupts();
1325894Sgblack@eecs.umich.edu    void setupFetchRequest(Request *req);
1332623SN/A    void preExecute();
1342623SN/A    void postExecute();
13510379Sandreas.hansson@arm.com    void advancePC(const Fault &fault);
136180SN/A
13711169Sandreas.hansson@arm.com    void haltContext(ThreadID thread_num) override;
1382SN/A
1392SN/A    // statistics
14011169Sandreas.hansson@arm.com    void regStats() override;
14111169Sandreas.hansson@arm.com    void resetStats() override;
1422SN/A
14311169Sandreas.hansson@arm.com    void startup() override;
1449461Snilay@cs.wisc.edu
14511147Smitch.hayenga@arm.com    virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
14611147Smitch.hayenga@arm.com                          unsigned flags) = 0;
147707SN/A
14811303Ssteve.reinhardt@amd.com    virtual Fault initiateMemRead(Addr addr, unsigned size, unsigned flags) = 0;
14911303Ssteve.reinhardt@amd.com
15011147Smitch.hayenga@arm.com    virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr,
15111147Smitch.hayenga@arm.com                           unsigned flags, uint64_t* res) = 0;
1528834Satgutier@umich.edu
15311147Smitch.hayenga@arm.com    void countInst();
15411169Sandreas.hansson@arm.com    Counter totalInsts() const override;
15511169Sandreas.hansson@arm.com    Counter totalOps() const override;
15610193SCurtis.Dunham@arm.com
15711168Sandreas.hansson@arm.com    void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
15811168Sandreas.hansson@arm.com    void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
1592SN/A
1602SN/A};
1612SN/A
1622623SN/A#endif // __CPU_SIMPLE_BASE_HH__
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