base.hh revision 11303
12817Sksewell@umich.edu/* 22817Sksewell@umich.edu * Copyright (c) 2011-2012,2015 ARM Limited 32817Sksewell@umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 42817Sksewell@umich.edu * All rights reserved 52817Sksewell@umich.edu * 62817Sksewell@umich.edu * The license below extends only to copyright in the software and shall 72817Sksewell@umich.edu * not be construed as granting a license to any other intellectual 82817Sksewell@umich.edu * property including but not limited to intellectual property relating 92817Sksewell@umich.edu * to a hardware implementation of the functionality of the software 102817Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 112817Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 122817Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 132817Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 142817Sksewell@umich.edu * 152817Sksewell@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 162817Sksewell@umich.edu * All rights reserved. 172817Sksewell@umich.edu * 182817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 192817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 202817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 212817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 222817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 232817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 242817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 252817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 262817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272817Sksewell@umich.edu * this software without specific prior written permission. 282817Sksewell@umich.edu * 294202Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 334202Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355192Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365192Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375192Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385192Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395192Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405192Ssaidi@eecs.umich.edu * 415192Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 425192Ssaidi@eecs.umich.edu * Dave Greene 435192Ssaidi@eecs.umich.edu * Nathan Binkert 445192Ssaidi@eecs.umich.edu */ 454202Sbinkertn@umich.edu 464486Sbinkertn@umich.edu#ifndef __CPU_SIMPLE_BASE_HH__ 474486Sbinkertn@umich.edu#define __CPU_SIMPLE_BASE_HH__ 484486Sbinkertn@umich.edu 494486Sbinkertn@umich.edu#include "base/statistics.hh" 504202Sbinkertn@umich.edu#include "config/the_isa.hh" 514202Sbinkertn@umich.edu#include "cpu/base.hh" 524202Sbinkertn@umich.edu#include "cpu/checker/cpu.hh" 534202Sbinkertn@umich.edu#include "cpu/exec_context.hh" 544202Sbinkertn@umich.edu#include "cpu/pc_event.hh" 554202Sbinkertn@umich.edu#include "cpu/simple_thread.hh" 564202Sbinkertn@umich.edu#include "cpu/static_inst.hh" 574202Sbinkertn@umich.edu#include "mem/packet.hh" 584202Sbinkertn@umich.edu#include "mem/port.hh" 594202Sbinkertn@umich.edu#include "mem/request.hh" 604202Sbinkertn@umich.edu#include "sim/eventq.hh" 614202Sbinkertn@umich.edu#include "sim/full_system.hh" 624202Sbinkertn@umich.edu#include "sim/system.hh" 634202Sbinkertn@umich.edu 644202Sbinkertn@umich.edu// forward declarations 654202Sbinkertn@umich.educlass Checkpoint; 664202Sbinkertn@umich.educlass Process; 674202Sbinkertn@umich.educlass Processor; 682817Sksewell@umich.educlass ThreadContext; 695192Ssaidi@eecs.umich.edu 705192Ssaidi@eecs.umich.edunamespace TheISA 715192Ssaidi@eecs.umich.edu{ 725192Ssaidi@eecs.umich.edu class DTB; 735192Ssaidi@eecs.umich.edu class ITB; 745192Ssaidi@eecs.umich.edu} 755192Ssaidi@eecs.umich.edu 765192Ssaidi@eecs.umich.edunamespace Trace { 775192Ssaidi@eecs.umich.edu class InstRecord; 785192Ssaidi@eecs.umich.edu} 795192Ssaidi@eecs.umich.edu 805192Ssaidi@eecs.umich.edustruct BaseSimpleCPUParams; 815192Ssaidi@eecs.umich.educlass BPredUnit; 825192Ssaidi@eecs.umich.educlass SimpleExecContext; 835192Ssaidi@eecs.umich.edu 844202Sbinkertn@umich.educlass BaseSimpleCPU : public BaseCPU 854202Sbinkertn@umich.edu{ 864202Sbinkertn@umich.edu protected: 874202Sbinkertn@umich.edu ThreadID curThread; 884202Sbinkertn@umich.edu BPredUnit *branchPred; 894202Sbinkertn@umich.edu 904202Sbinkertn@umich.edu void checkPcEventQueue(); 914202Sbinkertn@umich.edu void swapActiveThread(); 924202Sbinkertn@umich.edu 934202Sbinkertn@umich.edu public: 944202Sbinkertn@umich.edu BaseSimpleCPU(BaseSimpleCPUParams *params); 954202Sbinkertn@umich.edu virtual ~BaseSimpleCPU(); 964202Sbinkertn@umich.edu void wakeup(ThreadID tid) override; 974202Sbinkertn@umich.edu void init() override; 984202Sbinkertn@umich.edu public: 994202Sbinkertn@umich.edu Trace::InstRecord *traceData; 1004202Sbinkertn@umich.edu CheckerCPU *checker; 1012817Sksewell@umich.edu 1024202Sbinkertn@umich.edu std::vector<SimpleExecContext*> threadInfo; 1034497Sbinkertn@umich.edu std::list<ThreadID> activeThreads; 1044202Sbinkertn@umich.edu 105 /** Current instruction */ 106 TheISA::MachInst inst; 107 StaticInstPtr curStaticInst; 108 StaticInstPtr curMacroStaticInst; 109 110 protected: 111 enum Status { 112 Idle, 113 Running, 114 Faulting, 115 ITBWaitResponse, 116 IcacheRetry, 117 IcacheWaitResponse, 118 IcacheWaitSwitch, 119 DTBWaitResponse, 120 DcacheRetry, 121 DcacheWaitResponse, 122 DcacheWaitSwitch, 123 }; 124 125 Status _status; 126 127 public: 128 Addr dbg_vtophys(Addr addr); 129 130 131 void checkForInterrupts(); 132 void setupFetchRequest(Request *req); 133 void preExecute(); 134 void postExecute(); 135 void advancePC(const Fault &fault); 136 137 void haltContext(ThreadID thread_num) override; 138 139 // statistics 140 void regStats() override; 141 void resetStats() override; 142 143 void startup() override; 144 145 virtual Fault readMem(Addr addr, uint8_t* data, unsigned size, 146 unsigned flags) = 0; 147 148 virtual Fault initiateMemRead(Addr addr, unsigned size, unsigned flags) = 0; 149 150 virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr, 151 unsigned flags, uint64_t* res) = 0; 152 153 void countInst(); 154 Counter totalInsts() const override; 155 Counter totalOps() const override; 156 157 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 158 void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 159 160}; 161 162#endif // __CPU_SIMPLE_BASE_HH__ 163