base.cc revision 8737
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2010-2011 ARM Limited 37338SAli.Saidi@ARM.com * All rights reserved 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137338SAli.Saidi@ARM.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412SN/A */ 422SN/A 436216Snate@binkert.org#include "arch/faults.hh" 442439SN/A#include "arch/utility.hh" 458229Snate@binkert.org#include "base/loader/symtab.hh" 466216Snate@binkert.org#include "base/cp_annotate.hh" 47146SN/A#include "base/cprintf.hh" 48146SN/A#include "base/inifile.hh" 49146SN/A#include "base/misc.hh" 50146SN/A#include "base/pollevent.hh" 51146SN/A#include "base/range.hh" 52146SN/A#include "base/trace.hh" 536216Snate@binkert.org#include "base/types.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 558733Sgeoffrey.blake@arm.com#include "config/use_checker.hh" 568229Snate@binkert.org#include "cpu/simple/base.hh" 571717SN/A#include "cpu/base.hh" 58146SN/A#include "cpu/exetrace.hh" 591977SN/A#include "cpu/profile.hh" 602683Sktlim@umich.edu#include "cpu/simple_thread.hh" 611717SN/A#include "cpu/smt.hh" 62146SN/A#include "cpu/static_inst.hh" 632683Sktlim@umich.edu#include "cpu/thread_context.hh" 648232Snate@binkert.org#include "debug/Decode.hh" 658232Snate@binkert.org#include "debug/Fetch.hh" 668232Snate@binkert.org#include "debug/Quiesce.hh" 673348Sbinkertn@umich.edu#include "mem/packet.hh" 686105Ssteve.reinhardt@amd.com#include "mem/request.hh" 696216Snate@binkert.org#include "params/BaseSimpleCPU.hh" 702036SN/A#include "sim/byteswap.hh" 71146SN/A#include "sim/debug.hh" 7256SN/A#include "sim/sim_events.hh" 7356SN/A#include "sim/sim_object.hh" 74695SN/A#include "sim/stats.hh" 752901Ssaidi@eecs.umich.edu#include "sim/system.hh" 762SN/A 771858SN/A#if FULL_SYSTEM 783565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 793565Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 802171SN/A#include "arch/tlb.hh" 812170SN/A#include "arch/vtophys.hh" 82146SN/A#else // !FULL_SYSTEM 832462SN/A#include "mem/mem_object.hh" 84146SN/A#endif // FULL_SYSTEM 852SN/A 868733Sgeoffrey.blake@arm.com#if USE_CHECKER 878733Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 888733Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 898733Sgeoffrey.blake@arm.com#endif 908733Sgeoffrey.blake@arm.com 912SN/Ausing namespace std; 922449SN/Ausing namespace TheISA; 931355SN/A 945529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 954495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 96224SN/A{ 971858SN/A#if FULL_SYSTEM 982683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 992420SN/A#else 1005529Snate@binkert.org thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], 1016331Sgblack@eecs.umich.edu p->itb, p->dtb); 1022420SN/A#endif // !FULL_SYSTEM 1032SN/A 1046029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 1052672Sktlim@umich.edu 1062683Sktlim@umich.edu tc = thread->getTC(); 1072SN/A 1088733Sgeoffrey.blake@arm.com#if USE_CHECKER 1098733Sgeoffrey.blake@arm.com if (p->checker) { 1108733Sgeoffrey.blake@arm.com BaseCPU *temp_checker = p->checker; 1118733Sgeoffrey.blake@arm.com checker = dynamic_cast<CheckerCPU *>(temp_checker); 1128733Sgeoffrey.blake@arm.com#if FULL_SYSTEM 1138733Sgeoffrey.blake@arm.com checker->setSystem(p->system); 1148733Sgeoffrey.blake@arm.com#endif 1158733Sgeoffrey.blake@arm.com // Manipulate thread context 1168733Sgeoffrey.blake@arm.com ThreadContext *cpu_tc = tc; 1178733Sgeoffrey.blake@arm.com tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 1188733Sgeoffrey.blake@arm.com } else { 1198733Sgeoffrey.blake@arm.com checker = NULL; 1208733Sgeoffrey.blake@arm.com } 1218733Sgeoffrey.blake@arm.com#endif 1228733Sgeoffrey.blake@arm.com 1232SN/A numInst = 0; 124334SN/A startNumInst = 0; 125140SN/A numLoad = 0; 126334SN/A startNumLoad = 0; 1272SN/A lastIcacheStall = 0; 1282SN/A lastDcacheStall = 0; 1292SN/A 1302680Sktlim@umich.edu threadContexts.push_back(tc); 1314377Sgblack@eecs.umich.edu 1325169Ssaidi@eecs.umich.edu 1334377Sgblack@eecs.umich.edu fetchOffset = 0; 1344377Sgblack@eecs.umich.edu stayAtPC = false; 1352SN/A} 1362SN/A 1372623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1382SN/A{ 1392SN/A} 1402SN/A 141180SN/Avoid 1428737Skoansin.tan@gmail.comBaseSimpleCPU::deallocateContext(ThreadID thread_num) 143393SN/A{ 144393SN/A // for now, these are equivalent 145393SN/A suspendContext(thread_num); 146393SN/A} 147384SN/A 148384SN/A 149393SN/Avoid 1508737Skoansin.tan@gmail.comBaseSimpleCPU::haltContext(ThreadID thread_num) 151393SN/A{ 152393SN/A // for now, these are equivalent 153393SN/A suspendContext(thread_num); 154393SN/A} 155384SN/A 156189SN/A 157189SN/Avoid 1582623SN/ABaseSimpleCPU::regStats() 1592SN/A{ 160729SN/A using namespace Stats; 161334SN/A 1622SN/A BaseCPU::regStats(); 1632SN/A 1642SN/A numInsts 1652SN/A .name(name() + ".num_insts") 1662SN/A .desc("Number of instructions executed") 1672SN/A ; 1682SN/A 1697897Shestness@cs.utexas.edu numIntAluAccesses 1707897Shestness@cs.utexas.edu .name(name() + ".num_int_alu_accesses") 1717897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 1727897Shestness@cs.utexas.edu ; 1737897Shestness@cs.utexas.edu 1747897Shestness@cs.utexas.edu numFpAluAccesses 1757897Shestness@cs.utexas.edu .name(name() + ".num_fp_alu_accesses") 1767897Shestness@cs.utexas.edu .desc("Number of float alu accesses") 1777897Shestness@cs.utexas.edu ; 1787897Shestness@cs.utexas.edu 1797897Shestness@cs.utexas.edu numCallsReturns 1807897Shestness@cs.utexas.edu .name(name() + ".num_func_calls") 1817897Shestness@cs.utexas.edu .desc("number of times a function call or return occured") 1827897Shestness@cs.utexas.edu ; 1837897Shestness@cs.utexas.edu 1847897Shestness@cs.utexas.edu numCondCtrlInsts 1857897Shestness@cs.utexas.edu .name(name() + ".num_conditional_control_insts") 1867897Shestness@cs.utexas.edu .desc("number of instructions that are conditional controls") 1877897Shestness@cs.utexas.edu ; 1887897Shestness@cs.utexas.edu 1897897Shestness@cs.utexas.edu numIntInsts 1907897Shestness@cs.utexas.edu .name(name() + ".num_int_insts") 1917897Shestness@cs.utexas.edu .desc("number of integer instructions") 1927897Shestness@cs.utexas.edu ; 1937897Shestness@cs.utexas.edu 1947897Shestness@cs.utexas.edu numFpInsts 1957897Shestness@cs.utexas.edu .name(name() + ".num_fp_insts") 1967897Shestness@cs.utexas.edu .desc("number of float instructions") 1977897Shestness@cs.utexas.edu ; 1987897Shestness@cs.utexas.edu 1997897Shestness@cs.utexas.edu numIntRegReads 2007897Shestness@cs.utexas.edu .name(name() + ".num_int_register_reads") 2017897Shestness@cs.utexas.edu .desc("number of times the integer registers were read") 2027897Shestness@cs.utexas.edu ; 2037897Shestness@cs.utexas.edu 2047897Shestness@cs.utexas.edu numIntRegWrites 2057897Shestness@cs.utexas.edu .name(name() + ".num_int_register_writes") 2067897Shestness@cs.utexas.edu .desc("number of times the integer registers were written") 2077897Shestness@cs.utexas.edu ; 2087897Shestness@cs.utexas.edu 2097897Shestness@cs.utexas.edu numFpRegReads 2107897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_reads") 2117897Shestness@cs.utexas.edu .desc("number of times the floating registers were read") 2127897Shestness@cs.utexas.edu ; 2137897Shestness@cs.utexas.edu 2147897Shestness@cs.utexas.edu numFpRegWrites 2157897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_writes") 2167897Shestness@cs.utexas.edu .desc("number of times the floating registers were written") 2177897Shestness@cs.utexas.edu ; 2187897Shestness@cs.utexas.edu 2192SN/A numMemRefs 2207897Shestness@cs.utexas.edu .name(name()+".num_mem_refs") 2217897Shestness@cs.utexas.edu .desc("number of memory refs") 2227897Shestness@cs.utexas.edu ; 2237897Shestness@cs.utexas.edu 2247897Shestness@cs.utexas.edu numStoreInsts 2257897Shestness@cs.utexas.edu .name(name() + ".num_store_insts") 2267897Shestness@cs.utexas.edu .desc("Number of store instructions") 2277897Shestness@cs.utexas.edu ; 2287897Shestness@cs.utexas.edu 2297897Shestness@cs.utexas.edu numLoadInsts 2307897Shestness@cs.utexas.edu .name(name() + ".num_load_insts") 2317897Shestness@cs.utexas.edu .desc("Number of load instructions") 2322SN/A ; 2332SN/A 2341001SN/A notIdleFraction 2351001SN/A .name(name() + ".not_idle_fraction") 2361001SN/A .desc("Percentage of non-idle cycles") 2371001SN/A ; 2381001SN/A 2392SN/A idleFraction 2402SN/A .name(name() + ".idle_fraction") 2412SN/A .desc("Percentage of idle cycles") 2422SN/A ; 2432SN/A 2447897Shestness@cs.utexas.edu numBusyCycles 2457897Shestness@cs.utexas.edu .name(name() + ".num_busy_cycles") 2467897Shestness@cs.utexas.edu .desc("Number of busy cycles") 2477897Shestness@cs.utexas.edu ; 2487897Shestness@cs.utexas.edu 2497897Shestness@cs.utexas.edu numIdleCycles 2507897Shestness@cs.utexas.edu .name(name()+".num_idle_cycles") 2517897Shestness@cs.utexas.edu .desc("Number of idle cycles") 2527897Shestness@cs.utexas.edu ; 2537897Shestness@cs.utexas.edu 2542SN/A icacheStallCycles 2552SN/A .name(name() + ".icache_stall_cycles") 2562SN/A .desc("ICache total stall cycles") 2572SN/A .prereq(icacheStallCycles) 2582SN/A ; 2592SN/A 2602SN/A dcacheStallCycles 2612SN/A .name(name() + ".dcache_stall_cycles") 2622SN/A .desc("DCache total stall cycles") 2632SN/A .prereq(dcacheStallCycles) 2642SN/A ; 2652SN/A 2662390SN/A icacheRetryCycles 2672390SN/A .name(name() + ".icache_retry_cycles") 2682390SN/A .desc("ICache total retry cycles") 2692390SN/A .prereq(icacheRetryCycles) 2702390SN/A ; 2712390SN/A 2722390SN/A dcacheRetryCycles 2732390SN/A .name(name() + ".dcache_retry_cycles") 2742390SN/A .desc("DCache total retry cycles") 2752390SN/A .prereq(dcacheRetryCycles) 2762390SN/A ; 2772390SN/A 278385SN/A idleFraction = constant(1.0) - notIdleFraction; 2797897Shestness@cs.utexas.edu numIdleCycles = idleFraction * numCycles; 2807897Shestness@cs.utexas.edu numBusyCycles = (notIdleFraction)*numCycles; 2812SN/A} 2822SN/A 2832SN/Avoid 2842623SN/ABaseSimpleCPU::resetStats() 285334SN/A{ 2862361SN/A// startNumInst = numInst; 2875496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 288334SN/A} 289334SN/A 290334SN/Avoid 2912623SN/ABaseSimpleCPU::serialize(ostream &os) 2922SN/A{ 2935496Ssaidi@eecs.umich.edu SERIALIZE_ENUM(_status); 294921SN/A BaseCPU::serialize(os); 2952915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 2962915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 2972683Sktlim@umich.edu thread->serialize(os); 2982SN/A} 2992SN/A 3002SN/Avoid 3012623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 3022SN/A{ 3035496Ssaidi@eecs.umich.edu UNSERIALIZE_ENUM(_status); 304921SN/A BaseCPU::unserialize(cp, section); 3052915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 3062915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 3072SN/A} 3082SN/A 3092SN/Avoid 3106221Snate@binkert.orgchange_thread_state(ThreadID tid, int activate, int priority) 3112SN/A{ 3122SN/A} 3132SN/A 3141858SN/A#if FULL_SYSTEM 3152SN/AAddr 3162623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 3172SN/A{ 3182680Sktlim@umich.edu return vtophys(tc, addr); 3192SN/A} 3202SN/A#endif // FULL_SYSTEM 3212SN/A 3221858SN/A#if FULL_SYSTEM 3232SN/Avoid 3245807Snate@binkert.orgBaseSimpleCPU::wakeup() 3252SN/A{ 3265807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 3275807Snate@binkert.org return; 3282SN/A 3295807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3305807Snate@binkert.org thread->activate(); 3312SN/A} 3322SN/A#endif // FULL_SYSTEM 3332SN/A 3342SN/Avoid 3352623SN/ABaseSimpleCPU::checkForInterrupts() 3362SN/A{ 3371858SN/A#if FULL_SYSTEM 3385704Snate@binkert.org if (checkInterrupts(tc)) { 3395647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3402SN/A 3413520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3427338SAli.Saidi@ARM.com fetchOffset = 0; 3435647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3443520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3457408Sgblack@eecs.umich.edu predecoder.reset(); 3462SN/A } 3472SN/A } 3482SN/A#endif 3492623SN/A} 3502SN/A 3512623SN/A 3525894Sgblack@eecs.umich.eduvoid 3532662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3542623SN/A{ 3557720Sgblack@eecs.umich.edu Addr instAddr = thread->instAddr(); 3564495Sacolyte@umich.edu 3572623SN/A // set up memory request for instruction fetch 3587720Sgblack@eecs.umich.edu DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 3592623SN/A 3607720Sgblack@eecs.umich.edu Addr fetchPC = (instAddr & PCMask) + fetchOffset; 3617720Sgblack@eecs.umich.edu req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr); 3622623SN/A} 3632623SN/A 3642623SN/A 3652623SN/Avoid 3662623SN/ABaseSimpleCPU::preExecute() 3672623SN/A{ 3682SN/A // maintain $r0 semantics 3692683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3702427SN/A#if THE_ISA == ALPHA_ISA 3712683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3722427SN/A#endif // ALPHA_ISA 3732SN/A 3742623SN/A // check for instruction-count-based events 3752623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3767897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 3772SN/A 3782623SN/A // decode the instruction 3792623SN/A inst = gtoh(inst); 3804377Sgblack@eecs.umich.edu 3817720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 3824377Sgblack@eecs.umich.edu 3837720Sgblack@eecs.umich.edu if (isRomMicroPC(pcState.microPC())) { 3845665Sgblack@eecs.umich.edu stayAtPC = false; 3857720Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 3867720Sgblack@eecs.umich.edu curMacroStaticInst); 3875665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 3885665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 3894181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 3904181Sgblack@eecs.umich.edu 3914181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 3924182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 3934182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 3944182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 3957720Sgblack@eecs.umich.edu Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 3964593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 3977720Sgblack@eecs.umich.edu predecoder.moreBytes(pcState, fetchPC, inst); 3984593Sgblack@eecs.umich.edu //else 3994593Sgblack@eecs.umich.edu // predecoder.process(); 4004377Sgblack@eecs.umich.edu 4014377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 4024377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 4034377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 4044377Sgblack@eecs.umich.edu stayAtPC = false; 4057720Sgblack@eecs.umich.edu ExtMachInst machInst = predecoder.getExtMachInst(pcState); 4067720Sgblack@eecs.umich.edu thread->pcState(pcState); 4078541Sgblack@eecs.umich.edu instPtr = thread->decoder.decode(machInst, pcState.instAddr()); 4084377Sgblack@eecs.umich.edu } else { 4094377Sgblack@eecs.umich.edu stayAtPC = true; 4104377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 4114377Sgblack@eecs.umich.edu } 4124181Sgblack@eecs.umich.edu 4134181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 4144181Sgblack@eecs.umich.edu //out micro ops 4154539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4163276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4177720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4183280Sgblack@eecs.umich.edu } else { 4193280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4203276Sgblack@eecs.umich.edu } 4213276Sgblack@eecs.umich.edu } else { 4223276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4237720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4243276Sgblack@eecs.umich.edu } 4253276Sgblack@eecs.umich.edu 4264181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4274181Sgblack@eecs.umich.edu if(curStaticInst) 4284181Sgblack@eecs.umich.edu { 4294522Ssaidi@eecs.umich.edu#if TRACING_ON 4307823Ssteve.reinhardt@amd.com traceData = tracer->getInstRecord(curTick(), tc, 4317720Sgblack@eecs.umich.edu curStaticInst, thread->pcState(), curMacroStaticInst); 4322470SN/A 4334181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4344181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4354522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4364181Sgblack@eecs.umich.edu } 4372623SN/A} 4382623SN/A 4392623SN/Avoid 4402623SN/ABaseSimpleCPU::postExecute() 4412623SN/A{ 4427720Sgblack@eecs.umich.edu assert(curStaticInst); 4437720Sgblack@eecs.umich.edu 4447720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 4457720Sgblack@eecs.umich.edu Addr instAddr = pc.instAddr(); 4462623SN/A#if FULL_SYSTEM 4477720Sgblack@eecs.umich.edu if (thread->profile) { 4483577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4497720Sgblack@eecs.umich.edu thread->profilePC = usermode ? 1 : instAddr; 4505086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4512623SN/A if (node) 4522683Sktlim@umich.edu thread->profileNode = node; 4532623SN/A } 4542420SN/A#endif 4552SN/A 4562623SN/A if (curStaticInst->isMemRef()) { 4572623SN/A numMemRefs++; 4582SN/A } 4592SN/A 4602623SN/A if (curStaticInst->isLoad()) { 4612623SN/A ++numLoad; 4622623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4632623SN/A } 4642SN/A 4655953Ssaidi@eecs.umich.edu if (CPA::available()) { 4667720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 4675953Ssaidi@eecs.umich.edu } 4685953Ssaidi@eecs.umich.edu 4697897Shestness@cs.utexas.edu /* Power model statistics */ 4707897Shestness@cs.utexas.edu //integer alu accesses 4717897Shestness@cs.utexas.edu if (curStaticInst->isInteger()){ 4727897Shestness@cs.utexas.edu numIntAluAccesses++; 4737897Shestness@cs.utexas.edu numIntInsts++; 4747897Shestness@cs.utexas.edu } 4757897Shestness@cs.utexas.edu 4767897Shestness@cs.utexas.edu //float alu accesses 4777897Shestness@cs.utexas.edu if (curStaticInst->isFloating()){ 4787897Shestness@cs.utexas.edu numFpAluAccesses++; 4797897Shestness@cs.utexas.edu numFpInsts++; 4807897Shestness@cs.utexas.edu } 4817897Shestness@cs.utexas.edu 4827897Shestness@cs.utexas.edu //number of function calls/returns to get window accesses 4837897Shestness@cs.utexas.edu if (curStaticInst->isCall() || curStaticInst->isReturn()){ 4847897Shestness@cs.utexas.edu numCallsReturns++; 4857897Shestness@cs.utexas.edu } 4867897Shestness@cs.utexas.edu 4877897Shestness@cs.utexas.edu //the number of branch predictions that will be made 4887897Shestness@cs.utexas.edu if (curStaticInst->isCondCtrl()){ 4897897Shestness@cs.utexas.edu numCondCtrlInsts++; 4907897Shestness@cs.utexas.edu } 4917897Shestness@cs.utexas.edu 4927897Shestness@cs.utexas.edu //result bus acceses 4937897Shestness@cs.utexas.edu if (curStaticInst->isLoad()){ 4947897Shestness@cs.utexas.edu numLoadInsts++; 4957897Shestness@cs.utexas.edu } 4967897Shestness@cs.utexas.edu 4977897Shestness@cs.utexas.edu if (curStaticInst->isStore()){ 4987897Shestness@cs.utexas.edu numStoreInsts++; 4997897Shestness@cs.utexas.edu } 5007897Shestness@cs.utexas.edu /* End power model statistics */ 5017897Shestness@cs.utexas.edu 5027720Sgblack@eecs.umich.edu traceFunctions(instAddr); 5032644Sstever@eecs.umich.edu 5042644Sstever@eecs.umich.edu if (traceData) { 5054046Sbinkertn@umich.edu traceData->dump(); 5064046Sbinkertn@umich.edu delete traceData; 5074046Sbinkertn@umich.edu traceData = NULL; 5082644Sstever@eecs.umich.edu } 5092623SN/A} 5102SN/A 5112SN/A 5122623SN/Avoid 5132623SN/ABaseSimpleCPU::advancePC(Fault fault) 5142623SN/A{ 5154377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 5164377Sgblack@eecs.umich.edu fetchOffset = 0; 5172090SN/A if (fault != NoFault) { 5183905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5197678Sgblack@eecs.umich.edu fault->invoke(tc, curStaticInst); 5205120Sgblack@eecs.umich.edu predecoder.reset(); 5214377Sgblack@eecs.umich.edu } else { 5227720Sgblack@eecs.umich.edu if (curStaticInst) { 5237720Sgblack@eecs.umich.edu if (curStaticInst->isLastMicroop()) 5247720Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5257720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5267720Sgblack@eecs.umich.edu TheISA::advancePC(pcState, curStaticInst); 5277720Sgblack@eecs.umich.edu thread->pcState(pcState); 5283276Sgblack@eecs.umich.edu } 5292SN/A } 5302SN/A} 5312SN/A 5325250Sksewell@umich.edu/*Fault 5335222Sksewell@umich.eduBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 5345222Sksewell@umich.edu{ 5355222Sksewell@umich.edu // translate to physical address 5365222Sksewell@umich.edu Fault fault = NoFault; 5375222Sksewell@umich.edu int CacheID = Op & 0x3; // Lower 3 bits identify Cache 5385222Sksewell@umich.edu int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 5395222Sksewell@umich.edu if(CacheID > 1) 5405222Sksewell@umich.edu { 5415222Sksewell@umich.edu warn("CacheOps not implemented for secondary/tertiary caches\n"); 5425222Sksewell@umich.edu } 5435222Sksewell@umich.edu else 5445222Sksewell@umich.edu { 5455222Sksewell@umich.edu switch(CacheOP) 5465222Sksewell@umich.edu { // Fill Packet Type 5475222Sksewell@umich.edu case 0: warn("Invalidate Cache Op\n"); 5485222Sksewell@umich.edu break; 5495222Sksewell@umich.edu case 1: warn("Index Load Tag Cache Op\n"); 5505222Sksewell@umich.edu break; 5515222Sksewell@umich.edu case 2: warn("Index Store Tag Cache Op\n"); 5525222Sksewell@umich.edu break; 5535222Sksewell@umich.edu case 4: warn("Hit Invalidate Cache Op\n"); 5545222Sksewell@umich.edu break; 5555222Sksewell@umich.edu case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 5565222Sksewell@umich.edu break; 5575222Sksewell@umich.edu case 6: warn("Hit Writeback\n"); 5585222Sksewell@umich.edu break; 5595222Sksewell@umich.edu case 7: warn("Fetch & Lock Cache Op\n"); 5605222Sksewell@umich.edu break; 5615222Sksewell@umich.edu default: warn("Unimplemented Cache Op\n"); 5625222Sksewell@umich.edu } 5635222Sksewell@umich.edu } 5645222Sksewell@umich.edu return fault; 5655250Sksewell@umich.edu}*/ 566