base.cc revision 8737
1/* 2 * Copyright (c) 2010-2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#include "arch/faults.hh" 44#include "arch/utility.hh" 45#include "base/loader/symtab.hh" 46#include "base/cp_annotate.hh" 47#include "base/cprintf.hh" 48#include "base/inifile.hh" 49#include "base/misc.hh" 50#include "base/pollevent.hh" 51#include "base/range.hh" 52#include "base/trace.hh" 53#include "base/types.hh" 54#include "config/the_isa.hh" 55#include "config/use_checker.hh" 56#include "cpu/simple/base.hh" 57#include "cpu/base.hh" 58#include "cpu/exetrace.hh" 59#include "cpu/profile.hh" 60#include "cpu/simple_thread.hh" 61#include "cpu/smt.hh" 62#include "cpu/static_inst.hh" 63#include "cpu/thread_context.hh" 64#include "debug/Decode.hh" 65#include "debug/Fetch.hh" 66#include "debug/Quiesce.hh" 67#include "mem/packet.hh" 68#include "mem/request.hh" 69#include "params/BaseSimpleCPU.hh" 70#include "sim/byteswap.hh" 71#include "sim/debug.hh" 72#include "sim/sim_events.hh" 73#include "sim/sim_object.hh" 74#include "sim/stats.hh" 75#include "sim/system.hh" 76 77#if FULL_SYSTEM 78#include "arch/kernel_stats.hh" 79#include "arch/stacktrace.hh" 80#include "arch/tlb.hh" 81#include "arch/vtophys.hh" 82#else // !FULL_SYSTEM 83#include "mem/mem_object.hh" 84#endif // FULL_SYSTEM 85 86#if USE_CHECKER 87#include "cpu/checker/cpu.hh" 88#include "cpu/checker/thread_context.hh" 89#endif 90 91using namespace std; 92using namespace TheISA; 93 94BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 95 : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 96{ 97#if FULL_SYSTEM 98 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 99#else 100 thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], 101 p->itb, p->dtb); 102#endif // !FULL_SYSTEM 103 104 thread->setStatus(ThreadContext::Halted); 105 106 tc = thread->getTC(); 107 108#if USE_CHECKER 109 if (p->checker) { 110 BaseCPU *temp_checker = p->checker; 111 checker = dynamic_cast<CheckerCPU *>(temp_checker); 112#if FULL_SYSTEM 113 checker->setSystem(p->system); 114#endif 115 // Manipulate thread context 116 ThreadContext *cpu_tc = tc; 117 tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 118 } else { 119 checker = NULL; 120 } 121#endif 122 123 numInst = 0; 124 startNumInst = 0; 125 numLoad = 0; 126 startNumLoad = 0; 127 lastIcacheStall = 0; 128 lastDcacheStall = 0; 129 130 threadContexts.push_back(tc); 131 132 133 fetchOffset = 0; 134 stayAtPC = false; 135} 136 137BaseSimpleCPU::~BaseSimpleCPU() 138{ 139} 140 141void 142BaseSimpleCPU::deallocateContext(ThreadID thread_num) 143{ 144 // for now, these are equivalent 145 suspendContext(thread_num); 146} 147 148 149void 150BaseSimpleCPU::haltContext(ThreadID thread_num) 151{ 152 // for now, these are equivalent 153 suspendContext(thread_num); 154} 155 156 157void 158BaseSimpleCPU::regStats() 159{ 160 using namespace Stats; 161 162 BaseCPU::regStats(); 163 164 numInsts 165 .name(name() + ".num_insts") 166 .desc("Number of instructions executed") 167 ; 168 169 numIntAluAccesses 170 .name(name() + ".num_int_alu_accesses") 171 .desc("Number of integer alu accesses") 172 ; 173 174 numFpAluAccesses 175 .name(name() + ".num_fp_alu_accesses") 176 .desc("Number of float alu accesses") 177 ; 178 179 numCallsReturns 180 .name(name() + ".num_func_calls") 181 .desc("number of times a function call or return occured") 182 ; 183 184 numCondCtrlInsts 185 .name(name() + ".num_conditional_control_insts") 186 .desc("number of instructions that are conditional controls") 187 ; 188 189 numIntInsts 190 .name(name() + ".num_int_insts") 191 .desc("number of integer instructions") 192 ; 193 194 numFpInsts 195 .name(name() + ".num_fp_insts") 196 .desc("number of float instructions") 197 ; 198 199 numIntRegReads 200 .name(name() + ".num_int_register_reads") 201 .desc("number of times the integer registers were read") 202 ; 203 204 numIntRegWrites 205 .name(name() + ".num_int_register_writes") 206 .desc("number of times the integer registers were written") 207 ; 208 209 numFpRegReads 210 .name(name() + ".num_fp_register_reads") 211 .desc("number of times the floating registers were read") 212 ; 213 214 numFpRegWrites 215 .name(name() + ".num_fp_register_writes") 216 .desc("number of times the floating registers were written") 217 ; 218 219 numMemRefs 220 .name(name()+".num_mem_refs") 221 .desc("number of memory refs") 222 ; 223 224 numStoreInsts 225 .name(name() + ".num_store_insts") 226 .desc("Number of store instructions") 227 ; 228 229 numLoadInsts 230 .name(name() + ".num_load_insts") 231 .desc("Number of load instructions") 232 ; 233 234 notIdleFraction 235 .name(name() + ".not_idle_fraction") 236 .desc("Percentage of non-idle cycles") 237 ; 238 239 idleFraction 240 .name(name() + ".idle_fraction") 241 .desc("Percentage of idle cycles") 242 ; 243 244 numBusyCycles 245 .name(name() + ".num_busy_cycles") 246 .desc("Number of busy cycles") 247 ; 248 249 numIdleCycles 250 .name(name()+".num_idle_cycles") 251 .desc("Number of idle cycles") 252 ; 253 254 icacheStallCycles 255 .name(name() + ".icache_stall_cycles") 256 .desc("ICache total stall cycles") 257 .prereq(icacheStallCycles) 258 ; 259 260 dcacheStallCycles 261 .name(name() + ".dcache_stall_cycles") 262 .desc("DCache total stall cycles") 263 .prereq(dcacheStallCycles) 264 ; 265 266 icacheRetryCycles 267 .name(name() + ".icache_retry_cycles") 268 .desc("ICache total retry cycles") 269 .prereq(icacheRetryCycles) 270 ; 271 272 dcacheRetryCycles 273 .name(name() + ".dcache_retry_cycles") 274 .desc("DCache total retry cycles") 275 .prereq(dcacheRetryCycles) 276 ; 277 278 idleFraction = constant(1.0) - notIdleFraction; 279 numIdleCycles = idleFraction * numCycles; 280 numBusyCycles = (notIdleFraction)*numCycles; 281} 282 283void 284BaseSimpleCPU::resetStats() 285{ 286// startNumInst = numInst; 287 notIdleFraction = (_status != Idle); 288} 289 290void 291BaseSimpleCPU::serialize(ostream &os) 292{ 293 SERIALIZE_ENUM(_status); 294 BaseCPU::serialize(os); 295// SERIALIZE_SCALAR(inst); 296 nameOut(os, csprintf("%s.xc.0", name())); 297 thread->serialize(os); 298} 299 300void 301BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 302{ 303 UNSERIALIZE_ENUM(_status); 304 BaseCPU::unserialize(cp, section); 305// UNSERIALIZE_SCALAR(inst); 306 thread->unserialize(cp, csprintf("%s.xc.0", section)); 307} 308 309void 310change_thread_state(ThreadID tid, int activate, int priority) 311{ 312} 313 314#if FULL_SYSTEM 315Addr 316BaseSimpleCPU::dbg_vtophys(Addr addr) 317{ 318 return vtophys(tc, addr); 319} 320#endif // FULL_SYSTEM 321 322#if FULL_SYSTEM 323void 324BaseSimpleCPU::wakeup() 325{ 326 if (thread->status() != ThreadContext::Suspended) 327 return; 328 329 DPRINTF(Quiesce,"Suspended Processor awoke\n"); 330 thread->activate(); 331} 332#endif // FULL_SYSTEM 333 334void 335BaseSimpleCPU::checkForInterrupts() 336{ 337#if FULL_SYSTEM 338 if (checkInterrupts(tc)) { 339 Fault interrupt = interrupts->getInterrupt(tc); 340 341 if (interrupt != NoFault) { 342 fetchOffset = 0; 343 interrupts->updateIntrInfo(tc); 344 interrupt->invoke(tc); 345 predecoder.reset(); 346 } 347 } 348#endif 349} 350 351 352void 353BaseSimpleCPU::setupFetchRequest(Request *req) 354{ 355 Addr instAddr = thread->instAddr(); 356 357 // set up memory request for instruction fetch 358 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 359 360 Addr fetchPC = (instAddr & PCMask) + fetchOffset; 361 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr); 362} 363 364 365void 366BaseSimpleCPU::preExecute() 367{ 368 // maintain $r0 semantics 369 thread->setIntReg(ZeroReg, 0); 370#if THE_ISA == ALPHA_ISA 371 thread->setFloatReg(ZeroReg, 0.0); 372#endif // ALPHA_ISA 373 374 // check for instruction-count-based events 375 comInstEventQueue[0]->serviceEvents(numInst); 376 system->instEventQueue.serviceEvents(system->totalNumInsts); 377 378 // decode the instruction 379 inst = gtoh(inst); 380 381 TheISA::PCState pcState = thread->pcState(); 382 383 if (isRomMicroPC(pcState.microPC())) { 384 stayAtPC = false; 385 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 386 curMacroStaticInst); 387 } else if (!curMacroStaticInst) { 388 //We're not in the middle of a macro instruction 389 StaticInstPtr instPtr = NULL; 390 391 //Predecode, ie bundle up an ExtMachInst 392 //This should go away once the constructor can be set up properly 393 predecoder.setTC(thread->getTC()); 394 //If more fetch data is needed, pass it in. 395 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 396 //if(predecoder.needMoreBytes()) 397 predecoder.moreBytes(pcState, fetchPC, inst); 398 //else 399 // predecoder.process(); 400 401 //If an instruction is ready, decode it. Otherwise, we'll have to 402 //fetch beyond the MachInst at the current pc. 403 if (predecoder.extMachInstReady()) { 404 stayAtPC = false; 405 ExtMachInst machInst = predecoder.getExtMachInst(pcState); 406 thread->pcState(pcState); 407 instPtr = thread->decoder.decode(machInst, pcState.instAddr()); 408 } else { 409 stayAtPC = true; 410 fetchOffset += sizeof(MachInst); 411 } 412 413 //If we decoded an instruction and it's microcoded, start pulling 414 //out micro ops 415 if (instPtr && instPtr->isMacroop()) { 416 curMacroStaticInst = instPtr; 417 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 418 } else { 419 curStaticInst = instPtr; 420 } 421 } else { 422 //Read the next micro op from the macro op 423 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 424 } 425 426 //If we decoded an instruction this "tick", record information about it. 427 if(curStaticInst) 428 { 429#if TRACING_ON 430 traceData = tracer->getInstRecord(curTick(), tc, 431 curStaticInst, thread->pcState(), curMacroStaticInst); 432 433 DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 434 curStaticInst->getName(), curStaticInst->machInst); 435#endif // TRACING_ON 436 } 437} 438 439void 440BaseSimpleCPU::postExecute() 441{ 442 assert(curStaticInst); 443 444 TheISA::PCState pc = tc->pcState(); 445 Addr instAddr = pc.instAddr(); 446#if FULL_SYSTEM 447 if (thread->profile) { 448 bool usermode = TheISA::inUserMode(tc); 449 thread->profilePC = usermode ? 1 : instAddr; 450 ProfileNode *node = thread->profile->consume(tc, curStaticInst); 451 if (node) 452 thread->profileNode = node; 453 } 454#endif 455 456 if (curStaticInst->isMemRef()) { 457 numMemRefs++; 458 } 459 460 if (curStaticInst->isLoad()) { 461 ++numLoad; 462 comLoadEventQueue[0]->serviceEvents(numLoad); 463 } 464 465 if (CPA::available()) { 466 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 467 } 468 469 /* Power model statistics */ 470 //integer alu accesses 471 if (curStaticInst->isInteger()){ 472 numIntAluAccesses++; 473 numIntInsts++; 474 } 475 476 //float alu accesses 477 if (curStaticInst->isFloating()){ 478 numFpAluAccesses++; 479 numFpInsts++; 480 } 481 482 //number of function calls/returns to get window accesses 483 if (curStaticInst->isCall() || curStaticInst->isReturn()){ 484 numCallsReturns++; 485 } 486 487 //the number of branch predictions that will be made 488 if (curStaticInst->isCondCtrl()){ 489 numCondCtrlInsts++; 490 } 491 492 //result bus acceses 493 if (curStaticInst->isLoad()){ 494 numLoadInsts++; 495 } 496 497 if (curStaticInst->isStore()){ 498 numStoreInsts++; 499 } 500 /* End power model statistics */ 501 502 traceFunctions(instAddr); 503 504 if (traceData) { 505 traceData->dump(); 506 delete traceData; 507 traceData = NULL; 508 } 509} 510 511 512void 513BaseSimpleCPU::advancePC(Fault fault) 514{ 515 //Since we're moving to a new pc, zero out the offset 516 fetchOffset = 0; 517 if (fault != NoFault) { 518 curMacroStaticInst = StaticInst::nullStaticInstPtr; 519 fault->invoke(tc, curStaticInst); 520 predecoder.reset(); 521 } else { 522 if (curStaticInst) { 523 if (curStaticInst->isLastMicroop()) 524 curMacroStaticInst = StaticInst::nullStaticInstPtr; 525 TheISA::PCState pcState = thread->pcState(); 526 TheISA::advancePC(pcState, curStaticInst); 527 thread->pcState(pcState); 528 } 529 } 530} 531 532/*Fault 533BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 534{ 535 // translate to physical address 536 Fault fault = NoFault; 537 int CacheID = Op & 0x3; // Lower 3 bits identify Cache 538 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 539 if(CacheID > 1) 540 { 541 warn("CacheOps not implemented for secondary/tertiary caches\n"); 542 } 543 else 544 { 545 switch(CacheOP) 546 { // Fill Packet Type 547 case 0: warn("Invalidate Cache Op\n"); 548 break; 549 case 1: warn("Index Load Tag Cache Op\n"); 550 break; 551 case 2: warn("Index Store Tag Cache Op\n"); 552 break; 553 case 4: warn("Hit Invalidate Cache Op\n"); 554 break; 555 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 556 break; 557 case 6: warn("Hit Writeback\n"); 558 break; 559 case 7: warn("Fetch & Lock Cache Op\n"); 560 break; 561 default: warn("Unimplemented Cache Op\n"); 562 } 563 } 564 return fault; 565}*/ 566