atomic.cc revision 3806
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 323806Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 342623SN/A#include "cpu/exetrace.hh" 352623SN/A#include "cpu/simple/atomic.hh" 363348Sbinkertn@umich.edu#include "mem/packet.hh" 373348Sbinkertn@umich.edu#include "mem/packet_access.hh" 382623SN/A#include "sim/builder.hh" 392901Ssaidi@eecs.umich.edu#include "sim/system.hh" 402623SN/A 412623SN/Ausing namespace std; 422623SN/Ausing namespace TheISA; 432623SN/A 442623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 452623SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 462623SN/A{ 472623SN/A} 482623SN/A 492623SN/A 502623SN/Avoid 512623SN/AAtomicSimpleCPU::TickEvent::process() 522623SN/A{ 532623SN/A cpu->tick(); 542623SN/A} 552623SN/A 562623SN/Aconst char * 572623SN/AAtomicSimpleCPU::TickEvent::description() 582623SN/A{ 592623SN/A return "AtomicSimpleCPU tick event"; 602623SN/A} 612623SN/A 622856Srdreslin@umich.eduPort * 632856Srdreslin@umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx) 642856Srdreslin@umich.edu{ 652856Srdreslin@umich.edu if (if_name == "dcache_port") 662856Srdreslin@umich.edu return &dcachePort; 672856Srdreslin@umich.edu else if (if_name == "icache_port") 682856Srdreslin@umich.edu return &icachePort; 692856Srdreslin@umich.edu else 702856Srdreslin@umich.edu panic("No Such Port\n"); 712856Srdreslin@umich.edu} 722623SN/A 732623SN/Avoid 742623SN/AAtomicSimpleCPU::init() 752623SN/A{ 762623SN/A BaseCPU::init(); 772623SN/A#if FULL_SYSTEM 782680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 792680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 802623SN/A 813673Srdreslin@umich.edu // initialize the mem pointers 823673Srdreslin@umich.edu tc->init(); 833673Srdreslin@umich.edu 842623SN/A // initialize CPU, including PC 852680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 862623SN/A } 872623SN/A#endif 882623SN/A} 892623SN/A 902623SN/Abool 913349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) 922623SN/A{ 933184Srdreslin@umich.edu panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 942623SN/A return true; 952623SN/A} 962623SN/A 972623SN/ATick 983349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 992623SN/A{ 1003310Srdreslin@umich.edu //Snooping a coherence request, just return 1013649Srdreslin@umich.edu return 0; 1022623SN/A} 1032623SN/A 1042623SN/Avoid 1053349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 1062623SN/A{ 1073184Srdreslin@umich.edu //No internal storage to update, just return 1083184Srdreslin@umich.edu return; 1092623SN/A} 1102623SN/A 1112623SN/Avoid 1122623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 1132623SN/A{ 1143647Srdreslin@umich.edu if (status == RangeChange) { 1153647Srdreslin@umich.edu if (!snoopRangeSent) { 1163647Srdreslin@umich.edu snoopRangeSent = true; 1173647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 1183647Srdreslin@umich.edu } 1192626SN/A return; 1203647Srdreslin@umich.edu } 1212626SN/A 1222623SN/A panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 1232623SN/A} 1242623SN/A 1252657Ssaidi@eecs.umich.eduvoid 1262623SN/AAtomicSimpleCPU::CpuPort::recvRetry() 1272623SN/A{ 1282623SN/A panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 1292623SN/A} 1302623SN/A 1312623SN/A 1322623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p) 1332623SN/A : BaseSimpleCPU(p), tickEvent(this), 1342623SN/A width(p->width), simulate_stalls(p->simulate_stalls), 1352640Sstever@eecs.umich.edu icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 1362623SN/A{ 1372623SN/A _status = Idle; 1382623SN/A 1393647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1403647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1413647Srdreslin@umich.edu 1422663Sstever@eecs.umich.edu ifetch_req = new Request(); 1433170Sstever@eecs.umich.edu ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT 1442641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 1452623SN/A ifetch_pkt->dataStatic(&inst); 1462623SN/A 1472663Sstever@eecs.umich.edu data_read_req = new Request(); 1483170Sstever@eecs.umich.edu data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 1492641Sstever@eecs.umich.edu data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 1502641Sstever@eecs.umich.edu Packet::Broadcast); 1512623SN/A data_read_pkt->dataStatic(&dataReg); 1522623SN/A 1532663Sstever@eecs.umich.edu data_write_req = new Request(); 1543170Sstever@eecs.umich.edu data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 1552641Sstever@eecs.umich.edu data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 1562641Sstever@eecs.umich.edu Packet::Broadcast); 1572623SN/A} 1582623SN/A 1592623SN/A 1602623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1612623SN/A{ 1622623SN/A} 1632623SN/A 1642623SN/Avoid 1652623SN/AAtomicSimpleCPU::serialize(ostream &os) 1662623SN/A{ 1672915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1682915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1693177Shsul@eecs.umich.edu Status _status = status(); 1703177Shsul@eecs.umich.edu SERIALIZE_ENUM(_status); 1713145Shsul@eecs.umich.edu BaseSimpleCPU::serialize(os); 1722623SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1732623SN/A tickEvent.serialize(os); 1742623SN/A} 1752623SN/A 1762623SN/Avoid 1772623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1782623SN/A{ 1792915Sktlim@umich.edu SimObject::State so_state; 1802915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1813177Shsul@eecs.umich.edu UNSERIALIZE_ENUM(_status); 1823145Shsul@eecs.umich.edu BaseSimpleCPU::unserialize(cp, section); 1832915Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1842915Sktlim@umich.edu} 1852915Sktlim@umich.edu 1862915Sktlim@umich.eduvoid 1872915Sktlim@umich.eduAtomicSimpleCPU::resume() 1882915Sktlim@umich.edu{ 1893324Shsul@eecs.umich.edu if (_status != SwitchedOut && _status != Idle) { 1903201Shsul@eecs.umich.edu assert(system->getMemoryMode() == System::Atomic); 1913324Shsul@eecs.umich.edu 1923324Shsul@eecs.umich.edu changeState(SimObject::Running); 1933324Shsul@eecs.umich.edu if (thread->status() == ThreadContext::Active) { 1943431Sgblack@eecs.umich.edu if (!tickEvent.scheduled()) { 1953495Sktlim@umich.edu tickEvent.schedule(nextCycle()); 1963431Sgblack@eecs.umich.edu } 1973324Shsul@eecs.umich.edu } 1982915Sktlim@umich.edu } 1992623SN/A} 2002623SN/A 2012623SN/Avoid 2022798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 2032623SN/A{ 2042798Sktlim@umich.edu assert(status() == Running || status() == Idle); 2052798Sktlim@umich.edu _status = SwitchedOut; 2062623SN/A 2072798Sktlim@umich.edu tickEvent.squash(); 2082623SN/A} 2092623SN/A 2102623SN/A 2112623SN/Avoid 2122623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2132623SN/A{ 2142623SN/A BaseCPU::takeOverFrom(oldCPU); 2152623SN/A 2162623SN/A assert(!tickEvent.scheduled()); 2172623SN/A 2182680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2192623SN/A // running and schedule its tick event. 2202680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2212680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2222680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2232623SN/A _status = Running; 2243495Sktlim@umich.edu tickEvent.schedule(nextCycle()); 2252623SN/A break; 2262623SN/A } 2272623SN/A } 2283512Sktlim@umich.edu if (_status != Running) { 2293512Sktlim@umich.edu _status = Idle; 2303512Sktlim@umich.edu } 2312623SN/A} 2322623SN/A 2332623SN/A 2342623SN/Avoid 2352623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay) 2362623SN/A{ 2372623SN/A assert(thread_num == 0); 2382683Sktlim@umich.edu assert(thread); 2392623SN/A 2402623SN/A assert(_status == Idle); 2412623SN/A assert(!tickEvent.scheduled()); 2422623SN/A 2432623SN/A notIdleFraction++; 2443430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 2453495Sktlim@umich.edu tickEvent.schedule(nextCycle(curTick + cycles(delay))); 2462623SN/A _status = Running; 2472623SN/A} 2482623SN/A 2492623SN/A 2502623SN/Avoid 2512623SN/AAtomicSimpleCPU::suspendContext(int thread_num) 2522623SN/A{ 2532623SN/A assert(thread_num == 0); 2542683Sktlim@umich.edu assert(thread); 2552623SN/A 2562623SN/A assert(_status == Running); 2572626SN/A 2582626SN/A // tick event may not be scheduled if this gets called from inside 2592626SN/A // an instruction's execution, e.g. "quiesce" 2602626SN/A if (tickEvent.scheduled()) 2612626SN/A tickEvent.deschedule(); 2622623SN/A 2632623SN/A notIdleFraction--; 2642623SN/A _status = Idle; 2652623SN/A} 2662623SN/A 2672623SN/A 2682623SN/Atemplate <class T> 2692623SN/AFault 2702623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 2712623SN/A{ 2723169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 2733169Sstever@eecs.umich.edu Request *req = data_read_req; 2743349Sbinkertn@umich.edu PacketPtr pkt = data_read_pkt; 2753169Sstever@eecs.umich.edu 2763169Sstever@eecs.umich.edu req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 2772623SN/A 2782623SN/A if (traceData) { 2792623SN/A traceData->setAddr(addr); 2802623SN/A } 2812623SN/A 2822623SN/A // translate to physical address 2833169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2842623SN/A 2852623SN/A // Now do the access. 2862623SN/A if (fault == NoFault) { 2873169Sstever@eecs.umich.edu pkt->reinitFromRequest(); 2882623SN/A 2893806Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) 2903806Ssaidi@eecs.umich.edu dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt); 2913806Ssaidi@eecs.umich.edu else 2923806Ssaidi@eecs.umich.edu dcache_latency = dcachePort.sendAtomic(pkt); 2932623SN/A dcache_access = true; 2942623SN/A 2953169Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 2963169Sstever@eecs.umich.edu data = pkt->get<T>(); 2973170Sstever@eecs.umich.edu 2983170Sstever@eecs.umich.edu if (req->isLocked()) { 2993170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3003170Sstever@eecs.umich.edu } 3012623SN/A } 3022623SN/A 3032623SN/A // This will need a new way to tell if it has a dcache attached. 3043172Sstever@eecs.umich.edu if (req->isUncacheable()) 3052623SN/A recordEvent("Uncached Read"); 3062623SN/A 3072623SN/A return fault; 3082623SN/A} 3092623SN/A 3102623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3112623SN/A 3122623SN/Atemplate 3132623SN/AFault 3142623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3152623SN/A 3162623SN/Atemplate 3172623SN/AFault 3182623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3192623SN/A 3202623SN/Atemplate 3212623SN/AFault 3222623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3232623SN/A 3242623SN/Atemplate 3252623SN/AFault 3262623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3272623SN/A 3282623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3292623SN/A 3302623SN/Atemplate<> 3312623SN/AFault 3322623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 3332623SN/A{ 3342623SN/A return read(addr, *(uint64_t*)&data, flags); 3352623SN/A} 3362623SN/A 3372623SN/Atemplate<> 3382623SN/AFault 3392623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 3402623SN/A{ 3412623SN/A return read(addr, *(uint32_t*)&data, flags); 3422623SN/A} 3432623SN/A 3442623SN/A 3452623SN/Atemplate<> 3462623SN/AFault 3472623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3482623SN/A{ 3492623SN/A return read(addr, (uint32_t&)data, flags); 3502623SN/A} 3512623SN/A 3522623SN/A 3532623SN/Atemplate <class T> 3542623SN/AFault 3552623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3562623SN/A{ 3573169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 3583169Sstever@eecs.umich.edu Request *req = data_write_req; 3593349Sbinkertn@umich.edu PacketPtr pkt = data_write_pkt; 3603169Sstever@eecs.umich.edu 3613169Sstever@eecs.umich.edu req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 3622623SN/A 3632623SN/A if (traceData) { 3642623SN/A traceData->setAddr(addr); 3652623SN/A } 3662623SN/A 3672623SN/A // translate to physical address 3683169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3692623SN/A 3702623SN/A // Now do the access. 3712623SN/A if (fault == NoFault) { 3723170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3732623SN/A 3743170Sstever@eecs.umich.edu if (req->isLocked()) { 3753170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3763170Sstever@eecs.umich.edu } 3772623SN/A 3783170Sstever@eecs.umich.edu if (do_access) { 3793170Sstever@eecs.umich.edu pkt->reinitFromRequest(); 3803170Sstever@eecs.umich.edu pkt->dataStatic(&data); 3812631SN/A 3823806Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 3833806Ssaidi@eecs.umich.edu dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt); 3843806Ssaidi@eecs.umich.edu } else { 3853806Ssaidi@eecs.umich.edu data = htog(data); 3863806Ssaidi@eecs.umich.edu dcache_latency = dcachePort.sendAtomic(pkt); 3873806Ssaidi@eecs.umich.edu } 3883170Sstever@eecs.umich.edu dcache_access = true; 3893170Sstever@eecs.umich.edu 3903170Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 3913170Sstever@eecs.umich.edu } 3923170Sstever@eecs.umich.edu 3933170Sstever@eecs.umich.edu if (req->isLocked()) { 3943170Sstever@eecs.umich.edu uint64_t scResult = req->getScResult(); 3953170Sstever@eecs.umich.edu if (scResult != 0) { 3963170Sstever@eecs.umich.edu // clear failure counter 3973170Sstever@eecs.umich.edu thread->setStCondFailures(0); 3983170Sstever@eecs.umich.edu } 3993170Sstever@eecs.umich.edu if (res) { 4003170Sstever@eecs.umich.edu *res = req->getScResult(); 4013170Sstever@eecs.umich.edu } 4022631SN/A } 4032623SN/A } 4042623SN/A 4052623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 4063172Sstever@eecs.umich.edu if (req->isUncacheable()) 4072623SN/A recordEvent("Uncached Write"); 4082623SN/A 4092623SN/A // If the write needs to have a fault on the access, consider calling 4102623SN/A // changeStatus() and changing it to "bad addr write" or something. 4112623SN/A return fault; 4122623SN/A} 4132623SN/A 4142623SN/A 4152623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4162623SN/Atemplate 4172623SN/AFault 4182623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr, 4192623SN/A unsigned flags, uint64_t *res); 4202623SN/A 4212623SN/Atemplate 4222623SN/AFault 4232623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr, 4242623SN/A unsigned flags, uint64_t *res); 4252623SN/A 4262623SN/Atemplate 4272623SN/AFault 4282623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr, 4292623SN/A unsigned flags, uint64_t *res); 4302623SN/A 4312623SN/Atemplate 4322623SN/AFault 4332623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr, 4342623SN/A unsigned flags, uint64_t *res); 4352623SN/A 4362623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4372623SN/A 4382623SN/Atemplate<> 4392623SN/AFault 4402623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4412623SN/A{ 4422623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4432623SN/A} 4442623SN/A 4452623SN/Atemplate<> 4462623SN/AFault 4472623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4482623SN/A{ 4492623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4502623SN/A} 4512623SN/A 4522623SN/A 4532623SN/Atemplate<> 4542623SN/AFault 4552623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4562623SN/A{ 4572623SN/A return write((uint32_t)data, addr, flags, res); 4582623SN/A} 4592623SN/A 4602623SN/A 4612623SN/Avoid 4622623SN/AAtomicSimpleCPU::tick() 4632623SN/A{ 4642623SN/A Tick latency = cycles(1); // instruction takes one cycle by default 4652623SN/A 4662623SN/A for (int i = 0; i < width; ++i) { 4672623SN/A numCycles++; 4682623SN/A 4693387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4703387Sgblack@eecs.umich.edu checkForInterrupts(); 4712626SN/A 4722662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4732623SN/A 4742623SN/A if (fault == NoFault) { 4752662Sstever@eecs.umich.edu ifetch_pkt->reinitFromRequest(); 4762662Sstever@eecs.umich.edu 4772662Sstever@eecs.umich.edu Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); 4782623SN/A // ifetch_req is initialized to read the instruction directly 4792623SN/A // into the CPU object's inst field. 4802623SN/A 4812623SN/A dcache_access = false; // assume no dcache access 4822623SN/A preExecute(); 4832623SN/A fault = curStaticInst->execute(this, traceData); 4842623SN/A postExecute(); 4852623SN/A 4862623SN/A if (simulate_stalls) { 4872662Sstever@eecs.umich.edu Tick icache_stall = icache_latency - cycles(1); 4882623SN/A Tick dcache_stall = 4892662Sstever@eecs.umich.edu dcache_access ? dcache_latency - cycles(1) : 0; 4902803Ssaidi@eecs.umich.edu Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); 4912803Ssaidi@eecs.umich.edu if (cycles(stall_cycles) < (icache_stall + dcache_stall)) 4922803Ssaidi@eecs.umich.edu latency += cycles(stall_cycles+1); 4932803Ssaidi@eecs.umich.edu else 4942803Ssaidi@eecs.umich.edu latency += cycles(stall_cycles); 4952623SN/A } 4962623SN/A 4972623SN/A } 4982623SN/A 4992623SN/A advancePC(fault); 5002623SN/A } 5012623SN/A 5022626SN/A if (_status != Idle) 5032626SN/A tickEvent.schedule(curTick + latency); 5042623SN/A} 5052623SN/A 5062623SN/A 5072623SN/A//////////////////////////////////////////////////////////////////////// 5082623SN/A// 5092623SN/A// AtomicSimpleCPU Simulation Object 5102623SN/A// 5112623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 5122623SN/A 5132623SN/A Param<Counter> max_insts_any_thread; 5142623SN/A Param<Counter> max_insts_all_threads; 5152623SN/A Param<Counter> max_loads_any_thread; 5162623SN/A Param<Counter> max_loads_all_threads; 5173119Sktlim@umich.edu Param<Tick> progress_interval; 5182901Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 5193170Sstever@eecs.umich.edu Param<int> cpu_id; 5202623SN/A 5212623SN/A#if FULL_SYSTEM 5223453Sgblack@eecs.umich.edu SimObjectParam<TheISA::ITB *> itb; 5233453Sgblack@eecs.umich.edu SimObjectParam<TheISA::DTB *> dtb; 5242623SN/A Param<Tick> profile; 5253617Sbinkertn@umich.edu 5263617Sbinkertn@umich.edu Param<bool> do_quiesce; 5273617Sbinkertn@umich.edu Param<bool> do_checkpoint_insts; 5283617Sbinkertn@umich.edu Param<bool> do_statistics_insts; 5292623SN/A#else 5302623SN/A SimObjectParam<Process *> workload; 5312623SN/A#endif // FULL_SYSTEM 5322623SN/A 5332623SN/A Param<int> clock; 5343661Srdreslin@umich.edu Param<int> phase; 5352623SN/A 5362623SN/A Param<bool> defer_registration; 5372623SN/A Param<int> width; 5382623SN/A Param<bool> function_trace; 5392623SN/A Param<Tick> function_trace_start; 5402623SN/A Param<bool> simulate_stalls; 5412623SN/A 5422623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 5432623SN/A 5442623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 5452623SN/A 5462623SN/A INIT_PARAM(max_insts_any_thread, 5472623SN/A "terminate when any thread reaches this inst count"), 5482623SN/A INIT_PARAM(max_insts_all_threads, 5492623SN/A "terminate when all threads have reached this inst count"), 5502623SN/A INIT_PARAM(max_loads_any_thread, 5512623SN/A "terminate when any thread reaches this load count"), 5522623SN/A INIT_PARAM(max_loads_all_threads, 5532623SN/A "terminate when all threads have reached this load count"), 5543119Sktlim@umich.edu INIT_PARAM(progress_interval, "Progress interval"), 5552901Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object"), 5563170Sstever@eecs.umich.edu INIT_PARAM(cpu_id, "processor ID"), 5572623SN/A 5582623SN/A#if FULL_SYSTEM 5592623SN/A INIT_PARAM(itb, "Instruction TLB"), 5602623SN/A INIT_PARAM(dtb, "Data TLB"), 5612623SN/A INIT_PARAM(profile, ""), 5623617Sbinkertn@umich.edu INIT_PARAM(do_quiesce, ""), 5633617Sbinkertn@umich.edu INIT_PARAM(do_checkpoint_insts, ""), 5643617Sbinkertn@umich.edu INIT_PARAM(do_statistics_insts, ""), 5652623SN/A#else 5662623SN/A INIT_PARAM(workload, "processes to run"), 5672623SN/A#endif // FULL_SYSTEM 5682623SN/A 5692623SN/A INIT_PARAM(clock, "clock speed"), 5703661Srdreslin@umich.edu INIT_PARAM_DFLT(phase, "clock phase", 0), 5712623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 5722623SN/A INIT_PARAM(width, "cpu width"), 5732623SN/A INIT_PARAM(function_trace, "Enable function trace"), 5742623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 5752623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 5762623SN/A 5772623SN/AEND_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 5782623SN/A 5792623SN/A 5802623SN/ACREATE_SIM_OBJECT(AtomicSimpleCPU) 5812623SN/A{ 5822623SN/A AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 5832623SN/A params->name = getInstanceName(); 5842623SN/A params->numberOfThreads = 1; 5852623SN/A params->max_insts_any_thread = max_insts_any_thread; 5862623SN/A params->max_insts_all_threads = max_insts_all_threads; 5872623SN/A params->max_loads_any_thread = max_loads_any_thread; 5882623SN/A params->max_loads_all_threads = max_loads_all_threads; 5893119Sktlim@umich.edu params->progress_interval = progress_interval; 5902623SN/A params->deferRegistration = defer_registration; 5913661Srdreslin@umich.edu params->phase = phase; 5922623SN/A params->clock = clock; 5932623SN/A params->functionTrace = function_trace; 5942623SN/A params->functionTraceStart = function_trace_start; 5952623SN/A params->width = width; 5962623SN/A params->simulate_stalls = simulate_stalls; 5972901Ssaidi@eecs.umich.edu params->system = system; 5983170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 5992623SN/A 6002623SN/A#if FULL_SYSTEM 6012623SN/A params->itb = itb; 6022623SN/A params->dtb = dtb; 6032623SN/A params->profile = profile; 6043617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 6053617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 6063617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 6072623SN/A#else 6082623SN/A params->process = workload; 6092623SN/A#endif 6102623SN/A 6112623SN/A AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 6122623SN/A return cpu; 6132623SN/A} 6142623SN/A 6152623SN/AREGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 6162623SN/A 617