atomic.cc revision 3806 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "cpu/exetrace.hh"
35#include "cpu/simple/atomic.hh"
36#include "mem/packet.hh"
37#include "mem/packet_access.hh"
38#include "sim/builder.hh"
39#include "sim/system.hh"
40
41using namespace std;
42using namespace TheISA;
43
44AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
45    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
46{
47}
48
49
50void
51AtomicSimpleCPU::TickEvent::process()
52{
53    cpu->tick();
54}
55
56const char *
57AtomicSimpleCPU::TickEvent::description()
58{
59    return "AtomicSimpleCPU tick event";
60}
61
62Port *
63AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
64{
65    if (if_name == "dcache_port")
66        return &dcachePort;
67    else if (if_name == "icache_port")
68        return &icachePort;
69    else
70        panic("No Such Port\n");
71}
72
73void
74AtomicSimpleCPU::init()
75{
76    BaseCPU::init();
77#if FULL_SYSTEM
78    for (int i = 0; i < threadContexts.size(); ++i) {
79        ThreadContext *tc = threadContexts[i];
80
81        // initialize the mem pointers
82        tc->init();
83
84        // initialize CPU, including PC
85        TheISA::initCPU(tc, tc->readCpuId());
86    }
87#endif
88}
89
90bool
91AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
92{
93    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
94    return true;
95}
96
97Tick
98AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
99{
100    //Snooping a coherence request, just return
101    return 0;
102}
103
104void
105AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
106{
107    //No internal storage to update, just return
108    return;
109}
110
111void
112AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
113{
114    if (status == RangeChange) {
115        if (!snoopRangeSent) {
116            snoopRangeSent = true;
117            sendStatusChange(Port::RangeChange);
118        }
119        return;
120    }
121
122    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
123}
124
125void
126AtomicSimpleCPU::CpuPort::recvRetry()
127{
128    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
129}
130
131
132AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
133    : BaseSimpleCPU(p), tickEvent(this),
134      width(p->width), simulate_stalls(p->simulate_stalls),
135      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
136{
137    _status = Idle;
138
139    icachePort.snoopRangeSent = false;
140    dcachePort.snoopRangeSent = false;
141
142    ifetch_req = new Request();
143    ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
144    ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
145    ifetch_pkt->dataStatic(&inst);
146
147    data_read_req = new Request();
148    data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
149    data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
150                               Packet::Broadcast);
151    data_read_pkt->dataStatic(&dataReg);
152
153    data_write_req = new Request();
154    data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
155    data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
156                                Packet::Broadcast);
157}
158
159
160AtomicSimpleCPU::~AtomicSimpleCPU()
161{
162}
163
164void
165AtomicSimpleCPU::serialize(ostream &os)
166{
167    SimObject::State so_state = SimObject::getState();
168    SERIALIZE_ENUM(so_state);
169    Status _status = status();
170    SERIALIZE_ENUM(_status);
171    BaseSimpleCPU::serialize(os);
172    nameOut(os, csprintf("%s.tickEvent", name()));
173    tickEvent.serialize(os);
174}
175
176void
177AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
178{
179    SimObject::State so_state;
180    UNSERIALIZE_ENUM(so_state);
181    UNSERIALIZE_ENUM(_status);
182    BaseSimpleCPU::unserialize(cp, section);
183    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
184}
185
186void
187AtomicSimpleCPU::resume()
188{
189    if (_status != SwitchedOut && _status != Idle) {
190        assert(system->getMemoryMode() == System::Atomic);
191
192        changeState(SimObject::Running);
193        if (thread->status() == ThreadContext::Active) {
194            if (!tickEvent.scheduled()) {
195                tickEvent.schedule(nextCycle());
196            }
197        }
198    }
199}
200
201void
202AtomicSimpleCPU::switchOut()
203{
204    assert(status() == Running || status() == Idle);
205    _status = SwitchedOut;
206
207    tickEvent.squash();
208}
209
210
211void
212AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
213{
214    BaseCPU::takeOverFrom(oldCPU);
215
216    assert(!tickEvent.scheduled());
217
218    // if any of this CPU's ThreadContexts are active, mark the CPU as
219    // running and schedule its tick event.
220    for (int i = 0; i < threadContexts.size(); ++i) {
221        ThreadContext *tc = threadContexts[i];
222        if (tc->status() == ThreadContext::Active && _status != Running) {
223            _status = Running;
224            tickEvent.schedule(nextCycle());
225            break;
226        }
227    }
228    if (_status != Running) {
229        _status = Idle;
230    }
231}
232
233
234void
235AtomicSimpleCPU::activateContext(int thread_num, int delay)
236{
237    assert(thread_num == 0);
238    assert(thread);
239
240    assert(_status == Idle);
241    assert(!tickEvent.scheduled());
242
243    notIdleFraction++;
244    //Make sure ticks are still on multiples of cycles
245    tickEvent.schedule(nextCycle(curTick + cycles(delay)));
246    _status = Running;
247}
248
249
250void
251AtomicSimpleCPU::suspendContext(int thread_num)
252{
253    assert(thread_num == 0);
254    assert(thread);
255
256    assert(_status == Running);
257
258    // tick event may not be scheduled if this gets called from inside
259    // an instruction's execution, e.g. "quiesce"
260    if (tickEvent.scheduled())
261        tickEvent.deschedule();
262
263    notIdleFraction--;
264    _status = Idle;
265}
266
267
268template <class T>
269Fault
270AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
271{
272    // use the CPU's statically allocated read request and packet objects
273    Request *req = data_read_req;
274    PacketPtr pkt = data_read_pkt;
275
276    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
277
278    if (traceData) {
279        traceData->setAddr(addr);
280    }
281
282    // translate to physical address
283    Fault fault = thread->translateDataReadReq(req);
284
285    // Now do the access.
286    if (fault == NoFault) {
287        pkt->reinitFromRequest();
288
289        if (req->isMmapedIpr())
290            dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
291        else
292            dcache_latency = dcachePort.sendAtomic(pkt);
293        dcache_access = true;
294
295        assert(pkt->result == Packet::Success);
296        data = pkt->get<T>();
297
298        if (req->isLocked()) {
299            TheISA::handleLockedRead(thread, req);
300        }
301    }
302
303    // This will need a new way to tell if it has a dcache attached.
304    if (req->isUncacheable())
305        recordEvent("Uncached Read");
306
307    return fault;
308}
309
310#ifndef DOXYGEN_SHOULD_SKIP_THIS
311
312template
313Fault
314AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
315
316template
317Fault
318AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
319
320template
321Fault
322AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
323
324template
325Fault
326AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
327
328#endif //DOXYGEN_SHOULD_SKIP_THIS
329
330template<>
331Fault
332AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
333{
334    return read(addr, *(uint64_t*)&data, flags);
335}
336
337template<>
338Fault
339AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
340{
341    return read(addr, *(uint32_t*)&data, flags);
342}
343
344
345template<>
346Fault
347AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
348{
349    return read(addr, (uint32_t&)data, flags);
350}
351
352
353template <class T>
354Fault
355AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
356{
357    // use the CPU's statically allocated write request and packet objects
358    Request *req = data_write_req;
359    PacketPtr pkt = data_write_pkt;
360
361    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
362
363    if (traceData) {
364        traceData->setAddr(addr);
365    }
366
367    // translate to physical address
368    Fault fault = thread->translateDataWriteReq(req);
369
370    // Now do the access.
371    if (fault == NoFault) {
372        bool do_access = true;  // flag to suppress cache access
373
374        if (req->isLocked()) {
375            do_access = TheISA::handleLockedWrite(thread, req);
376        }
377
378        if (do_access) {
379            pkt->reinitFromRequest();
380            pkt->dataStatic(&data);
381
382            if (req->isMmapedIpr()) {
383                dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
384            } else {
385                data = htog(data);
386                dcache_latency = dcachePort.sendAtomic(pkt);
387            }
388            dcache_access = true;
389
390            assert(pkt->result == Packet::Success);
391        }
392
393        if (req->isLocked()) {
394            uint64_t scResult = req->getScResult();
395            if (scResult != 0) {
396                // clear failure counter
397                thread->setStCondFailures(0);
398            }
399            if (res) {
400                *res = req->getScResult();
401            }
402        }
403    }
404
405    // This will need a new way to tell if it's hooked up to a cache or not.
406    if (req->isUncacheable())
407        recordEvent("Uncached Write");
408
409    // If the write needs to have a fault on the access, consider calling
410    // changeStatus() and changing it to "bad addr write" or something.
411    return fault;
412}
413
414
415#ifndef DOXYGEN_SHOULD_SKIP_THIS
416template
417Fault
418AtomicSimpleCPU::write(uint64_t data, Addr addr,
419                       unsigned flags, uint64_t *res);
420
421template
422Fault
423AtomicSimpleCPU::write(uint32_t data, Addr addr,
424                       unsigned flags, uint64_t *res);
425
426template
427Fault
428AtomicSimpleCPU::write(uint16_t data, Addr addr,
429                       unsigned flags, uint64_t *res);
430
431template
432Fault
433AtomicSimpleCPU::write(uint8_t data, Addr addr,
434                       unsigned flags, uint64_t *res);
435
436#endif //DOXYGEN_SHOULD_SKIP_THIS
437
438template<>
439Fault
440AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
441{
442    return write(*(uint64_t*)&data, addr, flags, res);
443}
444
445template<>
446Fault
447AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
448{
449    return write(*(uint32_t*)&data, addr, flags, res);
450}
451
452
453template<>
454Fault
455AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
456{
457    return write((uint32_t)data, addr, flags, res);
458}
459
460
461void
462AtomicSimpleCPU::tick()
463{
464    Tick latency = cycles(1); // instruction takes one cycle by default
465
466    for (int i = 0; i < width; ++i) {
467        numCycles++;
468
469        if (!curStaticInst || !curStaticInst->isDelayedCommit())
470            checkForInterrupts();
471
472        Fault fault = setupFetchRequest(ifetch_req);
473
474        if (fault == NoFault) {
475            ifetch_pkt->reinitFromRequest();
476
477            Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
478            // ifetch_req is initialized to read the instruction directly
479            // into the CPU object's inst field.
480
481            dcache_access = false; // assume no dcache access
482            preExecute();
483            fault = curStaticInst->execute(this, traceData);
484            postExecute();
485
486            if (simulate_stalls) {
487                Tick icache_stall = icache_latency - cycles(1);
488                Tick dcache_stall =
489                    dcache_access ? dcache_latency - cycles(1) : 0;
490                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
491                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
492                    latency += cycles(stall_cycles+1);
493                else
494                    latency += cycles(stall_cycles);
495            }
496
497        }
498
499        advancePC(fault);
500    }
501
502    if (_status != Idle)
503        tickEvent.schedule(curTick + latency);
504}
505
506
507////////////////////////////////////////////////////////////////////////
508//
509//  AtomicSimpleCPU Simulation Object
510//
511BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
512
513    Param<Counter> max_insts_any_thread;
514    Param<Counter> max_insts_all_threads;
515    Param<Counter> max_loads_any_thread;
516    Param<Counter> max_loads_all_threads;
517    Param<Tick> progress_interval;
518    SimObjectParam<System *> system;
519    Param<int> cpu_id;
520
521#if FULL_SYSTEM
522    SimObjectParam<TheISA::ITB *> itb;
523    SimObjectParam<TheISA::DTB *> dtb;
524    Param<Tick> profile;
525
526    Param<bool> do_quiesce;
527    Param<bool> do_checkpoint_insts;
528    Param<bool> do_statistics_insts;
529#else
530    SimObjectParam<Process *> workload;
531#endif // FULL_SYSTEM
532
533    Param<int> clock;
534    Param<int> phase;
535
536    Param<bool> defer_registration;
537    Param<int> width;
538    Param<bool> function_trace;
539    Param<Tick> function_trace_start;
540    Param<bool> simulate_stalls;
541
542END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
543
544BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
545
546    INIT_PARAM(max_insts_any_thread,
547               "terminate when any thread reaches this inst count"),
548    INIT_PARAM(max_insts_all_threads,
549               "terminate when all threads have reached this inst count"),
550    INIT_PARAM(max_loads_any_thread,
551               "terminate when any thread reaches this load count"),
552    INIT_PARAM(max_loads_all_threads,
553               "terminate when all threads have reached this load count"),
554    INIT_PARAM(progress_interval, "Progress interval"),
555    INIT_PARAM(system, "system object"),
556    INIT_PARAM(cpu_id, "processor ID"),
557
558#if FULL_SYSTEM
559    INIT_PARAM(itb, "Instruction TLB"),
560    INIT_PARAM(dtb, "Data TLB"),
561    INIT_PARAM(profile, ""),
562    INIT_PARAM(do_quiesce, ""),
563    INIT_PARAM(do_checkpoint_insts, ""),
564    INIT_PARAM(do_statistics_insts, ""),
565#else
566    INIT_PARAM(workload, "processes to run"),
567#endif // FULL_SYSTEM
568
569    INIT_PARAM(clock, "clock speed"),
570    INIT_PARAM_DFLT(phase, "clock phase", 0),
571    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
572    INIT_PARAM(width, "cpu width"),
573    INIT_PARAM(function_trace, "Enable function trace"),
574    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
575    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
576
577END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
578
579
580CREATE_SIM_OBJECT(AtomicSimpleCPU)
581{
582    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
583    params->name = getInstanceName();
584    params->numberOfThreads = 1;
585    params->max_insts_any_thread = max_insts_any_thread;
586    params->max_insts_all_threads = max_insts_all_threads;
587    params->max_loads_any_thread = max_loads_any_thread;
588    params->max_loads_all_threads = max_loads_all_threads;
589    params->progress_interval = progress_interval;
590    params->deferRegistration = defer_registration;
591    params->phase = phase;
592    params->clock = clock;
593    params->functionTrace = function_trace;
594    params->functionTraceStart = function_trace_start;
595    params->width = width;
596    params->simulate_stalls = simulate_stalls;
597    params->system = system;
598    params->cpu_id = cpu_id;
599
600#if FULL_SYSTEM
601    params->itb = itb;
602    params->dtb = dtb;
603    params->profile = profile;
604    params->do_quiesce = do_quiesce;
605    params->do_checkpoint_insts = do_checkpoint_insts;
606    params->do_statistics_insts = do_statistics_insts;
607#else
608    params->process = workload;
609#endif
610
611    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
612    return cpu;
613}
614
615REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
616
617