thread_context_impl.hh revision 7720
12817Sksewell@umich.edu/* 22817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 32817Sksewell@umich.edu * All rights reserved. 42817Sksewell@umich.edu * 52817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142817Sksewell@umich.edu * this software without specific prior written permission. 152817Sksewell@umich.edu * 162817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * Authors: Kevin Lim 292817Sksewell@umich.edu * Korey Sewell 302817Sksewell@umich.edu */ 312817Sksewell@umich.edu 326329Sgblack@eecs.umich.edu#include "arch/registers.hh" 336658Snate@binkert.org#include "config/the_isa.hh" 342817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 352834Sksewell@umich.edu#include "cpu/quiesce_event.hh" 362817Sksewell@umich.edu 372817Sksewell@umich.edu#if FULL_SYSTEM 382817Sksewell@umich.edutemplate <class Impl> 392817Sksewell@umich.eduVirtualPort * 405499Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::getVirtPort() 412817Sksewell@umich.edu{ 425499Ssaidi@eecs.umich.edu return thread->getVirtPort(); 432817Sksewell@umich.edu} 442817Sksewell@umich.edu 452817Sksewell@umich.edutemplate <class Impl> 462817Sksewell@umich.eduvoid 472817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 482817Sksewell@umich.edu{ 493126Sktlim@umich.edu thread->dumpFuncProfile(); 502817Sksewell@umich.edu} 512817Sksewell@umich.edu#endif 522817Sksewell@umich.edu 532817Sksewell@umich.edutemplate <class Impl> 542817Sksewell@umich.eduvoid 552817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 562817Sksewell@umich.edu{ 572817Sksewell@umich.edu // some things should already be set up 587467Stjones1@inf.ed.ac.uk#if FULL_SYSTEM 592817Sksewell@umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 607467Stjones1@inf.ed.ac.uk#else 612817Sksewell@umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 622817Sksewell@umich.edu#endif 632817Sksewell@umich.edu 642817Sksewell@umich.edu // copy over functional state 652817Sksewell@umich.edu setStatus(old_context->status()); 662817Sksewell@umich.edu copyArchRegs(old_context); 675714Shsul@eecs.umich.edu setContextId(old_context->contextId()); 685715Shsul@eecs.umich.edu setThreadId(old_context->threadId()); 692817Sksewell@umich.edu 702817Sksewell@umich.edu#if !FULL_SYSTEM 712817Sksewell@umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 722817Sksewell@umich.edu#else 732817Sksewell@umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 742817Sksewell@umich.edu if (other_quiesce) { 752817Sksewell@umich.edu // Point the quiesce event's TC at this TC so that it wakes up 762817Sksewell@umich.edu // the proper CPU. 772817Sksewell@umich.edu other_quiesce->tc = this; 782817Sksewell@umich.edu } 792817Sksewell@umich.edu if (thread->quiesceEvent) { 802817Sksewell@umich.edu thread->quiesceEvent->tc = this; 812817Sksewell@umich.edu } 822817Sksewell@umich.edu 832817Sksewell@umich.edu // Transfer kernel stats from one CPU to the other. 842817Sksewell@umich.edu thread->kernelStats = old_context->getKernelStats(); 852817Sksewell@umich.edu// storeCondFailures = 0; 862817Sksewell@umich.edu cpu->lockFlag = false; 872817Sksewell@umich.edu#endif 882817Sksewell@umich.edu 896029Ssteve.reinhardt@amd.com old_context->setStatus(ThreadContext::Halted); 902817Sksewell@umich.edu 912817Sksewell@umich.edu thread->inSyscall = false; 922817Sksewell@umich.edu thread->trapPending = false; 932817Sksewell@umich.edu} 942817Sksewell@umich.edu 952817Sksewell@umich.edutemplate <class Impl> 962817Sksewell@umich.eduvoid 972817Sksewell@umich.eduO3ThreadContext<Impl>::activate(int delay) 982817Sksewell@umich.edu{ 992875Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 1005715Shsul@eecs.umich.edu threadId()); 1012817Sksewell@umich.edu 1022817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 1032817Sksewell@umich.edu return; 1042817Sksewell@umich.edu 1052817Sksewell@umich.edu#if FULL_SYSTEM 1062817Sksewell@umich.edu thread->lastActivate = curTick; 1072817Sksewell@umich.edu#endif 1082817Sksewell@umich.edu 1092817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 1102817Sksewell@umich.edu 1112817Sksewell@umich.edu // status() == Suspended 1125715Shsul@eecs.umich.edu cpu->activateContext(thread->threadId(), delay); 1132817Sksewell@umich.edu} 1142817Sksewell@umich.edu 1152817Sksewell@umich.edutemplate <class Impl> 1162817Sksewell@umich.eduvoid 1175250Sksewell@umich.eduO3ThreadContext<Impl>::suspend(int delay) 1182817Sksewell@umich.edu{ 1192875Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1205715Shsul@eecs.umich.edu threadId()); 1212817Sksewell@umich.edu 1222817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1232817Sksewell@umich.edu return; 1242817Sksewell@umich.edu 1252817Sksewell@umich.edu#if FULL_SYSTEM 1262817Sksewell@umich.edu thread->lastActivate = curTick; 1272817Sksewell@umich.edu thread->lastSuspend = curTick; 1282817Sksewell@umich.edu#endif 1292817Sksewell@umich.edu/* 1302817Sksewell@umich.edu#if FULL_SYSTEM 1312817Sksewell@umich.edu // Don't change the status from active if there are pending interrupts 1325704Snate@binkert.org if (cpu->checkInterrupts()) { 1332817Sksewell@umich.edu assert(status() == ThreadContext::Active); 1342817Sksewell@umich.edu return; 1352817Sksewell@umich.edu } 1362817Sksewell@umich.edu#endif 1372817Sksewell@umich.edu*/ 1382817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1395715Shsul@eecs.umich.edu cpu->suspendContext(thread->threadId()); 1402817Sksewell@umich.edu} 1412817Sksewell@umich.edu 1422817Sksewell@umich.edutemplate <class Impl> 1432817Sksewell@umich.eduvoid 1445250Sksewell@umich.eduO3ThreadContext<Impl>::halt(int delay) 1452817Sksewell@umich.edu{ 1462875Sksewell@umich.edu DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 1475715Shsul@eecs.umich.edu threadId()); 1482817Sksewell@umich.edu 1492817Sksewell@umich.edu if (thread->status() == ThreadContext::Halted) 1502817Sksewell@umich.edu return; 1512817Sksewell@umich.edu 1522817Sksewell@umich.edu thread->setStatus(ThreadContext::Halted); 1535715Shsul@eecs.umich.edu cpu->haltContext(thread->threadId()); 1542817Sksewell@umich.edu} 1552817Sksewell@umich.edu 1562817Sksewell@umich.edutemplate <class Impl> 1572817Sksewell@umich.eduvoid 1582817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1592817Sksewell@umich.edu{ 1602817Sksewell@umich.edu#if FULL_SYSTEM 1613548Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1622817Sksewell@umich.edu thread->kernelStats->regStats(name + ".kern"); 1632817Sksewell@umich.edu#endif 1642817Sksewell@umich.edu} 1652817Sksewell@umich.edu 1662817Sksewell@umich.edutemplate <class Impl> 1672817Sksewell@umich.eduvoid 1682817Sksewell@umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 1692817Sksewell@umich.edu{ 1702817Sksewell@umich.edu#if FULL_SYSTEM 1712817Sksewell@umich.edu if (thread->kernelStats) 1722817Sksewell@umich.edu thread->kernelStats->serialize(os); 1732817Sksewell@umich.edu#endif 1742817Sksewell@umich.edu 1752817Sksewell@umich.edu} 1762817Sksewell@umich.edu 1772817Sksewell@umich.edutemplate <class Impl> 1782817Sksewell@umich.eduvoid 1792817Sksewell@umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1802817Sksewell@umich.edu{ 1812817Sksewell@umich.edu#if FULL_SYSTEM 1822817Sksewell@umich.edu if (thread->kernelStats) 1832817Sksewell@umich.edu thread->kernelStats->unserialize(cp, section); 1842817Sksewell@umich.edu#endif 1852817Sksewell@umich.edu 1862817Sksewell@umich.edu} 1872817Sksewell@umich.edu 1882817Sksewell@umich.edu#if FULL_SYSTEM 1892817Sksewell@umich.edutemplate <class Impl> 1902817Sksewell@umich.eduTick 1912817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 1922817Sksewell@umich.edu{ 1932817Sksewell@umich.edu return thread->lastActivate; 1942817Sksewell@umich.edu} 1952817Sksewell@umich.edu 1962817Sksewell@umich.edutemplate <class Impl> 1972817Sksewell@umich.eduTick 1982817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 1992817Sksewell@umich.edu{ 2002817Sksewell@umich.edu return thread->lastSuspend; 2012817Sksewell@umich.edu} 2022817Sksewell@umich.edu 2032817Sksewell@umich.edutemplate <class Impl> 2042817Sksewell@umich.eduvoid 2052817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 2063126Sktlim@umich.edu{ 2073126Sktlim@umich.edu thread->profileClear(); 2083126Sktlim@umich.edu} 2092817Sksewell@umich.edu 2102817Sksewell@umich.edutemplate <class Impl> 2112817Sksewell@umich.eduvoid 2122817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 2133126Sktlim@umich.edu{ 2143126Sktlim@umich.edu thread->profileSample(); 2153126Sktlim@umich.edu} 2162817Sksewell@umich.edu#endif 2172817Sksewell@umich.edu 2182817Sksewell@umich.edutemplate <class Impl> 2192817Sksewell@umich.eduvoid 2202817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2212817Sksewell@umich.edu{ 2222817Sksewell@umich.edu // This function will mess things up unless the ROB is empty and 2232817Sksewell@umich.edu // there are no instructions in the pipeline. 2246221Snate@binkert.org ThreadID tid = thread->threadId(); 2252817Sksewell@umich.edu PhysRegIndex renamed_reg; 2262817Sksewell@umich.edu 2272817Sksewell@umich.edu // First loop through the integer registers. 2282817Sksewell@umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 2292817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i); 2302817Sksewell@umich.edu 2312817Sksewell@umich.edu DPRINTF(O3CPU, "Copying over register %i, had data %lli, " 2322817Sksewell@umich.edu "now has data %lli.\n", 2332817Sksewell@umich.edu renamed_reg, cpu->readIntReg(renamed_reg), 2342817Sksewell@umich.edu tc->readIntReg(i)); 2352817Sksewell@umich.edu 2362817Sksewell@umich.edu cpu->setIntReg(renamed_reg, tc->readIntReg(i)); 2372817Sksewell@umich.edu } 2382817Sksewell@umich.edu 2392817Sksewell@umich.edu // Then loop through the floating point registers. 2402817Sksewell@umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 2412817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag); 2422817Sksewell@umich.edu cpu->setFloatRegBits(renamed_reg, 2432817Sksewell@umich.edu tc->readFloatRegBits(i)); 2442817Sksewell@umich.edu } 2452817Sksewell@umich.edu 2462817Sksewell@umich.edu // Copy the misc regs. 2472986Sgblack@eecs.umich.edu TheISA::copyMiscRegs(tc, this); 2482817Sksewell@umich.edu 2495258Sksewell@umich.edu // Then finally set the PC, the next PC, the nextNPC, the micropc, and the 2505258Sksewell@umich.edu // next micropc. 2517720Sgblack@eecs.umich.edu cpu->pcState(tc->pcState(), tid); 2522817Sksewell@umich.edu#if !FULL_SYSTEM 2532817Sksewell@umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2542817Sksewell@umich.edu#endif 2552817Sksewell@umich.edu} 2562817Sksewell@umich.edu 2572817Sksewell@umich.edutemplate <class Impl> 2582817Sksewell@umich.eduvoid 2592817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 2602817Sksewell@umich.edu{} 2612817Sksewell@umich.edu 2622817Sksewell@umich.edutemplate <class Impl> 2632817Sksewell@umich.eduuint64_t 2642817Sksewell@umich.eduO3ThreadContext<Impl>::readIntReg(int reg_idx) 2652817Sksewell@umich.edu{ 2666313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 2675715Shsul@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->threadId()); 2682817Sksewell@umich.edu} 2692817Sksewell@umich.edu 2702817Sksewell@umich.edutemplate <class Impl> 2712986Sgblack@eecs.umich.eduTheISA::FloatReg 2722817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx) 2732817Sksewell@umich.edu{ 2746313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2756314Sgblack@eecs.umich.edu return cpu->readArchFloatReg(reg_idx, thread->threadId()); 2762817Sksewell@umich.edu} 2772817Sksewell@umich.edu 2782817Sksewell@umich.edutemplate <class Impl> 2792986Sgblack@eecs.umich.eduTheISA::FloatRegBits 2802817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 2812817Sksewell@umich.edu{ 2826313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2835715Shsul@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 2842817Sksewell@umich.edu} 2852817Sksewell@umich.edu 2862817Sksewell@umich.edutemplate <class Impl> 2872817Sksewell@umich.eduvoid 2882817Sksewell@umich.eduO3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 2892817Sksewell@umich.edu{ 2906313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 2915715Shsul@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->threadId()); 2922817Sksewell@umich.edu 2932817Sksewell@umich.edu // Squash if we're not already in a state update mode. 2942817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 2955715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 2962817Sksewell@umich.edu } 2972817Sksewell@umich.edu} 2982817Sksewell@umich.edu 2992817Sksewell@umich.edutemplate <class Impl> 3002817Sksewell@umich.eduvoid 3012817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 3022817Sksewell@umich.edu{ 3036313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 3046314Sgblack@eecs.umich.edu cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 3052817Sksewell@umich.edu 3062817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3075715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3082817Sksewell@umich.edu } 3092817Sksewell@umich.edu} 3102817Sksewell@umich.edu 3112817Sksewell@umich.edutemplate <class Impl> 3122817Sksewell@umich.eduvoid 3132817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 3142817Sksewell@umich.edu{ 3156313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 3165715Shsul@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 3172817Sksewell@umich.edu 3182817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3192817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3205715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3212817Sksewell@umich.edu } 3222817Sksewell@umich.edu} 3232817Sksewell@umich.edu 3242817Sksewell@umich.edutemplate <class Impl> 3252817Sksewell@umich.eduvoid 3267720Sgblack@eecs.umich.eduO3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 3272817Sksewell@umich.edu{ 3287720Sgblack@eecs.umich.edu cpu->pcState(val, thread->threadId()); 3295258Sksewell@umich.edu 3305258Sksewell@umich.edu // Squash if we're not already in a state update mode. 3315258Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3325715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3335258Sksewell@umich.edu } 3345258Sksewell@umich.edu} 3355258Sksewell@umich.edu 3365258Sksewell@umich.edutemplate <class Impl> 3376313Sgblack@eecs.umich.eduint 3386313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenIntIndex(int reg) 3396313Sgblack@eecs.umich.edu{ 3406313Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenIntIndex(reg); 3416313Sgblack@eecs.umich.edu} 3426313Sgblack@eecs.umich.edu 3436313Sgblack@eecs.umich.edutemplate <class Impl> 3446313Sgblack@eecs.umich.eduint 3456313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenFloatIndex(int reg) 3466313Sgblack@eecs.umich.edu{ 3476313Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenFloatIndex(reg); 3486313Sgblack@eecs.umich.edu} 3496313Sgblack@eecs.umich.edu 3506313Sgblack@eecs.umich.edutemplate <class Impl> 3515258Sksewell@umich.eduvoid 3524172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3532817Sksewell@umich.edu{ 3545715Shsul@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 3552817Sksewell@umich.edu 3562817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3572817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3585715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3592817Sksewell@umich.edu } 3602817Sksewell@umich.edu} 3612817Sksewell@umich.edu 3622817Sksewell@umich.edutemplate <class Impl> 3633468Sgblack@eecs.umich.eduvoid 3644172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscReg(int misc_reg, 3652817Sksewell@umich.edu const MiscReg &val) 3662817Sksewell@umich.edu{ 3675715Shsul@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->threadId()); 3682817Sksewell@umich.edu 3692817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3702817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3715715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3722817Sksewell@umich.edu } 3732817Sksewell@umich.edu} 3742817Sksewell@umich.edu 375