thread_context_impl.hh revision 7720
17139Sgblack@eecs.umich.edu/* 27139Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 37139Sgblack@eecs.umich.edu * All rights reserved. 47139Sgblack@eecs.umich.edu * 57139Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67139Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77139Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87139Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97139Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107139Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117139Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127139Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137139Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147139Sgblack@eecs.umich.edu * this software without specific prior written permission. 157139Sgblack@eecs.umich.edu * 167139Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177139Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187139Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197139Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207139Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217139Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227139Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237139Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247139Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257139Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267139Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277139Sgblack@eecs.umich.edu * 287139Sgblack@eecs.umich.edu * Authors: Kevin Lim 297139Sgblack@eecs.umich.edu * Korey Sewell 307139Sgblack@eecs.umich.edu */ 317139Sgblack@eecs.umich.edu 327139Sgblack@eecs.umich.edu#include "arch/registers.hh" 337139Sgblack@eecs.umich.edu#include "config/the_isa.hh" 347139Sgblack@eecs.umich.edu#include "cpu/o3/thread_context.hh" 357139Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 367139Sgblack@eecs.umich.edu 377139Sgblack@eecs.umich.edu#if FULL_SYSTEM 387255Sgblack@eecs.umich.edutemplate <class Impl> 397243Sgblack@eecs.umich.eduVirtualPort * 407243Sgblack@eecs.umich.eduO3ThreadContext<Impl>::getVirtPort() 417255Sgblack@eecs.umich.edu{ 427255Sgblack@eecs.umich.edu return thread->getVirtPort(); 437243Sgblack@eecs.umich.edu} 447243Sgblack@eecs.umich.edu 457255Sgblack@eecs.umich.edutemplate <class Impl> 467255Sgblack@eecs.umich.eduvoid 477255Sgblack@eecs.umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 487255Sgblack@eecs.umich.edu{ 497255Sgblack@eecs.umich.edu thread->dumpFuncProfile(); 507255Sgblack@eecs.umich.edu} 517255Sgblack@eecs.umich.edu#endif 527255Sgblack@eecs.umich.edu 537255Sgblack@eecs.umich.edutemplate <class Impl> 547255Sgblack@eecs.umich.eduvoid 557255Sgblack@eecs.umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 567256Sgblack@eecs.umich.edu{ 577256Sgblack@eecs.umich.edu // some things should already be set up 587255Sgblack@eecs.umich.edu#if FULL_SYSTEM 597256Sgblack@eecs.umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 607255Sgblack@eecs.umich.edu#else 617256Sgblack@eecs.umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 627255Sgblack@eecs.umich.edu#endif 637255Sgblack@eecs.umich.edu 647258Sgblack@eecs.umich.edu // copy over functional state 657258Sgblack@eecs.umich.edu setStatus(old_context->status()); 667255Sgblack@eecs.umich.edu copyArchRegs(old_context); 677258Sgblack@eecs.umich.edu setContextId(old_context->contextId()); 687255Sgblack@eecs.umich.edu setThreadId(old_context->threadId()); 697258Sgblack@eecs.umich.edu 707255Sgblack@eecs.umich.edu#if !FULL_SYSTEM 717243Sgblack@eecs.umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 727255Sgblack@eecs.umich.edu#else 737243Sgblack@eecs.umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 747243Sgblack@eecs.umich.edu if (other_quiesce) { 757243Sgblack@eecs.umich.edu // Point the quiesce event's TC at this TC so that it wakes up 767243Sgblack@eecs.umich.edu // the proper CPU. 777139Sgblack@eecs.umich.edu other_quiesce->tc = this; 787188Sgblack@eecs.umich.edu } 797188Sgblack@eecs.umich.edu if (thread->quiesceEvent) { 807188Sgblack@eecs.umich.edu thread->quiesceEvent->tc = this; 817188Sgblack@eecs.umich.edu } 827188Sgblack@eecs.umich.edu 837139Sgblack@eecs.umich.edu // Transfer kernel stats from one CPU to the other. 847139Sgblack@eecs.umich.edu thread->kernelStats = old_context->getKernelStats(); 857139Sgblack@eecs.umich.edu// storeCondFailures = 0; 867139Sgblack@eecs.umich.edu cpu->lockFlag = false; 877188Sgblack@eecs.umich.edu#endif 887188Sgblack@eecs.umich.edu 897188Sgblack@eecs.umich.edu old_context->setStatus(ThreadContext::Halted); 907188Sgblack@eecs.umich.edu 917188Sgblack@eecs.umich.edu thread->inSyscall = false; 927188Sgblack@eecs.umich.edu thread->trapPending = false; 937139Sgblack@eecs.umich.edu} 947146Sgblack@eecs.umich.edu 957141Sgblack@eecs.umich.edutemplate <class Impl> 967139Sgblack@eecs.umich.eduvoid 977139Sgblack@eecs.umich.eduO3ThreadContext<Impl>::activate(int delay) 987139Sgblack@eecs.umich.edu{ 997146Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 1007141Sgblack@eecs.umich.edu threadId()); 1017139Sgblack@eecs.umich.edu 1027146Sgblack@eecs.umich.edu if (thread->status() == ThreadContext::Active) 1037141Sgblack@eecs.umich.edu return; 1047139Sgblack@eecs.umich.edu 1057139Sgblack@eecs.umich.edu#if FULL_SYSTEM 1067139Sgblack@eecs.umich.edu thread->lastActivate = curTick; 1077139Sgblack@eecs.umich.edu#endif 1087139Sgblack@eecs.umich.edu 1097188Sgblack@eecs.umich.edu thread->setStatus(ThreadContext::Active); 1107188Sgblack@eecs.umich.edu 1117188Sgblack@eecs.umich.edu // status() == Suspended 1127188Sgblack@eecs.umich.edu cpu->activateContext(thread->threadId(), delay); 1137188Sgblack@eecs.umich.edu} 1147188Sgblack@eecs.umich.edu 1157188Sgblack@eecs.umich.edutemplate <class Impl> 1167188Sgblack@eecs.umich.eduvoid 1177188Sgblack@eecs.umich.eduO3ThreadContext<Impl>::suspend(int delay) 1187188Sgblack@eecs.umich.edu{ 1197188Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1207188Sgblack@eecs.umich.edu threadId()); 1217188Sgblack@eecs.umich.edu 1227188Sgblack@eecs.umich.edu if (thread->status() == ThreadContext::Suspended) 1237188Sgblack@eecs.umich.edu return; 1247188Sgblack@eecs.umich.edu 1257188Sgblack@eecs.umich.edu#if FULL_SYSTEM 1267188Sgblack@eecs.umich.edu thread->lastActivate = curTick; 1277188Sgblack@eecs.umich.edu thread->lastSuspend = curTick; 1287188Sgblack@eecs.umich.edu#endif 1297139Sgblack@eecs.umich.edu/* 1307139Sgblack@eecs.umich.edu#if FULL_SYSTEM 1317139Sgblack@eecs.umich.edu // Don't change the status from active if there are pending interrupts 1327139Sgblack@eecs.umich.edu if (cpu->checkInterrupts()) { 1337139Sgblack@eecs.umich.edu assert(status() == ThreadContext::Active); 1347139Sgblack@eecs.umich.edu return; 1357139Sgblack@eecs.umich.edu } 1367139Sgblack@eecs.umich.edu#endif 1377139Sgblack@eecs.umich.edu*/ 1387139Sgblack@eecs.umich.edu thread->setStatus(ThreadContext::Suspended); 1397139Sgblack@eecs.umich.edu cpu->suspendContext(thread->threadId()); 1407139Sgblack@eecs.umich.edu} 1417139Sgblack@eecs.umich.edu 1427139Sgblack@eecs.umich.edutemplate <class Impl> 1437139Sgblack@eecs.umich.eduvoid 1447139Sgblack@eecs.umich.eduO3ThreadContext<Impl>::halt(int delay) 1457139Sgblack@eecs.umich.edu{ 1467139Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 1477139Sgblack@eecs.umich.edu threadId()); 1487139Sgblack@eecs.umich.edu 1497139Sgblack@eecs.umich.edu if (thread->status() == ThreadContext::Halted) 1507188Sgblack@eecs.umich.edu return; 1517188Sgblack@eecs.umich.edu 1527188Sgblack@eecs.umich.edu thread->setStatus(ThreadContext::Halted); 1537188Sgblack@eecs.umich.edu cpu->haltContext(thread->threadId()); 1547139Sgblack@eecs.umich.edu} 1557188Sgblack@eecs.umich.edu 1567139Sgblack@eecs.umich.edutemplate <class Impl> 1577188Sgblack@eecs.umich.eduvoid 1587139Sgblack@eecs.umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1597139Sgblack@eecs.umich.edu{ 1607139Sgblack@eecs.umich.edu#if FULL_SYSTEM 1617139Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1627139Sgblack@eecs.umich.edu thread->kernelStats->regStats(name + ".kern"); 1637139Sgblack@eecs.umich.edu#endif 1647139Sgblack@eecs.umich.edu} 1657139Sgblack@eecs.umich.edu 1667210Sgblack@eecs.umich.edutemplate <class Impl> 1677210Sgblack@eecs.umich.eduvoid 1687210Sgblack@eecs.umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 1697210Sgblack@eecs.umich.edu{ 1707210Sgblack@eecs.umich.edu#if FULL_SYSTEM 1717210Sgblack@eecs.umich.edu if (thread->kernelStats) 1727210Sgblack@eecs.umich.edu thread->kernelStats->serialize(os); 1737227Sgblack@eecs.umich.edu#endif 1747227Sgblack@eecs.umich.edu 1757227Sgblack@eecs.umich.edu} 1767227Sgblack@eecs.umich.edu 1777227Sgblack@eecs.umich.edutemplate <class Impl> 1787227Sgblack@eecs.umich.eduvoid 1797227Sgblack@eecs.umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1807227Sgblack@eecs.umich.edu{ 1817210Sgblack@eecs.umich.edu#if FULL_SYSTEM 1827237Sgblack@eecs.umich.edu if (thread->kernelStats) 1837237Sgblack@eecs.umich.edu thread->kernelStats->unserialize(cp, section); 1847237Sgblack@eecs.umich.edu#endif 1857237Sgblack@eecs.umich.edu 1867237Sgblack@eecs.umich.edu} 1877237Sgblack@eecs.umich.edu 1887237Sgblack@eecs.umich.edu#if FULL_SYSTEM 1897210Sgblack@eecs.umich.edutemplate <class Impl> 1907227Sgblack@eecs.umich.eduTick 1917210Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readLastActivate() 1927227Sgblack@eecs.umich.edu{ 1937210Sgblack@eecs.umich.edu return thread->lastActivate; 1947210Sgblack@eecs.umich.edu} 1957210Sgblack@eecs.umich.edu 1967210Sgblack@eecs.umich.edutemplate <class Impl> 1977210Sgblack@eecs.umich.eduTick 1987240Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readLastSuspend() 1997235Sgblack@eecs.umich.edu{ 2007235Sgblack@eecs.umich.edu return thread->lastSuspend; 2017235Sgblack@eecs.umich.edu} 2027235Sgblack@eecs.umich.edu 2037235Sgblack@eecs.umich.edutemplate <class Impl> 2047235Sgblack@eecs.umich.eduvoid 2057240Sgblack@eecs.umich.eduO3ThreadContext<Impl>::profileClear() 2067240Sgblack@eecs.umich.edu{ 2077240Sgblack@eecs.umich.edu thread->profileClear(); 2087240Sgblack@eecs.umich.edu} 2097240Sgblack@eecs.umich.edu 2107240Sgblack@eecs.umich.edutemplate <class Impl> 2117240Sgblack@eecs.umich.eduvoid 2127240Sgblack@eecs.umich.eduO3ThreadContext<Impl>::profileSample() 2137240Sgblack@eecs.umich.edu{ 2147240Sgblack@eecs.umich.edu thread->profileSample(); 2157210Sgblack@eecs.umich.edu} 2167210Sgblack@eecs.umich.edu#endif 2177210Sgblack@eecs.umich.edu 2187210Sgblack@eecs.umich.edutemplate <class Impl> 2197210Sgblack@eecs.umich.eduvoid 2207227Sgblack@eecs.umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2217227Sgblack@eecs.umich.edu{ 2227227Sgblack@eecs.umich.edu // This function will mess things up unless the ROB is empty and 2237227Sgblack@eecs.umich.edu // there are no instructions in the pipeline. 2247227Sgblack@eecs.umich.edu ThreadID tid = thread->threadId(); 2257227Sgblack@eecs.umich.edu PhysRegIndex renamed_reg; 2267210Sgblack@eecs.umich.edu 2277235Sgblack@eecs.umich.edu // First loop through the integer registers. 2287235Sgblack@eecs.umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 2297235Sgblack@eecs.umich.edu renamed_reg = cpu->renameMap[tid].lookup(i); 2307235Sgblack@eecs.umich.edu 2317235Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Copying over register %i, had data %lli, " 2327235Sgblack@eecs.umich.edu "now has data %lli.\n", 2337235Sgblack@eecs.umich.edu renamed_reg, cpu->readIntReg(renamed_reg), 2347235Sgblack@eecs.umich.edu tc->readIntReg(i)); 2357210Sgblack@eecs.umich.edu 2367235Sgblack@eecs.umich.edu cpu->setIntReg(renamed_reg, tc->readIntReg(i)); 2377210Sgblack@eecs.umich.edu } 2387235Sgblack@eecs.umich.edu 2397210Sgblack@eecs.umich.edu // Then loop through the floating point registers. 2407210Sgblack@eecs.umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 2417210Sgblack@eecs.umich.edu renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag); 2427210Sgblack@eecs.umich.edu cpu->setFloatRegBits(renamed_reg, 2437210Sgblack@eecs.umich.edu tc->readFloatRegBits(i)); 2447211Sgblack@eecs.umich.edu } 2457211Sgblack@eecs.umich.edu 2467211Sgblack@eecs.umich.edu // Copy the misc regs. 2477210Sgblack@eecs.umich.edu TheISA::copyMiscRegs(tc, this); 2487235Sgblack@eecs.umich.edu 2497235Sgblack@eecs.umich.edu // Then finally set the PC, the next PC, the nextNPC, the micropc, and the 2507235Sgblack@eecs.umich.edu // next micropc. 2517235Sgblack@eecs.umich.edu cpu->pcState(tc->pcState(), tid); 2527235Sgblack@eecs.umich.edu#if !FULL_SYSTEM 2537235Sgblack@eecs.umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2547235Sgblack@eecs.umich.edu#endif 2557235Sgblack@eecs.umich.edu} 2567210Sgblack@eecs.umich.edu 2577235Sgblack@eecs.umich.edutemplate <class Impl> 2587210Sgblack@eecs.umich.eduvoid 2597235Sgblack@eecs.umich.eduO3ThreadContext<Impl>::clearArchRegs() 2607210Sgblack@eecs.umich.edu{} 2617210Sgblack@eecs.umich.edu 2627211Sgblack@eecs.umich.edutemplate <class Impl> 2637211Sgblack@eecs.umich.eduuint64_t 2647211Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readIntReg(int reg_idx) 2657210Sgblack@eecs.umich.edu{ 2667210Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 2677210Sgblack@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->threadId()); 2687210Sgblack@eecs.umich.edu} 2697235Sgblack@eecs.umich.edu 2707235Sgblack@eecs.umich.edutemplate <class Impl> 2717235Sgblack@eecs.umich.eduTheISA::FloatReg 2727235Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx) 2737235Sgblack@eecs.umich.edu{ 2747235Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2757235Sgblack@eecs.umich.edu return cpu->readArchFloatReg(reg_idx, thread->threadId()); 2767235Sgblack@eecs.umich.edu} 2777210Sgblack@eecs.umich.edu 2787235Sgblack@eecs.umich.edutemplate <class Impl> 2797210Sgblack@eecs.umich.eduTheISA::FloatRegBits 2807235Sgblack@eecs.umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 2817210Sgblack@eecs.umich.edu{ 2827210Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2837210Sgblack@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 2847210Sgblack@eecs.umich.edu} 2857210Sgblack@eecs.umich.edu 2867227Sgblack@eecs.umich.edutemplate <class Impl> 2877227Sgblack@eecs.umich.eduvoid 2887227Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 2897227Sgblack@eecs.umich.edu{ 2907227Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 2917227Sgblack@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->threadId()); 2927210Sgblack@eecs.umich.edu 2937235Sgblack@eecs.umich.edu // Squash if we're not already in a state update mode. 2947235Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 2957235Sgblack@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 2967235Sgblack@eecs.umich.edu } 2977235Sgblack@eecs.umich.edu} 2987235Sgblack@eecs.umich.edu 2997235Sgblack@eecs.umich.edutemplate <class Impl> 3007235Sgblack@eecs.umich.eduvoid 3017210Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 3027235Sgblack@eecs.umich.edu{ 3037210Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 3047235Sgblack@eecs.umich.edu cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 3057210Sgblack@eecs.umich.edu 3067210Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 3077210Sgblack@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3087210Sgblack@eecs.umich.edu } 3097250Sgblack@eecs.umich.edu} 3107235Sgblack@eecs.umich.edu 3117235Sgblack@eecs.umich.edutemplate <class Impl> 3127235Sgblack@eecs.umich.eduvoid 3137235Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 3147235Sgblack@eecs.umich.edu{ 3157235Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 3167250Sgblack@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 3177250Sgblack@eecs.umich.edu 3187250Sgblack@eecs.umich.edu // Squash if we're not already in a state update mode. 3197250Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 3207250Sgblack@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3217250Sgblack@eecs.umich.edu } 3227250Sgblack@eecs.umich.edu} 3237250Sgblack@eecs.umich.edu 3247250Sgblack@eecs.umich.edutemplate <class Impl> 3257250Sgblack@eecs.umich.eduvoid 3267250Sgblack@eecs.umich.eduO3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 3277250Sgblack@eecs.umich.edu{ 3287210Sgblack@eecs.umich.edu cpu->pcState(val, thread->threadId()); 3297210Sgblack@eecs.umich.edu 3307210Sgblack@eecs.umich.edu // Squash if we're not already in a state update mode. 3317210Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 3327210Sgblack@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3337210Sgblack@eecs.umich.edu } 3347210Sgblack@eecs.umich.edu} 3357210Sgblack@eecs.umich.edu 3367210Sgblack@eecs.umich.edutemplate <class Impl> 3377194Sgblack@eecs.umich.eduint 3387194Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenIntIndex(int reg) 3397194Sgblack@eecs.umich.edu{ 3407194Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenIntIndex(reg); 3417194Sgblack@eecs.umich.edu} 3427194Sgblack@eecs.umich.edu 3437194Sgblack@eecs.umich.edutemplate <class Impl> 3447194Sgblack@eecs.umich.eduint 3457194Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenFloatIndex(int reg) 3467194Sgblack@eecs.umich.edu{ 3477194Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenFloatIndex(reg); 3487194Sgblack@eecs.umich.edu} 3497194Sgblack@eecs.umich.edu 3507216Sgblack@eecs.umich.edutemplate <class Impl> 3517194Sgblack@eecs.umich.eduvoid 3527224Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3537194Sgblack@eecs.umich.edu{ 3547224Sgblack@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 3557194Sgblack@eecs.umich.edu 3567218Sgblack@eecs.umich.edu // Squash if we're not already in a state update mode. 3577194Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 3587216Sgblack@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3597194Sgblack@eecs.umich.edu } 3607218Sgblack@eecs.umich.edu} 3617194Sgblack@eecs.umich.edu 3627194Sgblack@eecs.umich.edutemplate <class Impl> 3637194Sgblack@eecs.umich.eduvoid 3647194Sgblack@eecs.umich.eduO3ThreadContext<Impl>::setMiscReg(int misc_reg, 3657194Sgblack@eecs.umich.edu const MiscReg &val) 3667194Sgblack@eecs.umich.edu{ 3677194Sgblack@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->threadId()); 3687194Sgblack@eecs.umich.edu 3697194Sgblack@eecs.umich.edu // Squash if we're not already in a state update mode. 3707194Sgblack@eecs.umich.edu if (!thread->trapPending && !thread->inSyscall) { 3717194Sgblack@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3727194Sgblack@eecs.umich.edu } 3737194Sgblack@eecs.umich.edu} 3747194Sgblack@eecs.umich.edu 3757194Sgblack@eecs.umich.edu