store_set.hh revision 2348
12SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#ifndef __CPU_O3_STORE_SET_HH__ 302SN/A#define __CPU_O3_STORE_SET_HH__ 312SN/A 322SN/A#include <list> 332SN/A#include <map> 342SN/A#include <utility> 352SN/A#include <vector> 361354SN/A 371354SN/A#include "arch/isa_traits.hh" 382SN/A#include "cpu/inst_seq.hh" 392SN/A 405501Snate@binkert.orgstruct ltseqnum { 415546Snate@binkert.org bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const 427004Snate@binkert.org { 432SN/A return lhs > rhs; 442SN/A } 455769Snate@binkert.org}; 462361SN/A 476216Snate@binkert.org/** 488232Snate@binkert.org * Implements a store set predictor for determining if memory 4956SN/A * instructions are dependent upon each other. See paper "Memory 502SN/A * Dependence Prediction using Store Sets" by Chrysos and Emer. SSID 515543Ssaidi@eecs.umich.edu * stands for Store Set ID, SSIT stands for Store Set ID Table, and 522SN/A * LFST is Last Fetched Store Table. 531354SN/A */ 541354SN/Aclass StoreSet 552SN/A{ 562SN/A public: 572SN/A typedef unsigned SSID; 582SN/A 595501Snate@binkert.org public: 605501Snate@binkert.org /** Default constructor. init() must be called prior to use. */ 612SN/A StoreSet() { }; 629044SAli.Saidi@ARM.com 632SN/A /** Creates store set predictor with given table sizes. */ 642SN/A StoreSet(int SSIT_size, int LFST_size); 652SN/A 665769Snate@binkert.org /** Default destructor. */ 678902Sandreas.hansson@arm.com ~StoreSet(); 685769Snate@binkert.org 695769Snate@binkert.org /** Initializes the store set predictor with the given table sizes. */ 707059Snate@binkert.org void init(int SSIT_size, int LFST_size); 717059Snate@binkert.org 727059Snate@binkert.org /** Records a memory ordering violation between the younger load 737059Snate@binkert.org * and the older store. */ 747059Snate@binkert.org void violation(Addr store_PC, Addr load_PC); 757059Snate@binkert.org 767059Snate@binkert.org /** Inserts a load into the store set predictor. This does nothing but 777059Snate@binkert.org * is included in case other predictors require a similar function. 787059Snate@binkert.org */ 797059Snate@binkert.org void insertLoad(Addr load_PC, InstSeqNum load_seq_num); 807059Snate@binkert.org 817059Snate@binkert.org /** Inserts a store into the store set predictor. Updates the 827059Snate@binkert.org * LFST if the store has a valid SSID. */ 837059Snate@binkert.org void insertStore(Addr store_PC, InstSeqNum store_seq_num, 847059Snate@binkert.org unsigned tid); 857059Snate@binkert.org 865769Snate@binkert.org /** Checks if the instruction with the given PC is dependent upon 877058Snate@binkert.org * any store. @return Returns the sequence number of the store 887058Snate@binkert.org * instruction this PC is dependent upon. Returns 0 if none. 897058Snate@binkert.org */ 902SN/A InstSeqNum checkInst(Addr PC); 915502Snate@binkert.org 925502Snate@binkert.org /** Records this PC/sequence number as issued. */ 935502Snate@binkert.org void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store); 945503Snate@binkert.org 955503Snate@binkert.org /** Squashes for a specific thread until the given sequence number. */ 965502Snate@binkert.org void squash(InstSeqNum squashed_num, unsigned tid); 975502Snate@binkert.org 985502Snate@binkert.org /** Resets all tables. */ 995502Snate@binkert.org void clear(); 1005502Snate@binkert.org 1015502Snate@binkert.org /** Debug function to dump the contents of the store list. */ 1025502Snate@binkert.org void dump(); 1035602Snate@binkert.org 1045602Snate@binkert.org private: 1055501Snate@binkert.org /** Calculates the index into the SSIT based on the PC. */ 1065543Ssaidi@eecs.umich.edu inline int calcIndex(Addr PC) 1077058Snate@binkert.org { return (PC >> offsetBits) & indexMask; } 1085769Snate@binkert.org 1094016Sstever@eecs.umich.edu /** Calculates a Store Set ID based on the PC. */ 1104016Sstever@eecs.umich.edu inline SSID calcSSID(Addr PC) 1114016Sstever@eecs.umich.edu { return ((PC ^ (PC >> 10)) % LFSTSize); } 1124016Sstever@eecs.umich.edu 1134016Sstever@eecs.umich.edu /** The Store Set ID Table. */ 1144016Sstever@eecs.umich.edu std::vector<SSID> SSIT; 1154016Sstever@eecs.umich.edu 1164016Sstever@eecs.umich.edu /** Bit vector to tell if the SSIT has a valid entry. */ 1174016Sstever@eecs.umich.edu std::vector<bool> validSSIT; 1185501Snate@binkert.org 1195605Snate@binkert.org /** Last Fetched Store Table. */ 1205605Snate@binkert.org std::vector<InstSeqNum> LFST; 1215605Snate@binkert.org 1225605Snate@binkert.org /** Bit vector to tell if the LFST has a valid entry. */ 1235501Snate@binkert.org std::vector<bool> validLFST; 1244016Sstever@eecs.umich.edu 1255577SSteve.Reinhardt@amd.com /** Map of stores that have been inserted into the store set, but 1265501Snate@binkert.org * not yet issued or squashed. 1275501Snate@binkert.org */ 1285501Snate@binkert.org std::map<InstSeqNum, int, ltseqnum> storeList; 1295502Snate@binkert.org 1305502Snate@binkert.org typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt; 1315605Snate@binkert.org 1325502Snate@binkert.org /** Store Set ID Table size, in entries. */ 1335502Snate@binkert.org int SSITSize; 1345605Snate@binkert.org 1355605Snate@binkert.org /** Last Fetched Store Table size, in entries. */ 1365605Snate@binkert.org int LFSTSize; 1375577SSteve.Reinhardt@amd.com 1387823Ssteve.reinhardt@amd.com /** Mask to obtain the index. */ 1395502Snate@binkert.org int indexMask; 1405502Snate@binkert.org 1415502Snate@binkert.org // HACK: Hardcoded for now. 1422SN/A int offsetBits; 1435769Snate@binkert.org}; 1445769Snate@binkert.org 1455769Snate@binkert.org#endif // __CPU_O3_STORE_SET_HH__ 1465769Snate@binkert.org