store_set.hh revision 2348 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_STORE_SET_HH__
30#define __CPU_O3_STORE_SET_HH__
31
32#include <list>
33#include <map>
34#include <utility>
35#include <vector>
36
37#include "arch/isa_traits.hh"
38#include "cpu/inst_seq.hh"
39
40struct ltseqnum {
41    bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
42    {
43        return lhs > rhs;
44    }
45};
46
47/**
48 * Implements a store set predictor for determining if memory
49 * instructions are dependent upon each other.  See paper "Memory
50 * Dependence Prediction using Store Sets" by Chrysos and Emer.  SSID
51 * stands for Store Set ID, SSIT stands for Store Set ID Table, and
52 * LFST is Last Fetched Store Table.
53 */
54class StoreSet
55{
56  public:
57    typedef unsigned SSID;
58
59  public:
60    /** Default constructor.  init() must be called prior to use. */
61    StoreSet() { };
62
63    /** Creates store set predictor with given table sizes. */
64    StoreSet(int SSIT_size, int LFST_size);
65
66    /** Default destructor. */
67    ~StoreSet();
68
69    /** Initializes the store set predictor with the given table sizes. */
70    void init(int SSIT_size, int LFST_size);
71
72    /** Records a memory ordering violation between the younger load
73     * and the older store. */
74    void violation(Addr store_PC, Addr load_PC);
75
76    /** Inserts a load into the store set predictor.  This does nothing but
77     * is included in case other predictors require a similar function.
78     */
79    void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
80
81    /** Inserts a store into the store set predictor.  Updates the
82     * LFST if the store has a valid SSID. */
83    void insertStore(Addr store_PC, InstSeqNum store_seq_num,
84                     unsigned tid);
85
86    /** Checks if the instruction with the given PC is dependent upon
87     * any store.  @return Returns the sequence number of the store
88     * instruction this PC is dependent upon.  Returns 0 if none.
89     */
90    InstSeqNum checkInst(Addr PC);
91
92    /** Records this PC/sequence number as issued. */
93    void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
94
95    /** Squashes for a specific thread until the given sequence number. */
96    void squash(InstSeqNum squashed_num, unsigned tid);
97
98    /** Resets all tables. */
99    void clear();
100
101    /** Debug function to dump the contents of the store list. */
102    void dump();
103
104  private:
105    /** Calculates the index into the SSIT based on the PC. */
106    inline int calcIndex(Addr PC)
107    { return (PC >> offsetBits) & indexMask; }
108
109    /** Calculates a Store Set ID based on the PC. */
110    inline SSID calcSSID(Addr PC)
111    { return ((PC ^ (PC >> 10)) % LFSTSize); }
112
113    /** The Store Set ID Table. */
114    std::vector<SSID> SSIT;
115
116    /** Bit vector to tell if the SSIT has a valid entry. */
117    std::vector<bool> validSSIT;
118
119    /** Last Fetched Store Table. */
120    std::vector<InstSeqNum> LFST;
121
122    /** Bit vector to tell if the LFST has a valid entry. */
123    std::vector<bool> validLFST;
124
125    /** Map of stores that have been inserted into the store set, but
126     * not yet issued or squashed.
127     */
128    std::map<InstSeqNum, int, ltseqnum> storeList;
129
130    typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
131
132    /** Store Set ID Table size, in entries. */
133    int SSITSize;
134
135    /** Last Fetched Store Table size, in entries. */
136    int LFSTSize;
137
138    /** Mask to obtain the index. */
139    int indexMask;
140
141    // HACK: Hardcoded for now.
142    int offsetBits;
143};
144
145#endif // __CPU_O3_STORE_SET_HH__
146