rob.hh revision 2831
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292831Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322292SN/A#ifndef __CPU_O3_ROB_HH__ 332292SN/A#define __CPU_O3_ROB_HH__ 341060SN/A 352292SN/A#include <string> 361461SN/A#include <utility> 371461SN/A#include <vector> 381060SN/A 391060SN/A/** 402292SN/A * ROB class. The ROB is largely what drives squashing. 411060SN/A */ 421061SN/Atemplate <class Impl> 431060SN/Aclass ROB 441060SN/A{ 452107SN/A protected: 462107SN/A typedef TheISA::RegIndex RegIndex; 471060SN/A public: 481060SN/A //Typedefs from the Impl. 492733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 501061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 511060SN/A 522292SN/A typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo; 532292SN/A typedef typename std::list<DynInstPtr>::iterator InstIt; 542292SN/A 552292SN/A /** Possible ROB statuses. */ 562292SN/A enum Status { 572292SN/A Running, 582292SN/A Idle, 592329SN/A ROBSquashing 602292SN/A }; 612292SN/A 622292SN/A /** SMT ROB Sharing Policy */ 632292SN/A enum ROBPolicy{ 642292SN/A Dynamic, 652292SN/A Partitioned, 662292SN/A Threshold 672292SN/A }; 682292SN/A 692292SN/A private: 702292SN/A /** Per-thread ROB status. */ 712292SN/A Status robStatus[Impl::MaxThreads]; 722292SN/A 732292SN/A /** ROB resource sharing policy for SMT mode. */ 742292SN/A ROBPolicy robPolicy; 751060SN/A 761060SN/A public: 771060SN/A /** ROB constructor. 782292SN/A * @param _numEntries Number of entries in ROB. 792292SN/A * @param _squashWidth Number of instructions that can be squashed in a 802292SN/A * single cycle. 812292SN/A * @param _smtROBPolicy ROB Partitioning Scheme for SMT. 822292SN/A * @param _smtROBThreshold Max Resources(by %) a thread can have in the ROB. 832292SN/A * @param _numThreads The number of active threads. 841060SN/A */ 852292SN/A ROB(unsigned _numEntries, unsigned _squashWidth, std::string smtROBPolicy, 862292SN/A unsigned _smtROBThreshold, unsigned _numThreads); 872292SN/A 882292SN/A std::string name() const; 891060SN/A 901060SN/A /** Function to set the CPU pointer, necessary due to which object the ROB 911060SN/A * is created within. 921763SN/A * @param cpu_ptr Pointer to the implementation specific full CPU object. 931060SN/A */ 942733Sktlim@umich.edu void setCPU(O3CPU *cpu_ptr); 951060SN/A 962292SN/A /** Sets pointer to the list of active threads. 972292SN/A * @param at_ptr Pointer to the list of active threads. 982292SN/A */ 992292SN/A void setActiveThreads(std::list<unsigned>* at_ptr); 1002292SN/A 1012348SN/A /** Switches out the ROB. */ 1022307SN/A void switchOut(); 1032307SN/A 1042348SN/A /** Takes over another CPU's thread. */ 1052307SN/A void takeOverFrom(); 1062307SN/A 1072292SN/A /** Function to insert an instruction into the ROB. Note that whatever 1082292SN/A * calls this function must ensure that there is enough space within the 1092292SN/A * ROB for the new instruction. 1101763SN/A * @param inst The instruction being inserted into the ROB. 1111060SN/A */ 1121061SN/A void insertInst(DynInstPtr &inst); 1131060SN/A 1141060SN/A /** Returns pointer to the head instruction within the ROB. There is 1151060SN/A * no guarantee as to the return value if the ROB is empty. 1161060SN/A * @retval Pointer to the DynInst that is at the head of the ROB. 1171060SN/A */ 1182329SN/A// DynInstPtr readHeadInst(); 1191060SN/A 1202292SN/A /** Returns a pointer to the head instruction of a specific thread within 1212292SN/A * the ROB. 1222292SN/A * @return Pointer to the DynInst that is at the head of the ROB. 1232292SN/A */ 1242292SN/A DynInstPtr readHeadInst(unsigned tid); 1251060SN/A 1262292SN/A /** Returns pointer to the tail instruction within the ROB. There is 1272292SN/A * no guarantee as to the return value if the ROB is empty. 1282292SN/A * @retval Pointer to the DynInst that is at the tail of the ROB. 1292292SN/A */ 1302329SN/A// DynInstPtr readTailInst(); 1311060SN/A 1322292SN/A /** Returns a pointer to the tail instruction of a specific thread within 1332292SN/A * the ROB. 1342292SN/A * @return Pointer to the DynInst that is at the tail of the ROB. 1352292SN/A */ 1362292SN/A DynInstPtr readTailInst(unsigned tid); 1371060SN/A 1382292SN/A /** Retires the head instruction, removing it from the ROB. */ 1392329SN/A// void retireHead(); 1402107SN/A 1412292SN/A /** Retires the head instruction of a specific thread, removing it from the 1422292SN/A * ROB. 1432292SN/A */ 1442292SN/A void retireHead(unsigned tid); 1452292SN/A 1462292SN/A /** Is the oldest instruction across all threads ready. */ 1472329SN/A// bool isHeadReady(); 1482107SN/A 1492292SN/A /** Is the oldest instruction across a particular thread ready. */ 1502292SN/A bool isHeadReady(unsigned tid); 1512292SN/A 1522292SN/A /** Is there any commitable head instruction across all threads ready. */ 1532292SN/A bool canCommit(); 1542292SN/A 1552292SN/A /** Re-adjust ROB partitioning. */ 1562292SN/A void resetEntries(); 1572292SN/A 1582292SN/A /** Number of entries needed For 'num_threads' amount of threads. */ 1592292SN/A int entryAmount(int num_threads); 1602292SN/A 1612292SN/A /** Returns the number of total free entries in the ROB. */ 1621060SN/A unsigned numFreeEntries(); 1631060SN/A 1642292SN/A /** Returns the number of free entries in a specific ROB paritition. */ 1652292SN/A unsigned numFreeEntries(unsigned tid); 1662292SN/A 1672292SN/A /** Returns the maximum number of entries for a specific thread. */ 1682292SN/A unsigned getMaxEntries(unsigned tid) 1692292SN/A { return maxEntries[tid]; } 1702292SN/A 1712292SN/A /** Returns the number of entries being used by a specific thread. */ 1722292SN/A unsigned getThreadEntries(unsigned tid) 1732292SN/A { return threadEntries[tid]; } 1742292SN/A 1752292SN/A /** Returns if the ROB is full. */ 1761060SN/A bool isFull() 1771060SN/A { return numInstsInROB == numEntries; } 1781060SN/A 1792292SN/A /** Returns if a specific thread's partition is full. */ 1802292SN/A bool isFull(unsigned tid) 1812292SN/A { return threadEntries[tid] == numEntries; } 1822292SN/A 1832292SN/A /** Returns if the ROB is empty. */ 1841060SN/A bool isEmpty() 1851060SN/A { return numInstsInROB == 0; } 1861060SN/A 1872292SN/A /** Returns if a specific thread's partition is empty. */ 1882292SN/A bool isEmpty(unsigned tid) 1892292SN/A { return threadEntries[tid] == 0; } 1901060SN/A 1912292SN/A /** Executes the squash, marking squashed instructions. */ 1922292SN/A void doSquash(unsigned tid); 1931060SN/A 1942292SN/A /** Squashes all instructions younger than the given sequence number for 1952292SN/A * the specific thread. 1962292SN/A */ 1972292SN/A void squash(InstSeqNum squash_num, unsigned tid); 1981060SN/A 1992292SN/A /** Updates the head instruction with the new oldest instruction. */ 2002292SN/A void updateHead(); 2011060SN/A 2022292SN/A /** Updates the tail instruction with the new youngest instruction. */ 2032292SN/A void updateTail(); 2041060SN/A 2052292SN/A /** Reads the PC of the oldest head instruction. */ 2062329SN/A// uint64_t readHeadPC(); 2071060SN/A 2082292SN/A /** Reads the PC of the head instruction of a specific thread. */ 2092329SN/A// uint64_t readHeadPC(unsigned tid); 2102292SN/A 2112292SN/A /** Reads the next PC of the oldest head instruction. */ 2122329SN/A// uint64_t readHeadNextPC(); 2132107SN/A 2142292SN/A /** Reads the next PC of the head instruction of a specific thread. */ 2152329SN/A// uint64_t readHeadNextPC(unsigned tid); 2162292SN/A 2172292SN/A /** Reads the sequence number of the oldest head instruction. */ 2182329SN/A// InstSeqNum readHeadSeqNum(); 2192107SN/A 2202292SN/A /** Reads the sequence number of the head instruction of a specific thread. 2212292SN/A */ 2222329SN/A// InstSeqNum readHeadSeqNum(unsigned tid); 2232292SN/A 2242292SN/A /** Reads the PC of the youngest tail instruction. */ 2252329SN/A// uint64_t readTailPC(); 2262107SN/A 2272292SN/A /** Reads the PC of the tail instruction of a specific thread. */ 2282329SN/A// uint64_t readTailPC(unsigned tid); 2292292SN/A 2302292SN/A /** Reads the sequence number of the youngest tail instruction. */ 2312329SN/A// InstSeqNum readTailSeqNum(); 2322107SN/A 2332292SN/A /** Reads the sequence number of tail instruction of a specific thread. */ 2342329SN/A// InstSeqNum readTailSeqNum(unsigned tid); 2351060SN/A 2361060SN/A /** Checks if the ROB is still in the process of squashing instructions. 2371060SN/A * @retval Whether or not the ROB is done squashing. 2381060SN/A */ 2392292SN/A bool isDoneSquashing(unsigned tid) const 2402292SN/A { return doneSquashing[tid]; } 2412292SN/A 2422292SN/A /** Checks if the ROB is still in the process of squashing instructions for 2432292SN/A * any thread. 2442292SN/A */ 2452292SN/A bool isDoneSquashing(); 2461060SN/A 2471060SN/A /** This is more of a debugging function than anything. Use 2481060SN/A * numInstsInROB to get the instructions in the ROB unless you are 2491060SN/A * double checking that variable. 2501060SN/A */ 2511060SN/A int countInsts(); 2521060SN/A 2532292SN/A /** This is more of a debugging function than anything. Use 2542292SN/A * threadEntries to get the instructions in the ROB unless you are 2552292SN/A * double checking that variable. 2562292SN/A */ 2572292SN/A int countInsts(unsigned tid); 2582292SN/A 2591060SN/A private: 2601060SN/A /** Pointer to the CPU. */ 2612733Sktlim@umich.edu O3CPU *cpu; 2621060SN/A 2632292SN/A /** Active Threads in CPU */ 2642292SN/A std::list<unsigned>* activeThreads; 2652292SN/A 2661061SN/A /** Number of instructions in the ROB. */ 2671060SN/A unsigned numEntries; 2681060SN/A 2692292SN/A /** Entries Per Thread */ 2702292SN/A unsigned threadEntries[Impl::MaxThreads]; 2712292SN/A 2722292SN/A /** Max Insts a Thread Can Have in the ROB */ 2732292SN/A unsigned maxEntries[Impl::MaxThreads]; 2742292SN/A 2752292SN/A /** ROB List of Instructions */ 2762292SN/A std::list<DynInstPtr> instList[Impl::MaxThreads]; 2772292SN/A 2781060SN/A /** Number of instructions that can be squashed in a single cycle. */ 2791060SN/A unsigned squashWidth; 2801060SN/A 2812292SN/A public: 2821061SN/A /** Iterator pointing to the instruction which is the last instruction 2831061SN/A * in the ROB. This may at times be invalid (ie when the ROB is empty), 2841061SN/A * however it should never be incorrect. 2851061SN/A */ 2862292SN/A InstIt tail; 2871060SN/A 2882292SN/A /** Iterator pointing to the instruction which is the first instruction in 2892292SN/A * in the ROB*/ 2902292SN/A InstIt head; 2912292SN/A 2922292SN/A private: 2931061SN/A /** Iterator used for walking through the list of instructions when 2941061SN/A * squashing. Used so that there is persistent state between cycles; 2951061SN/A * when squashing, the instructions are marked as squashed but not 2961061SN/A * immediately removed, meaning the tail iterator remains the same before 2971061SN/A * and after a squash. 2981061SN/A * This will always be set to cpu->instList.end() if it is invalid. 2991061SN/A */ 3002292SN/A InstIt squashIt[Impl::MaxThreads]; 3011060SN/A 3022292SN/A public: 3031061SN/A /** Number of instructions in the ROB. */ 3041060SN/A int numInstsInROB; 3051060SN/A 3062348SN/A /** Dummy instruction returned if there are no insts left. */ 3072292SN/A DynInstPtr dummyInst; 3082292SN/A 3092292SN/A private: 3101060SN/A /** The sequence number of the squashed instruction. */ 3111060SN/A InstSeqNum squashedSeqNum; 3121060SN/A 3131060SN/A /** Is the ROB done squashing. */ 3142292SN/A bool doneSquashing[Impl::MaxThreads]; 3152292SN/A 3162292SN/A /** Number of active threads. */ 3172292SN/A unsigned numThreads; 3181060SN/A}; 3191060SN/A 3202292SN/A#endif //__CPU_O3_ROB_HH__ 321