rename_impl.hh revision 2348
12292SN/A/* 22727Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu */ 282689Sktlim@umich.edu 292292SN/A#include <list> 302292SN/A 312329SN/A#include "config/full_system.hh" 322329SN/A#include "cpu/o3/rename.hh" 332329SN/A 342292SN/Ausing namespace std; 352292SN/A 362292SN/Atemplate <class Impl> 372292SN/ADefaultRename<Impl>::DefaultRename(Params *params) 382292SN/A : iewToRenameDelay(params->iewToRenameDelay), 392292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 402292SN/A commitToRenameDelay(params->commitToRenameDelay), 412292SN/A renameWidth(params->renameWidth), 422292SN/A commitWidth(params->commitWidth), 432292SN/A numThreads(params->numberOfThreads) 442292SN/A{ 452292SN/A _status = Inactive; 462292SN/A 472292SN/A for (int i=0; i< numThreads; i++) { 482292SN/A renameStatus[i] = Idle; 492292SN/A 502292SN/A freeEntries[i].iqEntries = 0; 512292SN/A freeEntries[i].lsqEntries = 0; 522292SN/A freeEntries[i].robEntries = 0; 532292SN/A 542292SN/A stalls[i].iew = false; 552292SN/A stalls[i].commit = false; 562292SN/A serializeInst[i] = NULL; 572292SN/A 582292SN/A instsInProgress[i] = 0; 592292SN/A 602292SN/A emptyROB[i] = true; 612292SN/A 622292SN/A serializeOnNextInst[i] = false; 632292SN/A } 642292SN/A 652292SN/A // @todo: Make into a parameter. 662292SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 672292SN/A} 682292SN/A 692292SN/Atemplate <class Impl> 702292SN/Astd::string 712292SN/ADefaultRename<Impl>::name() const 722292SN/A{ 732292SN/A return cpu->name() + ".rename"; 742292SN/A} 752292SN/A 762292SN/Atemplate <class Impl> 772292SN/Avoid 782292SN/ADefaultRename<Impl>::regStats() 792292SN/A{ 802292SN/A renameSquashCycles 812292SN/A .name(name() + ".RENAME:SquashCycles") 822292SN/A .desc("Number of cycles rename is squashing") 832292SN/A .prereq(renameSquashCycles); 842292SN/A renameIdleCycles 852292SN/A .name(name() + ".RENAME:IdleCycles") 862292SN/A .desc("Number of cycles rename is idle") 872292SN/A .prereq(renameIdleCycles); 882292SN/A renameBlockCycles 892292SN/A .name(name() + ".RENAME:BlockCycles") 902292SN/A .desc("Number of cycles rename is blocking") 912292SN/A .prereq(renameBlockCycles); 922292SN/A renameSerializeStallCycles 932292SN/A .name(name() + ".RENAME:serializeStallCycles") 942292SN/A .desc("count of cycles rename stalled for serializing inst") 952292SN/A .flags(Stats::total); 962292SN/A renameRunCycles 972329SN/A .name(name() + ".RENAME:RunCycles") 982292SN/A .desc("Number of cycles rename is running") 992292SN/A .prereq(renameIdleCycles); 1002292SN/A renameUnblockCycles 1012292SN/A .name(name() + ".RENAME:UnblockCycles") 1022292SN/A .desc("Number of cycles rename is unblocking") 1032292SN/A .prereq(renameUnblockCycles); 1042292SN/A renameRenamedInsts 1052292SN/A .name(name() + ".RENAME:RenamedInsts") 1062292SN/A .desc("Number of instructions processed by rename") 1072292SN/A .prereq(renameRenamedInsts); 1082292SN/A renameSquashedInsts 1092292SN/A .name(name() + ".RENAME:SquashedInsts") 1102292SN/A .desc("Number of squashed instructions processed by rename") 1112727Sktlim@umich.edu .prereq(renameSquashedInsts); 1122727Sktlim@umich.edu renameROBFullEvents 1132727Sktlim@umich.edu .name(name() + ".RENAME:ROBFullEvents") 1142727Sktlim@umich.edu .desc("Number of times rename has blocked due to ROB full") 1152727Sktlim@umich.edu .prereq(renameROBFullEvents); 1162727Sktlim@umich.edu renameIQFullEvents 1172727Sktlim@umich.edu .name(name() + ".RENAME:IQFullEvents") 1182727Sktlim@umich.edu .desc("Number of times rename has blocked due to IQ full") 1192727Sktlim@umich.edu .prereq(renameIQFullEvents); 1202727Sktlim@umich.edu renameLSQFullEvents 1212292SN/A .name(name() + ".RENAME:LSQFullEvents") 1222292SN/A .desc("Number of times rename has blocked due to LSQ full") 1232292SN/A .prereq(renameLSQFullEvents); 1242292SN/A renameFullRegistersEvents 1252292SN/A .name(name() + ".RENAME:FullRegisterEvents") 1262292SN/A .desc("Number of times there has been no free registers") 1272292SN/A .prereq(renameFullRegistersEvents); 1282292SN/A renameRenamedOperands 1292733Sktlim@umich.edu .name(name() + ".RENAME:RenamedOperands") 1302292SN/A .desc("Number of destination operands rename has renamed") 1312292SN/A .prereq(renameRenamedOperands); 1322292SN/A renameRenameLookups 1332292SN/A .name(name() + ".RENAME:RenameLookups") 1342292SN/A .desc("Number of register rename lookups that rename has made") 1352292SN/A .prereq(renameRenameLookups); 1362292SN/A renameCommittedMaps 1372292SN/A .name(name() + ".RENAME:CommittedMaps") 1382292SN/A .desc("Number of HB maps that are committed") 1392292SN/A .prereq(renameCommittedMaps); 1402292SN/A renameUndoneMaps 1412292SN/A .name(name() + ".RENAME:UndoneMaps") 1422292SN/A .desc("Number of HB maps that are undone due to squashing") 1432292SN/A .prereq(renameUndoneMaps); 1442292SN/A renamedSerializing 1452292SN/A .name(name() + ".RENAME:serializingInsts") 1462292SN/A .desc("count of serializing insts renamed") 1472292SN/A .flags(Stats::total) 1482292SN/A ; 1492292SN/A renamedTempSerializing 1502307SN/A .name(name() + ".RENAME:tempSerializingInsts") 1512307SN/A .desc("count of temporary serializing insts renamed") 1522307SN/A .flags(Stats::total) 1532307SN/A ; 1542307SN/A renameSkidInsts 1552307SN/A .name(name() + ".RENAME:skidInsts") 1562307SN/A .desc("count of insts added to the skid buffer") 1572307SN/A .flags(Stats::total) 1582307SN/A ; 1592307SN/A} 1602307SN/A 1612307SN/Atemplate <class Impl> 1622307SN/Avoid 1632307SN/ADefaultRename<Impl>::setCPU(FullCPU *cpu_ptr) 1642307SN/A{ 1652307SN/A DPRINTF(Rename, "Setting CPU pointer.\n"); 1662307SN/A cpu = cpu_ptr; 1672307SN/A} 1682292SN/A 1692292SN/Atemplate <class Impl> 1702292SN/Avoid 1712292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1722292SN/A{ 1732292SN/A DPRINTF(Rename, "Setting time buffer pointer.\n"); 1742292SN/A timeBuffer = tb_ptr; 1752292SN/A 1762292SN/A // Setup wire to read information from time buffer, from IEW stage. 1772292SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1782292SN/A 1792292SN/A // Setup wire to read infromation from time buffer, from commit stage. 1802292SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1812292SN/A 1822292SN/A // Setup wire to write information to previous stages. 1832292SN/A toDecode = timeBuffer->getWire(0); 1842292SN/A} 1852292SN/A 1862292SN/Atemplate <class Impl> 1872292SN/Avoid 1882292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1892292SN/A{ 1902292SN/A DPRINTF(Rename, "Setting rename queue pointer.\n"); 1912292SN/A renameQueue = rq_ptr; 1922292SN/A 1932292SN/A // Setup wire to write information to future stages. 1942292SN/A toIEW = renameQueue->getWire(0); 1952292SN/A} 1962292SN/A 1972292SN/Atemplate <class Impl> 1982292SN/Avoid 1992292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2002292SN/A{ 2012292SN/A DPRINTF(Rename, "Setting decode queue pointer.\n"); 2022292SN/A decodeQueue = dq_ptr; 2032292SN/A 2042292SN/A // Setup wire to get information from decode. 2052292SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2062292SN/A} 2072292SN/A 2082292SN/Atemplate <class Impl> 2092292SN/Avoid 2102292SN/ADefaultRename<Impl>::initStage() 2112292SN/A{ 2122292SN/A // Grab the number of free entries directly from the stages. 2132292SN/A for (int tid=0; tid < numThreads; tid++) { 2142292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2152292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2162292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2172292SN/A emptyROB[tid] = true; 2182292SN/A } 2192292SN/A} 2202292SN/A 2212292SN/Atemplate<class Impl> 2222292SN/Avoid 2232292SN/ADefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr) 2242292SN/A{ 2252292SN/A DPRINTF(Rename, "Setting active threads list pointer.\n"); 2262292SN/A activeThreads = at_ptr; 2272292SN/A} 2282292SN/A 2292292SN/A 2302292SN/Atemplate <class Impl> 2312292SN/Avoid 2322292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2332292SN/A{ 2342292SN/A DPRINTF(Rename, "Setting rename map pointers.\n"); 2352292SN/A 2362292SN/A for (int i=0; i<numThreads; i++) { 2372292SN/A renameMap[i] = &rm_ptr[i]; 2382292SN/A } 2392292SN/A} 2402292SN/A 2412292SN/Atemplate <class Impl> 2422292SN/Avoid 2432292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2442292SN/A{ 2452292SN/A DPRINTF(Rename, "Setting free list pointer.\n"); 2462292SN/A freeList = fl_ptr; 2472292SN/A} 2482292SN/A 2492292SN/Atemplate<class Impl> 2502292SN/Avoid 2512292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2522292SN/A{ 2532292SN/A DPRINTF(Rename, "Setting scoreboard pointer.\n"); 2542292SN/A scoreboard = _scoreboard; 2552292SN/A} 2562292SN/A 2572292SN/Atemplate <class Impl> 2582292SN/Avoid 2592292SN/ADefaultRename<Impl>::switchOut() 2602292SN/A{ 2612292SN/A // Rename is ready to switch out at any time. 2622292SN/A cpu->signalSwitched(); 2632292SN/A} 2642292SN/A 2652292SN/Atemplate <class Impl> 2662292SN/Avoid 2672292SN/ADefaultRename<Impl>::doSwitchOut() 2682292SN/A{ 2692292SN/A // Clear any state, fix up the rename map. 2702292SN/A for (int i = 0; i < numThreads; i++) { 2712292SN/A typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin(); 2722292SN/A 2732292SN/A while (!historyBuffer[i].empty()) { 2742292SN/A assert(hb_it != historyBuffer[i].end()); 2752292SN/A 2762292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2772292SN/A "number %i.\n", i, (*hb_it).instSeqNum); 2782292SN/A 2792329SN/A // Tell the rename map to set the architected register to the 2802329SN/A // previous physical register that it was renamed to. 2812292SN/A renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2822292SN/A 2832292SN/A // Put the renamed physical register back on the free list. 2842292SN/A freeList->addReg(hb_it->newPhysReg); 2852292SN/A 2862292SN/A historyBuffer[i].erase(hb_it++); 2872292SN/A } 2882292SN/A insts[i].clear(); 2892292SN/A skidBuffer[i].clear(); 2902292SN/A } 2912292SN/A} 2922292SN/A 2932292SN/Atemplate <class Impl> 2942292SN/Avoid 2952292SN/ADefaultRename<Impl>::takeOverFrom() 2962292SN/A{ 2972292SN/A _status = Inactive; 2982292SN/A initStage(); 2992292SN/A 3002292SN/A // Reset all state prior to taking over from the other CPU. 3012292SN/A for (int i=0; i< numThreads; i++) { 3022292SN/A renameStatus[i] = Idle; 3032292SN/A 3042292SN/A stalls[i].iew = false; 3052292SN/A stalls[i].commit = false; 3062292SN/A serializeInst[i] = NULL; 3072292SN/A 3082292SN/A instsInProgress[i] = 0; 3092292SN/A 3102292SN/A emptyROB[i] = true; 3112292SN/A 3122292SN/A serializeOnNextInst[i] = false; 3132292SN/A } 3142292SN/A} 3152292SN/A 3162292SN/Atemplate <class Impl> 3172292SN/Avoid 3182292SN/ADefaultRename<Impl>::squash(unsigned tid) 3192292SN/A{ 3202292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3212292SN/A 3222292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3232292SN/A // If it still needs to block, the blocking should happen the next 3242292SN/A // cycle and there should be space to hold everything due to the squash. 3252292SN/A if (renameStatus[tid] == Blocked || 3262292SN/A renameStatus[tid] == Unblocking || 3272292SN/A renameStatus[tid] == SerializeStall) { 3282292SN/A#if 0 3292292SN/A // In syscall emulation, we can have both a block and a squash due 3302292SN/A // to a syscall in the same cycle. This would cause both signals to 3312292SN/A // be high. This shouldn't happen in full system. 3322292SN/A if (toDecode->renameBlock[tid]) { 3332292SN/A toDecode->renameBlock[tid] = 0; 3342292SN/A } else { 3352292SN/A toDecode->renameUnblock[tid] = 1; 3362292SN/A } 3372292SN/A#else 3382292SN/A toDecode->renameUnblock[tid] = 1; 3392292SN/A#endif 3402292SN/A serializeInst[tid] = NULL; 3412292SN/A } 3422292SN/A 3432292SN/A // Set the status to Squashing. 3442292SN/A renameStatus[tid] = Squashing; 3452292SN/A 3462292SN/A // Squash any instructions from decode. 3472292SN/A unsigned squashCount = 0; 3482292SN/A 3492292SN/A for (int i=0; i<fromDecode->size; i++) { 3502292SN/A if (fromDecode->insts[i]->threadNumber == tid) { 3512292SN/A fromDecode->insts[i]->squashed = true; 3522292SN/A wroteToTimeBuffer = true; 3532292SN/A squashCount++; 3542292SN/A } 3552292SN/A } 3562292SN/A 3572292SN/A insts[tid].clear(); 3582292SN/A 3592292SN/A // Clear the skid buffer in case it has any data in it. 3602292SN/A skidBuffer[tid].clear(); 3612292SN/A 3622292SN/A doSquash(tid); 3632292SN/A} 3642292SN/A 3652292SN/Atemplate <class Impl> 3662292SN/Avoid 3672292SN/ADefaultRename<Impl>::tick() 3682292SN/A{ 3692292SN/A wroteToTimeBuffer = false; 3702292SN/A 3712292SN/A blockThisCycle = false; 3722292SN/A 3732292SN/A bool status_change = false; 3742292SN/A 3752292SN/A toIEWIndex = 0; 3762292SN/A 3772292SN/A sortInsts(); 3782292SN/A 3792292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 3802292SN/A 3812292SN/A // Check stall and squash signals. 3822292SN/A while (threads != (*activeThreads).end()) { 3832292SN/A unsigned tid = *threads++; 3842292SN/A 3852292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3862292SN/A 3872292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 3882292SN/A 3892292SN/A rename(status_change, tid); 3902292SN/A } 3912292SN/A 3922292SN/A if (status_change) { 3932292SN/A updateStatus(); 3942292SN/A } 3952292SN/A 3962292SN/A if (wroteToTimeBuffer) { 3972292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 3982292SN/A cpu->activityThisCycle(); 3992292SN/A } 4002292SN/A 4012292SN/A threads = (*activeThreads).begin(); 4022292SN/A 4032292SN/A while (threads != (*activeThreads).end()) { 4042292SN/A unsigned tid = *threads++; 4052292SN/A 4062292SN/A // If we committed this cycle then doneSeqNum will be > 0 4072292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4082292SN/A !fromCommit->commitInfo[tid].squash && 4092292SN/A renameStatus[tid] != Squashing) { 4102292SN/A 4112292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4122292SN/A tid); 4132292SN/A } 4142292SN/A } 4152292SN/A 4162292SN/A // @todo: make into updateProgress function 4172292SN/A for (int tid=0; tid < numThreads; tid++) { 4182292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4192292SN/A 4202292SN/A assert(instsInProgress[tid] >=0); 4212292SN/A } 4222292SN/A 4232292SN/A} 4242292SN/A 4252292SN/Atemplate<class Impl> 4262292SN/Avoid 4272292SN/ADefaultRename<Impl>::rename(bool &status_change, unsigned tid) 4282292SN/A{ 4292292SN/A // If status is Running or idle, 4302292SN/A // call renameInsts() 4312292SN/A // If status is Unblocking, 4322292SN/A // buffer any instructions coming from decode 4332292SN/A // continue trying to empty skid buffer 4342292SN/A // check if stall conditions have passed 4352292SN/A 4362292SN/A if (renameStatus[tid] == Blocked) { 4372292SN/A ++renameBlockCycles; 4382292SN/A } else if (renameStatus[tid] == Squashing) { 4392292SN/A ++renameSquashCycles; 4402292SN/A } else if (renameStatus[tid] == SerializeStall) { 4412292SN/A ++renameSerializeStallCycles; 4422292SN/A } 4432292SN/A 4442292SN/A if (renameStatus[tid] == Running || 4452292SN/A renameStatus[tid] == Idle) { 4462292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4472292SN/A "stage.\n", tid); 4482292SN/A 4492292SN/A renameInsts(tid); 4502292SN/A } else if (renameStatus[tid] == Unblocking) { 4512292SN/A renameInsts(tid); 4522292SN/A 4532292SN/A if (validInsts()) { 4542292SN/A // Add the current inputs to the skid buffer so they can be 4552292SN/A // reprocessed when this stage unblocks. 4562292SN/A skidInsert(tid); 4572292SN/A } 4582292SN/A 4592292SN/A // If we switched over to blocking, then there's a potential for 4602292SN/A // an overall status change. 4612292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4622292SN/A } 4632292SN/A} 4642292SN/A 4652292SN/Atemplate <class Impl> 4662292SN/Avoid 4672292SN/ADefaultRename<Impl>::renameInsts(unsigned tid) 4682292SN/A{ 4692292SN/A // Instructions can be either in the skid buffer or the queue of 4702292SN/A // instructions coming from decode, depending on the status. 4712292SN/A int insts_available = renameStatus[tid] == Unblocking ? 4722292SN/A skidBuffer[tid].size() : insts[tid].size(); 4732292SN/A 4742292SN/A // Check the decode queue to see if instructions are available. 4752292SN/A // If there are no available instructions to rename, then do nothing. 4762292SN/A if (insts_available == 0) { 4772292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4782292SN/A tid); 4792292SN/A // Should I change status to idle? 4802292SN/A ++renameIdleCycles; 4812292SN/A return; 4822292SN/A } else if (renameStatus[tid] == Unblocking) { 4832292SN/A ++renameUnblockCycles; 4842292SN/A } else if (renameStatus[tid] == Running) { 4852292SN/A ++renameRunCycles; 4862292SN/A } 4872292SN/A 4882292SN/A DynInstPtr inst; 4892292SN/A 4902292SN/A // Will have to do a different calculation for the number of free 4912292SN/A // entries. 4922292SN/A int free_rob_entries = calcFreeROBEntries(tid); 4932292SN/A int free_iq_entries = calcFreeIQEntries(tid); 4942292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 4952292SN/A int min_free_entries = free_rob_entries; 4962292SN/A 4972292SN/A FullSource source = ROB; 4982292SN/A 4992292SN/A if (free_iq_entries < min_free_entries) { 5002292SN/A min_free_entries = free_iq_entries; 5012292SN/A source = IQ; 5022292SN/A } 5032292SN/A 5042292SN/A if (free_lsq_entries < min_free_entries) { 5052292SN/A min_free_entries = free_lsq_entries; 5062292SN/A source = LSQ; 5072292SN/A } 5082292SN/A 5092292SN/A // Check if there's any space left. 5102292SN/A if (min_free_entries <= 0) { 5112292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5122292SN/A "entries.\n" 5132292SN/A "ROB has %i free entries.\n" 5142292SN/A "IQ has %i free entries.\n" 5152292SN/A "LSQ has %i free entries.\n", 5162292SN/A tid, 5172292SN/A free_rob_entries, 5182292SN/A free_iq_entries, 5192292SN/A free_lsq_entries); 5202292SN/A 5212292SN/A blockThisCycle = true; 5222292SN/A 5232292SN/A block(tid); 5242292SN/A 5252292SN/A incrFullStat(source); 5262292SN/A 5272292SN/A return; 5282292SN/A } else if (min_free_entries < insts_available) { 5292292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5302292SN/A "%i insts available, but only %i insts can be " 5312292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5322292SN/A tid, insts_available, min_free_entries); 5332292SN/A 5342292SN/A insts_available = min_free_entries; 5352292SN/A 5362292SN/A blockThisCycle = true; 5372292SN/A 5382292SN/A incrFullStat(source); 5392292SN/A } 540 541 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 542 skidBuffer[tid] : insts[tid]; 543 544 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 545 "send iew.\n", tid, insts_available); 546 547 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 548 "dispatched to IQ last cycle.\n", 549 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 550 551 // Handle serializing the next instruction if necessary. 552 if (serializeOnNextInst[tid]) { 553 if (emptyROB[tid] && instsInProgress[tid] == 0) { 554 // ROB already empty; no need to serialize. 555 serializeOnNextInst[tid] = false; 556 } else if (!insts_to_rename.empty()) { 557 insts_to_rename.front()->setSerializeBefore(); 558 } 559 } 560 561 int renamed_insts = 0; 562 563 while (insts_available > 0 && toIEWIndex < renameWidth) { 564 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 565 566 assert(!insts_to_rename.empty()); 567 568 inst = insts_to_rename.front(); 569 570 insts_to_rename.pop_front(); 571 572 if (renameStatus[tid] == Unblocking) { 573 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 574 "skidBuffer\n", 575 tid, inst->seqNum, inst->readPC()); 576 } 577 578 if (inst->isSquashed()) { 579 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 580 "squashed, skipping.\n", 581 tid, inst->seqNum, inst->threadNumber,inst->readPC()); 582 583 ++renameSquashedInsts; 584 585 // Decrement how many instructions are available. 586 --insts_available; 587 588 continue; 589 } 590 591 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 592 "PC %#x.\n", 593 tid, inst->seqNum, inst->readPC()); 594 595 // Handle serializeAfter/serializeBefore instructions. 596 // serializeAfter marks the next instruction as serializeBefore. 597 // serializeBefore makes the instruction wait in rename until the ROB 598 // is empty. 599 600 // In this model, IPR accesses are serialize before 601 // instructions, and store conditionals are serialize after 602 // instructions. This is mainly due to lack of support for 603 // out-of-order operations of either of those classes of 604 // instructions. 605 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 606 !inst->isSerializeHandled()) { 607 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 608 609 if (!inst->isTempSerializeBefore()) { 610 renamedSerializing++; 611 inst->setSerializeHandled(); 612 } else { 613 renamedTempSerializing++; 614 } 615 616 // Change status over to SerializeStall so that other stages know 617 // what this is blocked on. 618 renameStatus[tid] = SerializeStall; 619 620 serializeInst[tid] = inst; 621 622 blockThisCycle = true; 623 624 break; 625 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 626 !inst->isSerializeHandled()) { 627 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 628 629 renamedSerializing++; 630 631 inst->setSerializeHandled(); 632 633 serializeAfter(insts_to_rename, tid); 634 } 635 636 // Check here to make sure there are enough destination registers 637 // to rename to. Otherwise block. 638 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 639 DPRINTF(Rename, "Blocking due to lack of free " 640 "physical registers to rename to.\n"); 641 blockThisCycle = true; 642 643 ++renameFullRegistersEvents; 644 645 break; 646 } 647 648 renameSrcRegs(inst, inst->threadNumber); 649 650 renameDestRegs(inst, inst->threadNumber); 651 652 ++renamed_insts; 653 654 // Put instruction in rename queue. 655 toIEW->insts[toIEWIndex] = inst; 656 ++(toIEW->size); 657 658 // Increment which instruction we're on. 659 ++toIEWIndex; 660 661 // Decrement how many instructions are available. 662 --insts_available; 663 } 664 665 instsInProgress[tid] += renamed_insts; 666 renameRenamedInsts += renamed_insts; 667 668 // If we wrote to the time buffer, record this. 669 if (toIEWIndex) { 670 wroteToTimeBuffer = true; 671 } 672 673 // Check if there's any instructions left that haven't yet been renamed. 674 // If so then block. 675 if (insts_available) { 676 blockThisCycle = true; 677 } 678 679 if (blockThisCycle) { 680 block(tid); 681 toDecode->renameUnblock[tid] = false; 682 } 683} 684 685template<class Impl> 686void 687DefaultRename<Impl>::skidInsert(unsigned tid) 688{ 689 DynInstPtr inst = NULL; 690 691 while (!insts[tid].empty()) { 692 inst = insts[tid].front(); 693 694 insts[tid].pop_front(); 695 696 assert(tid == inst->threadNumber); 697 698 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 699 "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 700 701 ++renameSkidInsts; 702 703 skidBuffer[tid].push_back(inst); 704 } 705 706 if (skidBuffer[tid].size() > skidBufferMax) 707 panic("Skidbuffer Exceeded Max Size"); 708} 709 710template <class Impl> 711void 712DefaultRename<Impl>::sortInsts() 713{ 714 int insts_from_decode = fromDecode->size; 715#ifdef DEBUG 716 for (int i=0; i < numThreads; i++) 717 assert(insts[i].empty()); 718#endif 719 for (int i = 0; i < insts_from_decode; ++i) { 720 DynInstPtr inst = fromDecode->insts[i]; 721 insts[inst->threadNumber].push_back(inst); 722 } 723} 724 725template<class Impl> 726bool 727DefaultRename<Impl>::skidsEmpty() 728{ 729 list<unsigned>::iterator threads = (*activeThreads).begin(); 730 731 while (threads != (*activeThreads).end()) { 732 if (!skidBuffer[*threads++].empty()) 733 return false; 734 } 735 736 return true; 737} 738 739template<class Impl> 740void 741DefaultRename<Impl>::updateStatus() 742{ 743 bool any_unblocking = false; 744 745 list<unsigned>::iterator threads = (*activeThreads).begin(); 746 747 threads = (*activeThreads).begin(); 748 749 while (threads != (*activeThreads).end()) { 750 unsigned tid = *threads++; 751 752 if (renameStatus[tid] == Unblocking) { 753 any_unblocking = true; 754 break; 755 } 756 } 757 758 // Rename will have activity if it's unblocking. 759 if (any_unblocking) { 760 if (_status == Inactive) { 761 _status = Active; 762 763 DPRINTF(Activity, "Activating stage.\n"); 764 765 cpu->activateStage(FullCPU::RenameIdx); 766 } 767 } else { 768 // If it's not unblocking, then rename will not have any internal 769 // activity. Switch it to inactive. 770 if (_status == Active) { 771 _status = Inactive; 772 DPRINTF(Activity, "Deactivating stage.\n"); 773 774 cpu->deactivateStage(FullCPU::RenameIdx); 775 } 776 } 777} 778 779template <class Impl> 780bool 781DefaultRename<Impl>::block(unsigned tid) 782{ 783 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 784 785 // Add the current inputs onto the skid buffer, so they can be 786 // reprocessed when this stage unblocks. 787 skidInsert(tid); 788 789 // Only signal backwards to block if the previous stages do not think 790 // rename is already blocked. 791 if (renameStatus[tid] != Blocked) { 792 if (renameStatus[tid] != Unblocking) { 793 toDecode->renameBlock[tid] = true; 794 toDecode->renameUnblock[tid] = false; 795 wroteToTimeBuffer = true; 796 } 797 798 // Rename can not go from SerializeStall to Blocked, otherwise 799 // it would not know to complete the serialize stall. 800 if (renameStatus[tid] != SerializeStall) { 801 // Set status to Blocked. 802 renameStatus[tid] = Blocked; 803 return true; 804 } 805 } 806 807 return false; 808} 809 810template <class Impl> 811bool 812DefaultRename<Impl>::unblock(unsigned tid) 813{ 814 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 815 816 // Rename is done unblocking if the skid buffer is empty. 817 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 818 819 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 820 821 toDecode->renameUnblock[tid] = true; 822 wroteToTimeBuffer = true; 823 824 renameStatus[tid] = Running; 825 return true; 826 } 827 828 return false; 829} 830 831template <class Impl> 832void 833DefaultRename<Impl>::doSquash(unsigned tid) 834{ 835 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin(); 836 837 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 838 839 // After a syscall squashes everything, the history buffer may be empty 840 // but the ROB may still be squashing instructions. 841 if (historyBuffer[tid].empty()) { 842 return; 843 } 844 845 // Go through the most recent instructions, undoing the mappings 846 // they did and freeing up the registers. 847 while (!historyBuffer[tid].empty() && 848 (*hb_it).instSeqNum > squashed_seq_num) { 849 assert(hb_it != historyBuffer[tid].end()); 850 851 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 852 "number %i.\n", tid, (*hb_it).instSeqNum); 853 854 // Tell the rename map to set the architected register to the 855 // previous physical register that it was renamed to. 856 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 857 858 // Put the renamed physical register back on the free list. 859 freeList->addReg(hb_it->newPhysReg); 860 861 historyBuffer[tid].erase(hb_it++); 862 863 ++renameUndoneMaps; 864 } 865} 866 867template<class Impl> 868void 869DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 870{ 871 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 872 "history buffer %u (size=%i), until [sn:%lli].\n", 873 tid, tid, historyBuffer[tid].size(), inst_seq_num); 874 875 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end(); 876 877 --hb_it; 878 879 if (historyBuffer[tid].empty()) { 880 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 881 return; 882 } else if (hb_it->instSeqNum > inst_seq_num) { 883 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 884 "that a syscall happened recently.\n", tid); 885 return; 886 } 887 888 // Commit all the renames up until (and including) the committed sequence 889 // number. Some or even all of the committed instructions may not have 890 // rename histories if they did not have destination registers that were 891 // renamed. 892 while (!historyBuffer[tid].empty() && 893 hb_it != historyBuffer[tid].end() && 894 (*hb_it).instSeqNum <= inst_seq_num) { 895 896 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 897 "[sn:%lli].\n", 898 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 899 900 freeList->addReg((*hb_it).prevPhysReg); 901 ++renameCommittedMaps; 902 903 historyBuffer[tid].erase(hb_it--); 904 } 905} 906 907template <class Impl> 908inline void 909DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 910{ 911 assert(renameMap[tid] != 0); 912 913 unsigned num_src_regs = inst->numSrcRegs(); 914 915 // Get the architectual register numbers from the source and 916 // destination operands, and redirect them to the right register. 917 // Will need to mark dependencies though. 918 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 919 RegIndex src_reg = inst->srcRegIdx(src_idx); 920 921 // Look up the source registers to get the phys. register they've 922 // been renamed to, and set the sources to those registers. 923 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg); 924 925 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 926 "physical reg %i.\n", tid, (int)src_reg, 927 (int)renamed_reg); 928 929 inst->renameSrcReg(src_idx, renamed_reg); 930 931 // See if the register is ready or not. 932 if (scoreboard->getReg(renamed_reg) == true) { 933 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 934 935 inst->markSrcRegReady(src_idx); 936 } 937 938 ++renameRenameLookups; 939 } 940} 941 942template <class Impl> 943inline void 944DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 945{ 946 typename RenameMap::RenameInfo rename_result; 947 948 unsigned num_dest_regs = inst->numDestRegs(); 949 950 // Rename the destination registers. 951 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 952 RegIndex dest_reg = inst->destRegIdx(dest_idx); 953 954 // Get the physical register that the destination will be 955 // renamed to. 956 rename_result = renameMap[tid]->rename(dest_reg); 957 958 //Mark Scoreboard entry as not ready 959 scoreboard->unsetReg(rename_result.first); 960 961 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 962 "reg %i.\n", tid, (int)dest_reg, 963 (int)rename_result.first); 964 965 // Record the rename information so that a history can be kept. 966 RenameHistory hb_entry(inst->seqNum, dest_reg, 967 rename_result.first, 968 rename_result.second); 969 970 historyBuffer[tid].push_front(hb_entry); 971 972 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, " 973 "[sn:%lli].\n",tid, 974 (*historyBuffer[tid].begin()).instSeqNum); 975 976 // Tell the instruction to rename the appropriate destination 977 // register (dest_idx) to the new physical register 978 // (rename_result.first), and record the previous physical 979 // register that the same logical register was renamed to 980 // (rename_result.second). 981 inst->renameDestReg(dest_idx, 982 rename_result.first, 983 rename_result.second); 984 985 ++renameRenamedOperands; 986 } 987} 988 989template <class Impl> 990inline int 991DefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 992{ 993 int num_free = freeEntries[tid].robEntries - 994 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 995 996 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 997 998 return num_free; 999} 1000 1001template <class Impl> 1002inline int 1003DefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 1004{ 1005 int num_free = freeEntries[tid].iqEntries - 1006 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1007 1008 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1009 1010 return num_free; 1011} 1012 1013template <class Impl> 1014inline int 1015DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 1016{ 1017 int num_free = freeEntries[tid].lsqEntries - 1018 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1019 1020 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1021 1022 return num_free; 1023} 1024 1025template <class Impl> 1026unsigned 1027DefaultRename<Impl>::validInsts() 1028{ 1029 unsigned inst_count = 0; 1030 1031 for (int i=0; i<fromDecode->size; i++) { 1032 if (!fromDecode->insts[i]->squashed) 1033 inst_count++; 1034 } 1035 1036 return inst_count; 1037} 1038 1039template <class Impl> 1040void 1041DefaultRename<Impl>::readStallSignals(unsigned tid) 1042{ 1043 if (fromIEW->iewBlock[tid]) { 1044 stalls[tid].iew = true; 1045 } 1046 1047 if (fromIEW->iewUnblock[tid]) { 1048 assert(stalls[tid].iew); 1049 stalls[tid].iew = false; 1050 } 1051 1052 if (fromCommit->commitBlock[tid]) { 1053 stalls[tid].commit = true; 1054 } 1055 1056 if (fromCommit->commitUnblock[tid]) { 1057 assert(stalls[tid].commit); 1058 stalls[tid].commit = false; 1059 } 1060} 1061 1062template <class Impl> 1063bool 1064DefaultRename<Impl>::checkStall(unsigned tid) 1065{ 1066 bool ret_val = false; 1067 1068 if (stalls[tid].iew) { 1069 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1070 ret_val = true; 1071 } else if (stalls[tid].commit) { 1072 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1073 ret_val = true; 1074 } else if (calcFreeROBEntries(tid) <= 0) { 1075 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1076 ret_val = true; 1077 } else if (calcFreeIQEntries(tid) <= 0) { 1078 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1079 ret_val = true; 1080 } else if (calcFreeLSQEntries(tid) <= 0) { 1081 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1082 ret_val = true; 1083 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1084 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1085 ret_val = true; 1086 } else if (renameStatus[tid] == SerializeStall && 1087 (!emptyROB[tid] || instsInProgress[tid])) { 1088 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1089 "empty.\n", 1090 tid); 1091 ret_val = true; 1092 } 1093 1094 return ret_val; 1095} 1096 1097template <class Impl> 1098void 1099DefaultRename<Impl>::readFreeEntries(unsigned tid) 1100{ 1101 bool updated = false; 1102 if (fromIEW->iewInfo[tid].usedIQ) { 1103 freeEntries[tid].iqEntries = 1104 fromIEW->iewInfo[tid].freeIQEntries; 1105 updated = true; 1106 } 1107 1108 if (fromIEW->iewInfo[tid].usedLSQ) { 1109 freeEntries[tid].lsqEntries = 1110 fromIEW->iewInfo[tid].freeLSQEntries; 1111 updated = true; 1112 } 1113 1114 if (fromCommit->commitInfo[tid].usedROB) { 1115 freeEntries[tid].robEntries = 1116 fromCommit->commitInfo[tid].freeROBEntries; 1117 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1118 updated = true; 1119 } 1120 1121 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1122 tid, 1123 freeEntries[tid].iqEntries, 1124 freeEntries[tid].robEntries, 1125 freeEntries[tid].lsqEntries); 1126 1127 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1128 tid, instsInProgress[tid]); 1129} 1130 1131template <class Impl> 1132bool 1133DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 1134{ 1135 // Check if there's a squash signal, squash if there is 1136 // Check stall signals, block if necessary. 1137 // If status was blocked 1138 // check if stall conditions have passed 1139 // if so then go to unblocking 1140 // If status was Squashing 1141 // check if squashing is not high. Switch to running this cycle. 1142 // If status was serialize stall 1143 // check if ROB is empty and no insts are in flight to the ROB 1144 1145 readFreeEntries(tid); 1146 readStallSignals(tid); 1147 1148 if (fromCommit->commitInfo[tid].squash) { 1149 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1150 "commit.\n", tid); 1151 1152 squash(tid); 1153 1154 return true; 1155 } 1156 1157 if (fromCommit->commitInfo[tid].robSquashing) { 1158 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1159 1160 renameStatus[tid] = Squashing; 1161 1162 return true; 1163 } 1164 1165 if (checkStall(tid)) { 1166 return block(tid); 1167 } 1168 1169 if (renameStatus[tid] == Blocked) { 1170 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1171 tid); 1172 1173 renameStatus[tid] = Unblocking; 1174 1175 unblock(tid); 1176 1177 return true; 1178 } 1179 1180 if (renameStatus[tid] == Squashing) { 1181 // Switch status to running if rename isn't being told to block or 1182 // squash this cycle. 1183 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1184 tid); 1185 1186 renameStatus[tid] = Running; 1187 1188 return false; 1189 } 1190 1191 if (renameStatus[tid] == SerializeStall) { 1192 // Stall ends once the ROB is free. 1193 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1194 "unblocking.\n", tid); 1195 1196 DynInstPtr serial_inst = serializeInst[tid]; 1197 1198 renameStatus[tid] = Unblocking; 1199 1200 unblock(tid); 1201 1202 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1203 "PC %#x.\n", 1204 tid, serial_inst->seqNum, serial_inst->readPC()); 1205 1206 // Put instruction into queue here. 1207 serial_inst->clearSerializeBefore(); 1208 1209 if (!skidBuffer[tid].empty()) { 1210 skidBuffer[tid].push_front(serial_inst); 1211 } else { 1212 insts[tid].push_front(serial_inst); 1213 } 1214 1215 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1216 " Adding to front of list.", tid); 1217 1218 serializeInst[tid] = NULL; 1219 1220 return true; 1221 } 1222 1223 // If we've reached this point, we have not gotten any signals that 1224 // cause rename to change its status. Rename remains the same as before. 1225 return false; 1226} 1227 1228template<class Impl> 1229void 1230DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 1231 unsigned tid) 1232{ 1233 if (inst_list.empty()) { 1234 // Mark a bit to say that I must serialize on the next instruction. 1235 serializeOnNextInst[tid] = true; 1236 return; 1237 } 1238 1239 // Set the next instruction as serializing. 1240 inst_list.front()->setSerializeBefore(); 1241} 1242 1243template <class Impl> 1244inline void 1245DefaultRename<Impl>::incrFullStat(const FullSource &source) 1246{ 1247 switch (source) { 1248 case ROB: 1249 ++renameROBFullEvents; 1250 break; 1251 case IQ: 1252 ++renameIQFullEvents; 1253 break; 1254 case LSQ: 1255 ++renameLSQFullEvents; 1256 break; 1257 default: 1258 panic("Rename full stall stat should be incremented for a reason!"); 1259 break; 1260 } 1261} 1262 1263template <class Impl> 1264void 1265DefaultRename<Impl>::dumpHistory() 1266{ 1267 typename list<RenameHistory>::iterator buf_it; 1268 1269 for (int i = 0; i < numThreads; i++) { 1270 1271 buf_it = historyBuffer[i].begin(); 1272 1273 while (buf_it != historyBuffer[i].end()) { 1274 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1275 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1276 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1277 1278 buf_it++; 1279 } 1280 } 1281} 1282