rename_impl.hh revision 2348
12623SN/A/* 22623SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292623SN/A#include <list> 302623SN/A 313170Sstever@eecs.umich.edu#include "config/full_system.hh" 328105Sgblack@eecs.umich.edu#include "cpu/o3/rename.hh" 332623SN/A 344040Ssaidi@eecs.umich.eduusing namespace std; 356658Snate@binkert.org 368229Snate@binkert.orgtemplate <class Impl> 372623SN/ADefaultRename<Impl>::DefaultRename(Params *params) 388232Snate@binkert.org : iewToRenameDelay(params->iewToRenameDelay), 398232Snate@binkert.org decodeToRenameDelay(params->decodeToRenameDelay), 403348Sbinkertn@umich.edu commitToRenameDelay(params->commitToRenameDelay), 413348Sbinkertn@umich.edu renameWidth(params->renameWidth), 424762Snate@binkert.org commitWidth(params->commitWidth), 437678Sgblack@eecs.umich.edu numThreads(params->numberOfThreads) 442901Ssaidi@eecs.umich.edu{ 458779Sgblack@eecs.umich.edu _status = Inactive; 462623SN/A 472623SN/A for (int i=0; i< numThreads; i++) { 482623SN/A renameStatus[i] = Idle; 492623SN/A 502623SN/A freeEntries[i].iqEntries = 0; 515606Snate@binkert.org freeEntries[i].lsqEntries = 0; 522623SN/A freeEntries[i].robEntries = 0; 532623SN/A 542623SN/A stalls[i].iew = false; 552623SN/A stalls[i].commit = false; 562623SN/A serializeInst[i] = NULL; 572623SN/A 582623SN/A instsInProgress[i] = 0; 592623SN/A 602623SN/A emptyROB[i] = true; 612623SN/A 622623SN/A serializeOnNextInst[i] = false; 635336Shines@cs.fsu.edu } 642623SN/A 654873Sstever@eecs.umich.edu // @todo: Make into a parameter. 662623SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 672623SN/A} 682856Srdreslin@umich.edu 696227Snate@binkert.orgtemplate <class Impl> 702856Srdreslin@umich.edustd::string 712856Srdreslin@umich.eduDefaultRename<Impl>::name() const 722856Srdreslin@umich.edu{ 732856Srdreslin@umich.edu return cpu->name() + ".rename"; 742856Srdreslin@umich.edu} 754968Sacolyte@umich.edu 764968Sacolyte@umich.edutemplate <class Impl> 774968Sacolyte@umich.eduvoid 784968Sacolyte@umich.eduDefaultRename<Impl>::regStats() 792856Srdreslin@umich.edu{ 802856Srdreslin@umich.edu renameSquashCycles 812856Srdreslin@umich.edu .name(name() + ".RENAME:SquashCycles") 822623SN/A .desc("Number of cycles rename is squashing") 832623SN/A .prereq(renameSquashCycles); 842623SN/A renameIdleCycles 852623SN/A .name(name() + ".RENAME:IdleCycles") 862623SN/A .desc("Number of cycles rename is idle") 878779Sgblack@eecs.umich.edu .prereq(renameIdleCycles); 888779Sgblack@eecs.umich.edu renameBlockCycles 898779Sgblack@eecs.umich.edu .name(name() + ".RENAME:BlockCycles") 908779Sgblack@eecs.umich.edu .desc("Number of cycles rename is blocking") 918779Sgblack@eecs.umich.edu .prereq(renameBlockCycles); 928779Sgblack@eecs.umich.edu renameSerializeStallCycles 938779Sgblack@eecs.umich.edu .name(name() + ".RENAME:serializeStallCycles") 942623SN/A .desc("count of cycles rename stalled for serializing inst") 958706Sandreas.hansson@arm.com .flags(Stats::total); 968706Sandreas.hansson@arm.com renameRunCycles 978706Sandreas.hansson@arm.com .name(name() + ".RENAME:RunCycles") 988799Sgblack@eecs.umich.edu .desc("Number of cycles rename is running") 994968Sacolyte@umich.edu .prereq(renameIdleCycles); 1008711Sandreas.hansson@arm.com renameUnblockCycles 1014968Sacolyte@umich.edu .name(name() + ".RENAME:UnblockCycles") 1024968Sacolyte@umich.edu .desc("Number of cycles rename is unblocking") 1035714Shsul@eecs.umich.edu .prereq(renameUnblockCycles); 1045712Shsul@eecs.umich.edu renameRenamedInsts 1055712Shsul@eecs.umich.edu .name(name() + ".RENAME:RenamedInsts") 1065712Shsul@eecs.umich.edu .desc("Number of instructions processed by rename") 1072623SN/A .prereq(renameRenamedInsts); 1082623SN/A renameSquashedInsts 1095529Snate@binkert.org .name(name() + ".RENAME:SquashedInsts") 1106078Sgblack@eecs.umich.edu .desc("Number of squashed instructions processed by rename") 1115487Snate@binkert.org .prereq(renameSquashedInsts); 1125487Snate@binkert.org renameROBFullEvents 1134968Sacolyte@umich.edu .name(name() + ".RENAME:ROBFullEvents") 1144968Sacolyte@umich.edu .desc("Number of times rename has blocked due to ROB full") 1152623SN/A .prereq(renameROBFullEvents); 1162623SN/A renameIQFullEvents 1172623SN/A .name(name() + ".RENAME:IQFullEvents") 1182623SN/A .desc("Number of times rename has blocked due to IQ full") 1192623SN/A .prereq(renameIQFullEvents); 1202623SN/A renameLSQFullEvents 1212623SN/A .name(name() + ".RENAME:LSQFullEvents") 1226775SBrad.Beckmann@amd.com .desc("Number of times rename has blocked due to LSQ full") 1236775SBrad.Beckmann@amd.com .prereq(renameLSQFullEvents); 1246775SBrad.Beckmann@amd.com renameFullRegistersEvents 1252623SN/A .name(name() + ".RENAME:FullRegisterEvents") 1262623SN/A .desc("Number of times there has been no free registers") 1272623SN/A .prereq(renameFullRegistersEvents); 1282623SN/A renameRenamedOperands 1292623SN/A .name(name() + ".RENAME:RenamedOperands") 1302915Sktlim@umich.edu .desc("Number of destination operands rename has renamed") 1312915Sktlim@umich.edu .prereq(renameRenamedOperands); 1326078Sgblack@eecs.umich.edu renameRenameLookups 1333145Shsul@eecs.umich.edu .name(name() + ".RENAME:RenameLookups") 1342623SN/A .desc("Number of register rename lookups that rename has made") 1352623SN/A .prereq(renameRenameLookups); 1362623SN/A renameCommittedMaps 1372623SN/A .name(name() + ".RENAME:CommittedMaps") 1382623SN/A .desc("Number of HB maps that are committed") 1392623SN/A .prereq(renameCommittedMaps); 1402623SN/A renameUndoneMaps 1412915Sktlim@umich.edu .name(name() + ".RENAME:UndoneMaps") 1422915Sktlim@umich.edu .desc("Number of HB maps that are undone due to squashing") 1436078Sgblack@eecs.umich.edu .prereq(renameUndoneMaps); 1443145Shsul@eecs.umich.edu renamedSerializing 1452915Sktlim@umich.edu .name(name() + ".RENAME:serializingInsts") 1462915Sktlim@umich.edu .desc("count of serializing insts renamed") 1472915Sktlim@umich.edu .flags(Stats::total) 1482915Sktlim@umich.edu ; 1492915Sktlim@umich.edu renamedTempSerializing 1502915Sktlim@umich.edu .name(name() + ".RENAME:tempSerializingInsts") 1515220Ssaidi@eecs.umich.edu .desc("count of temporary serializing insts renamed") 1525220Ssaidi@eecs.umich.edu .flags(Stats::total) 1535220Ssaidi@eecs.umich.edu ; 1544940Snate@binkert.org renameSkidInsts 1555220Ssaidi@eecs.umich.edu .name(name() + ".RENAME:skidInsts") 1563324Shsul@eecs.umich.edu .desc("count of insts added to the skid buffer") 1575220Ssaidi@eecs.umich.edu .flags(Stats::total) 1585220Ssaidi@eecs.umich.edu ; 1595606Snate@binkert.org} 1605606Snate@binkert.org 1612915Sktlim@umich.edutemplate <class Impl> 1627897Shestness@cs.utexas.eduvoid 1632623SN/ADefaultRename<Impl>::setCPU(FullCPU *cpu_ptr) 1642623SN/A{ 1652623SN/A DPRINTF(Rename, "Setting CPU pointer.\n"); 1662798Sktlim@umich.edu cpu = cpu_ptr; 1672623SN/A} 1685496Ssaidi@eecs.umich.edu 1692798Sktlim@umich.edutemplate <class Impl> 1702623SN/Avoid 1712798Sktlim@umich.eduDefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1722623SN/A{ 1732623SN/A DPRINTF(Rename, "Setting time buffer pointer.\n"); 1742623SN/A timeBuffer = tb_ptr; 1752623SN/A 1762623SN/A // Setup wire to read information from time buffer, from IEW stage. 1772623SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1784192Sktlim@umich.edu 1792623SN/A // Setup wire to read infromation from time buffer, from commit stage. 1802623SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1812623SN/A 1822680Sktlim@umich.edu // Setup wire to write information to previous stages. 1832623SN/A toDecode = timeBuffer->getWire(0); 1846221Snate@binkert.org} 1856221Snate@binkert.org 1862680Sktlim@umich.edutemplate <class Impl> 1872680Sktlim@umich.eduvoid 1882623SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1895606Snate@binkert.org{ 1902623SN/A DPRINTF(Rename, "Setting rename queue pointer.\n"); 1912623SN/A renameQueue = rq_ptr; 1922623SN/A 1933512Sktlim@umich.edu // Setup wire to write information to future stages. 1943512Sktlim@umich.edu toIEW = renameQueue->getWire(0); 1953512Sktlim@umich.edu} 1965169Ssaidi@eecs.umich.edu 1975712Shsul@eecs.umich.edutemplate <class Impl> 1985712Shsul@eecs.umich.eduvoid 1995712Shsul@eecs.umich.eduDefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2002623SN/A{ 2012623SN/A DPRINTF(Rename, "Setting decode queue pointer.\n"); 2022623SN/A decodeQueue = dq_ptr; 2032623SN/A 2042623SN/A // Setup wire to get information from decode. 2052623SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2064940Snate@binkert.org} 2074940Snate@binkert.org 2082623SN/Atemplate <class Impl> 2092683Sktlim@umich.eduvoid 2102623SN/ADefaultRename<Impl>::initStage() 2112623SN/A{ 2122623SN/A // Grab the number of free entries directly from the stages. 2132623SN/A for (int tid=0; tid < numThreads; tid++) { 2142623SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2155101Ssaidi@eecs.umich.edu freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2163686Sktlim@umich.edu freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2173430Sgblack@eecs.umich.edu emptyROB[tid] = true; 2187823Ssteve.reinhardt@amd.com } 2192623SN/A} 2202623SN/A 2212623SN/Atemplate<class Impl> 2222623SN/Avoid 2232623SN/ADefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr) 2242623SN/A{ 2252623SN/A DPRINTF(Rename, "Setting active threads list pointer.\n"); 2264940Snate@binkert.org activeThreads = at_ptr; 2274940Snate@binkert.org} 2282623SN/A 2292683Sktlim@umich.edu 2302623SN/Atemplate <class Impl> 2316043Sgblack@eecs.umich.eduvoid 2326043Sgblack@eecs.umich.eduDefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2336043Sgblack@eecs.umich.edu{ 2342623SN/A DPRINTF(Rename, "Setting rename map pointers.\n"); 2352626SN/A 2362626SN/A for (int i=0; i<numThreads; i++) { 2372626SN/A renameMap[i] = &rm_ptr[i]; 2382626SN/A } 2395606Snate@binkert.org} 2402623SN/A 2412623SN/Atemplate <class Impl> 2422623SN/Avoid 2432623SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2442623SN/A{ 2452623SN/A DPRINTF(Rename, "Setting free list pointer.\n"); 2462623SN/A freeList = fl_ptr; 2478444Sgblack@eecs.umich.edu} 2488444Sgblack@eecs.umich.edu 2492623SN/Atemplate<class Impl> 2503169Sstever@eecs.umich.eduvoid 2514870Sstever@eecs.umich.eduDefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2522623SN/A{ 2532623SN/A DPRINTF(Rename, "Setting scoreboard pointer.\n"); 2542623SN/A scoreboard = _scoreboard; 2552623SN/A} 2562623SN/A 2574999Sgblack@eecs.umich.edutemplate <class Impl> 2586227Snate@binkert.orgvoid 2594999Sgblack@eecs.umich.eduDefaultRename<Impl>::switchOut() 2607520Sgblack@eecs.umich.edu{ 2612623SN/A // Rename is ready to switch out at any time. 2624999Sgblack@eecs.umich.edu cpu->signalSwitched(); 2634999Sgblack@eecs.umich.edu} 2647520Sgblack@eecs.umich.edu 2654999Sgblack@eecs.umich.edutemplate <class Impl> 2667520Sgblack@eecs.umich.eduvoid 2677520Sgblack@eecs.umich.eduDefaultRename<Impl>::doSwitchOut() 2684999Sgblack@eecs.umich.edu{ 2694999Sgblack@eecs.umich.edu // Clear any state, fix up the rename map. 2704999Sgblack@eecs.umich.edu for (int i = 0; i < numThreads; i++) { 2717520Sgblack@eecs.umich.edu typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin(); 2727720Sgblack@eecs.umich.edu 2734999Sgblack@eecs.umich.edu while (!historyBuffer[i].empty()) { 2744999Sgblack@eecs.umich.edu assert(hb_it != historyBuffer[i].end()); 2756023Snate@binkert.org 2764999Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2774999Sgblack@eecs.umich.edu "number %i.\n", i, (*hb_it).instSeqNum); 2786623Sgblack@eecs.umich.edu 2794999Sgblack@eecs.umich.edu // Tell the rename map to set the architected register to the 2806102Sgblack@eecs.umich.edu // previous physical register that it was renamed to. 2814999Sgblack@eecs.umich.edu renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2827520Sgblack@eecs.umich.edu 2834999Sgblack@eecs.umich.edu // Put the renamed physical register back on the free list. 2848105Sgblack@eecs.umich.edu freeList->addReg(hb_it->newPhysReg); 2854999Sgblack@eecs.umich.edu 2864999Sgblack@eecs.umich.edu historyBuffer[i].erase(hb_it++); 2874999Sgblack@eecs.umich.edu } 2884999Sgblack@eecs.umich.edu insts[i].clear(); 2894999Sgblack@eecs.umich.edu skidBuffer[i].clear(); 2904999Sgblack@eecs.umich.edu } 2914999Sgblack@eecs.umich.edu} 2924999Sgblack@eecs.umich.edu 2935012Sgblack@eecs.umich.edutemplate <class Impl> 2944999Sgblack@eecs.umich.eduvoid 2954999Sgblack@eecs.umich.eduDefaultRename<Impl>::takeOverFrom() 2966102Sgblack@eecs.umich.edu{ 2974999Sgblack@eecs.umich.edu _status = Inactive; 2984999Sgblack@eecs.umich.edu initStage(); 2994968Sacolyte@umich.edu 3004986Ssaidi@eecs.umich.edu // Reset all state prior to taking over from the other CPU. 3014999Sgblack@eecs.umich.edu for (int i=0; i< numThreads; i++) { 3026739Sgblack@eecs.umich.edu renameStatus[i] = Idle; 3036739Sgblack@eecs.umich.edu 3046739Sgblack@eecs.umich.edu stalls[i].iew = false; 3056739Sgblack@eecs.umich.edu stalls[i].commit = false; 3066739Sgblack@eecs.umich.edu serializeInst[i] = NULL; 3076739Sgblack@eecs.umich.edu 3086739Sgblack@eecs.umich.edu instsInProgress[i] = 0; 3096739Sgblack@eecs.umich.edu 3104999Sgblack@eecs.umich.edu emptyROB[i] = true; 3114999Sgblack@eecs.umich.edu 3124999Sgblack@eecs.umich.edu serializeOnNextInst[i] = false; 3136078Sgblack@eecs.umich.edu } 3146078Sgblack@eecs.umich.edu} 3156078Sgblack@eecs.umich.edu 3166078Sgblack@eecs.umich.edutemplate <class Impl> 3174999Sgblack@eecs.umich.eduvoid 3184968Sacolyte@umich.eduDefaultRename<Impl>::squash(unsigned tid) 3193170Sstever@eecs.umich.edu{ 3204999Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3214999Sgblack@eecs.umich.edu 3224999Sgblack@eecs.umich.edu // Clear the stall signal if rename was blocked or unblocking before. 3234999Sgblack@eecs.umich.edu // If it still needs to block, the blocking should happen the next 3244999Sgblack@eecs.umich.edu // cycle and there should be space to hold everything due to the squash. 3257520Sgblack@eecs.umich.edu if (renameStatus[tid] == Blocked || 3264999Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking || 3277520Sgblack@eecs.umich.edu renameStatus[tid] == SerializeStall) { 3284999Sgblack@eecs.umich.edu#if 0 3294999Sgblack@eecs.umich.edu // In syscall emulation, we can have both a block and a squash due 3302623SN/A // to a syscall in the same cycle. This would cause both signals to 3312623SN/A // be high. This shouldn't happen in full system. 3322623SN/A if (toDecode->renameBlock[tid]) { 3337520Sgblack@eecs.umich.edu toDecode->renameBlock[tid] = 0; 3342623SN/A } else { 3358444Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3368444Sgblack@eecs.umich.edu } 3372623SN/A#else 3383169Sstever@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3394870Sstever@eecs.umich.edu#endif 3402623SN/A serializeInst[tid] = NULL; 3412623SN/A } 3422623SN/A 3432623SN/A // Set the status to Squashing. 3442623SN/A renameStatus[tid] = Squashing; 3454999Sgblack@eecs.umich.edu 3466227Snate@binkert.org // Squash any instructions from decode. 3474999Sgblack@eecs.umich.edu unsigned squashCount = 0; 3487520Sgblack@eecs.umich.edu 3492623SN/A for (int i=0; i<fromDecode->size; i++) { 3504999Sgblack@eecs.umich.edu if (fromDecode->insts[i]->threadNumber == tid) { 3514999Sgblack@eecs.umich.edu fromDecode->insts[i]->squashed = true; 3527520Sgblack@eecs.umich.edu wroteToTimeBuffer = true; 3534999Sgblack@eecs.umich.edu squashCount++; 3544999Sgblack@eecs.umich.edu } 3557520Sgblack@eecs.umich.edu } 3564999Sgblack@eecs.umich.edu 3574999Sgblack@eecs.umich.edu insts[tid].clear(); 3584999Sgblack@eecs.umich.edu 3594999Sgblack@eecs.umich.edu // Clear the skid buffer in case it has any data in it. 3607720Sgblack@eecs.umich.edu skidBuffer[tid].clear(); 3614999Sgblack@eecs.umich.edu 3624999Sgblack@eecs.umich.edu doSquash(tid); 3636023Snate@binkert.org} 3644999Sgblack@eecs.umich.edu 3654999Sgblack@eecs.umich.edutemplate <class Impl> 3664999Sgblack@eecs.umich.eduvoid 3674999Sgblack@eecs.umich.eduDefaultRename<Impl>::tick() 3684999Sgblack@eecs.umich.edu{ 3694999Sgblack@eecs.umich.edu wroteToTimeBuffer = false; 3706102Sgblack@eecs.umich.edu 3714999Sgblack@eecs.umich.edu blockThisCycle = false; 3724999Sgblack@eecs.umich.edu 3734999Sgblack@eecs.umich.edu bool status_change = false; 3744999Sgblack@eecs.umich.edu 3754999Sgblack@eecs.umich.edu toIEWIndex = 0; 3764999Sgblack@eecs.umich.edu 3774999Sgblack@eecs.umich.edu sortInsts(); 3784999Sgblack@eecs.umich.edu 3794999Sgblack@eecs.umich.edu list<unsigned>::iterator threads = (*activeThreads).begin(); 3804999Sgblack@eecs.umich.edu 3816623Sgblack@eecs.umich.edu // Check stall and squash signals. 3824999Sgblack@eecs.umich.edu while (threads != (*activeThreads).end()) { 3837520Sgblack@eecs.umich.edu unsigned tid = *threads++; 3844999Sgblack@eecs.umich.edu 3858105Sgblack@eecs.umich.edu DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3864999Sgblack@eecs.umich.edu 3874999Sgblack@eecs.umich.edu status_change = checkSignalsAndUpdate(tid) || status_change; 3884999Sgblack@eecs.umich.edu 3894999Sgblack@eecs.umich.edu rename(status_change, tid); 3904999Sgblack@eecs.umich.edu } 3914999Sgblack@eecs.umich.edu 3924999Sgblack@eecs.umich.edu if (status_change) { 3934999Sgblack@eecs.umich.edu updateStatus(); 3944999Sgblack@eecs.umich.edu } 3954999Sgblack@eecs.umich.edu 3964999Sgblack@eecs.umich.edu if (wroteToTimeBuffer) { 3974999Sgblack@eecs.umich.edu DPRINTF(Activity, "Activity this cycle.\n"); 3984999Sgblack@eecs.umich.edu cpu->activityThisCycle(); 3997520Sgblack@eecs.umich.edu } 4004999Sgblack@eecs.umich.edu 4014999Sgblack@eecs.umich.edu threads = (*activeThreads).begin(); 4024999Sgblack@eecs.umich.edu 4034999Sgblack@eecs.umich.edu while (threads != (*activeThreads).end()) { 4044999Sgblack@eecs.umich.edu unsigned tid = *threads++; 4054878Sstever@eecs.umich.edu 4064040Ssaidi@eecs.umich.edu // If we committed this cycle then doneSeqNum will be > 0 4074040Ssaidi@eecs.umich.edu if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4084999Sgblack@eecs.umich.edu !fromCommit->commitInfo[tid].squash && 4094999Sgblack@eecs.umich.edu renameStatus[tid] != Squashing) { 4104999Sgblack@eecs.umich.edu 4114999Sgblack@eecs.umich.edu removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4126078Sgblack@eecs.umich.edu tid); 4136078Sgblack@eecs.umich.edu } 4146078Sgblack@eecs.umich.edu } 4156078Sgblack@eecs.umich.edu 4166739Sgblack@eecs.umich.edu // @todo: make into updateProgress function 4176739Sgblack@eecs.umich.edu for (int tid=0; tid < numThreads; tid++) { 4186739Sgblack@eecs.umich.edu instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4196739Sgblack@eecs.umich.edu 4206739Sgblack@eecs.umich.edu assert(instsInProgress[tid] >=0); 4213170Sstever@eecs.umich.edu } 4223170Sstever@eecs.umich.edu 4234999Sgblack@eecs.umich.edu} 4244999Sgblack@eecs.umich.edu 4254999Sgblack@eecs.umich.edutemplate<class Impl> 4264999Sgblack@eecs.umich.eduvoid 4274999Sgblack@eecs.umich.eduDefaultRename<Impl>::rename(bool &status_change, unsigned tid) 4287520Sgblack@eecs.umich.edu{ 4294999Sgblack@eecs.umich.edu // If status is Running or idle, 4307520Sgblack@eecs.umich.edu // call renameInsts() 4314999Sgblack@eecs.umich.edu // If status is Unblocking, 4324999Sgblack@eecs.umich.edu // buffer any instructions coming from decode 4332623SN/A // continue trying to empty skid buffer 4342623SN/A // check if stall conditions have passed 4352623SN/A 4362623SN/A if (renameStatus[tid] == Blocked) { 4372623SN/A ++renameBlockCycles; 4382623SN/A } else if (renameStatus[tid] == Squashing) { 4392623SN/A ++renameSquashCycles; 4404940Snate@binkert.org } else if (renameStatus[tid] == SerializeStall) { 4414940Snate@binkert.org ++renameSerializeStallCycles; 4425487Snate@binkert.org } 4432623SN/A 4446078Sgblack@eecs.umich.edu if (renameStatus[tid] == Running || 4452623SN/A renameStatus[tid] == Idle) { 4462623SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4473387Sgblack@eecs.umich.edu "stage.\n", tid); 4483387Sgblack@eecs.umich.edu 4492626SN/A renameInsts(tid); 4505348Ssaidi@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4518143SAli.Saidi@ARM.com renameInsts(tid); 4528143SAli.Saidi@ARM.com 4538143SAli.Saidi@ARM.com if (validInsts()) { 4545348Ssaidi@eecs.umich.edu // Add the current inputs to the skid buffer so they can be 4555669Sgblack@eecs.umich.edu // reprocessed when this stage unblocks. 4565669Sgblack@eecs.umich.edu skidInsert(tid); 4577720Sgblack@eecs.umich.edu } 4587720Sgblack@eecs.umich.edu 4597720Sgblack@eecs.umich.edu // If we switched over to blocking, then there's a potential for 4607720Sgblack@eecs.umich.edu // an overall status change. 4617720Sgblack@eecs.umich.edu status_change = unblock(tid) || status_change || blockThisCycle; 4625894Sgblack@eecs.umich.edu } 4636023Snate@binkert.org} 4646023Snate@binkert.org 4655894Sgblack@eecs.umich.edutemplate <class Impl> 4662623SN/Avoid 4672623SN/ADefaultRename<Impl>::renameInsts(unsigned tid) 4684182Sgblack@eecs.umich.edu{ 4694182Sgblack@eecs.umich.edu // Instructions can be either in the skid buffer or the queue of 4704182Sgblack@eecs.umich.edu // instructions coming from decode, depending on the status. 4712662Sstever@eecs.umich.edu int insts_available = renameStatus[tid] == Unblocking ? 4727720Sgblack@eecs.umich.edu skidBuffer[tid].size() : insts[tid].size(); 4735694Sgblack@eecs.umich.edu 4745694Sgblack@eecs.umich.edu // Check the decode queue to see if instructions are available. 4755694Sgblack@eecs.umich.edu // If there are no available instructions to rename, then do nothing. 4765694Sgblack@eecs.umich.edu if (insts_available == 0) { 4775669Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4785669Sgblack@eecs.umich.edu tid); 4795669Sgblack@eecs.umich.edu // Should I change status to idle? 4805669Sgblack@eecs.umich.edu ++renameIdleCycles; 4815669Sgblack@eecs.umich.edu return; 4825669Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4835669Sgblack@eecs.umich.edu ++renameUnblockCycles; 4842623SN/A } else if (renameStatus[tid] == Running) { 4855669Sgblack@eecs.umich.edu ++renameRunCycles; 4865669Sgblack@eecs.umich.edu } 4875669Sgblack@eecs.umich.edu 4885669Sgblack@eecs.umich.edu DynInstPtr inst; 4894968Sacolyte@umich.edu 4905669Sgblack@eecs.umich.edu // Will have to do a different calculation for the number of free 4914968Sacolyte@umich.edu // entries. 4925669Sgblack@eecs.umich.edu int free_rob_entries = calcFreeROBEntries(tid); 4935669Sgblack@eecs.umich.edu int free_iq_entries = calcFreeIQEntries(tid); 4945669Sgblack@eecs.umich.edu int free_lsq_entries = calcFreeLSQEntries(tid); 4955669Sgblack@eecs.umich.edu int min_free_entries = free_rob_entries; 4964182Sgblack@eecs.umich.edu 4972623SN/A FullSource source = ROB; 4983814Ssaidi@eecs.umich.edu 4995001Sgblack@eecs.umich.edu if (free_iq_entries < min_free_entries) { 5004182Sgblack@eecs.umich.edu min_free_entries = free_iq_entries; 5014998Sgblack@eecs.umich.edu source = IQ; 5024998Sgblack@eecs.umich.edu } 5034998Sgblack@eecs.umich.edu 5044998Sgblack@eecs.umich.edu if (free_lsq_entries < min_free_entries) { 5057655Sali.saidi@arm.com min_free_entries = free_lsq_entries; 5065001Sgblack@eecs.umich.edu source = LSQ; 5075001Sgblack@eecs.umich.edu } 5085001Sgblack@eecs.umich.edu 5094998Sgblack@eecs.umich.edu // Check if there's any space left. 5104182Sgblack@eecs.umich.edu if (min_free_entries <= 0) { 5114182Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5122623SN/A "entries.\n" 5133814Ssaidi@eecs.umich.edu "ROB has %i free entries.\n" 5144539Sgblack@eecs.umich.edu "IQ has %i free entries.\n" 5154539Sgblack@eecs.umich.edu "LSQ has %i free entries.\n", 5163814Ssaidi@eecs.umich.edu tid, 5173814Ssaidi@eecs.umich.edu free_rob_entries, 5185487Snate@binkert.org free_iq_entries, 5195487Snate@binkert.org free_lsq_entries); 5205487Snate@binkert.org 5215487Snate@binkert.org blockThisCycle = true; 5225487Snate@binkert.org 5235487Snate@binkert.org block(tid); 5245487Snate@binkert.org 5255487Snate@binkert.org incrFullStat(source); 5265487Snate@binkert.org 5275487Snate@binkert.org return; 5285487Snate@binkert.org } else if (min_free_entries < insts_available) { 5295487Snate@binkert.org DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5305487Snate@binkert.org "%i insts available, but only %i insts can be " 5315487Snate@binkert.org "renamed due to ROB/IQ/LSQ limits.\n", 5325487Snate@binkert.org tid, insts_available, min_free_entries); 5332623SN/A 5342623SN/A insts_available = min_free_entries; 5352623SN/A 5364377Sgblack@eecs.umich.edu blockThisCycle = true; 5374182Sgblack@eecs.umich.edu 5382623SN/A incrFullStat(source); 5392623SN/A } 5405487Snate@binkert.org 5415487Snate@binkert.org InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5425487Snate@binkert.org skidBuffer[tid] : insts[tid]; 5435487Snate@binkert.org 5442626SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5457823Ssteve.reinhardt@amd.com "send iew.\n", tid, insts_available); 5462623SN/A 5472623SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5482623SN/A "dispatched to IQ last cycle.\n", 5495315Sstever@gmail.com tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5505315Sstever@gmail.com 5515315Sstever@gmail.com // Handle serializing the next instruction if necessary. 5525315Sstever@gmail.com if (serializeOnNextInst[tid]) { 5535315Sstever@gmail.com if (emptyROB[tid] && instsInProgress[tid] == 0) { 5545315Sstever@gmail.com // ROB already empty; no need to serialize. 5555315Sstever@gmail.com serializeOnNextInst[tid] = false; 5562623SN/A } else if (!insts_to_rename.empty()) { 5572623SN/A insts_to_rename.front()->setSerializeBefore(); 5582623SN/A } 5592623SN/A } 5604762Snate@binkert.org 5614762Snate@binkert.org int renamed_insts = 0; 5622623SN/A 5635529Snate@binkert.org while (insts_available > 0 && toIEWIndex < renameWidth) { 5648779Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5654762Snate@binkert.org 5665529Snate@binkert.org assert(!insts_to_rename.empty()); 5672623SN/A 568 inst = insts_to_rename.front(); 569 570 insts_to_rename.pop_front(); 571 572 if (renameStatus[tid] == Unblocking) { 573 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 574 "skidBuffer\n", 575 tid, inst->seqNum, inst->readPC()); 576 } 577 578 if (inst->isSquashed()) { 579 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 580 "squashed, skipping.\n", 581 tid, inst->seqNum, inst->threadNumber,inst->readPC()); 582 583 ++renameSquashedInsts; 584 585 // Decrement how many instructions are available. 586 --insts_available; 587 588 continue; 589 } 590 591 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 592 "PC %#x.\n", 593 tid, inst->seqNum, inst->readPC()); 594 595 // Handle serializeAfter/serializeBefore instructions. 596 // serializeAfter marks the next instruction as serializeBefore. 597 // serializeBefore makes the instruction wait in rename until the ROB 598 // is empty. 599 600 // In this model, IPR accesses are serialize before 601 // instructions, and store conditionals are serialize after 602 // instructions. This is mainly due to lack of support for 603 // out-of-order operations of either of those classes of 604 // instructions. 605 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 606 !inst->isSerializeHandled()) { 607 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 608 609 if (!inst->isTempSerializeBefore()) { 610 renamedSerializing++; 611 inst->setSerializeHandled(); 612 } else { 613 renamedTempSerializing++; 614 } 615 616 // Change status over to SerializeStall so that other stages know 617 // what this is blocked on. 618 renameStatus[tid] = SerializeStall; 619 620 serializeInst[tid] = inst; 621 622 blockThisCycle = true; 623 624 break; 625 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 626 !inst->isSerializeHandled()) { 627 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 628 629 renamedSerializing++; 630 631 inst->setSerializeHandled(); 632 633 serializeAfter(insts_to_rename, tid); 634 } 635 636 // Check here to make sure there are enough destination registers 637 // to rename to. Otherwise block. 638 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 639 DPRINTF(Rename, "Blocking due to lack of free " 640 "physical registers to rename to.\n"); 641 blockThisCycle = true; 642 643 ++renameFullRegistersEvents; 644 645 break; 646 } 647 648 renameSrcRegs(inst, inst->threadNumber); 649 650 renameDestRegs(inst, inst->threadNumber); 651 652 ++renamed_insts; 653 654 // Put instruction in rename queue. 655 toIEW->insts[toIEWIndex] = inst; 656 ++(toIEW->size); 657 658 // Increment which instruction we're on. 659 ++toIEWIndex; 660 661 // Decrement how many instructions are available. 662 --insts_available; 663 } 664 665 instsInProgress[tid] += renamed_insts; 666 renameRenamedInsts += renamed_insts; 667 668 // If we wrote to the time buffer, record this. 669 if (toIEWIndex) { 670 wroteToTimeBuffer = true; 671 } 672 673 // Check if there's any instructions left that haven't yet been renamed. 674 // If so then block. 675 if (insts_available) { 676 blockThisCycle = true; 677 } 678 679 if (blockThisCycle) { 680 block(tid); 681 toDecode->renameUnblock[tid] = false; 682 } 683} 684 685template<class Impl> 686void 687DefaultRename<Impl>::skidInsert(unsigned tid) 688{ 689 DynInstPtr inst = NULL; 690 691 while (!insts[tid].empty()) { 692 inst = insts[tid].front(); 693 694 insts[tid].pop_front(); 695 696 assert(tid == inst->threadNumber); 697 698 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 699 "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 700 701 ++renameSkidInsts; 702 703 skidBuffer[tid].push_back(inst); 704 } 705 706 if (skidBuffer[tid].size() > skidBufferMax) 707 panic("Skidbuffer Exceeded Max Size"); 708} 709 710template <class Impl> 711void 712DefaultRename<Impl>::sortInsts() 713{ 714 int insts_from_decode = fromDecode->size; 715#ifdef DEBUG 716 for (int i=0; i < numThreads; i++) 717 assert(insts[i].empty()); 718#endif 719 for (int i = 0; i < insts_from_decode; ++i) { 720 DynInstPtr inst = fromDecode->insts[i]; 721 insts[inst->threadNumber].push_back(inst); 722 } 723} 724 725template<class Impl> 726bool 727DefaultRename<Impl>::skidsEmpty() 728{ 729 list<unsigned>::iterator threads = (*activeThreads).begin(); 730 731 while (threads != (*activeThreads).end()) { 732 if (!skidBuffer[*threads++].empty()) 733 return false; 734 } 735 736 return true; 737} 738 739template<class Impl> 740void 741DefaultRename<Impl>::updateStatus() 742{ 743 bool any_unblocking = false; 744 745 list<unsigned>::iterator threads = (*activeThreads).begin(); 746 747 threads = (*activeThreads).begin(); 748 749 while (threads != (*activeThreads).end()) { 750 unsigned tid = *threads++; 751 752 if (renameStatus[tid] == Unblocking) { 753 any_unblocking = true; 754 break; 755 } 756 } 757 758 // Rename will have activity if it's unblocking. 759 if (any_unblocking) { 760 if (_status == Inactive) { 761 _status = Active; 762 763 DPRINTF(Activity, "Activating stage.\n"); 764 765 cpu->activateStage(FullCPU::RenameIdx); 766 } 767 } else { 768 // If it's not unblocking, then rename will not have any internal 769 // activity. Switch it to inactive. 770 if (_status == Active) { 771 _status = Inactive; 772 DPRINTF(Activity, "Deactivating stage.\n"); 773 774 cpu->deactivateStage(FullCPU::RenameIdx); 775 } 776 } 777} 778 779template <class Impl> 780bool 781DefaultRename<Impl>::block(unsigned tid) 782{ 783 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 784 785 // Add the current inputs onto the skid buffer, so they can be 786 // reprocessed when this stage unblocks. 787 skidInsert(tid); 788 789 // Only signal backwards to block if the previous stages do not think 790 // rename is already blocked. 791 if (renameStatus[tid] != Blocked) { 792 if (renameStatus[tid] != Unblocking) { 793 toDecode->renameBlock[tid] = true; 794 toDecode->renameUnblock[tid] = false; 795 wroteToTimeBuffer = true; 796 } 797 798 // Rename can not go from SerializeStall to Blocked, otherwise 799 // it would not know to complete the serialize stall. 800 if (renameStatus[tid] != SerializeStall) { 801 // Set status to Blocked. 802 renameStatus[tid] = Blocked; 803 return true; 804 } 805 } 806 807 return false; 808} 809 810template <class Impl> 811bool 812DefaultRename<Impl>::unblock(unsigned tid) 813{ 814 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 815 816 // Rename is done unblocking if the skid buffer is empty. 817 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 818 819 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 820 821 toDecode->renameUnblock[tid] = true; 822 wroteToTimeBuffer = true; 823 824 renameStatus[tid] = Running; 825 return true; 826 } 827 828 return false; 829} 830 831template <class Impl> 832void 833DefaultRename<Impl>::doSquash(unsigned tid) 834{ 835 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin(); 836 837 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 838 839 // After a syscall squashes everything, the history buffer may be empty 840 // but the ROB may still be squashing instructions. 841 if (historyBuffer[tid].empty()) { 842 return; 843 } 844 845 // Go through the most recent instructions, undoing the mappings 846 // they did and freeing up the registers. 847 while (!historyBuffer[tid].empty() && 848 (*hb_it).instSeqNum > squashed_seq_num) { 849 assert(hb_it != historyBuffer[tid].end()); 850 851 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 852 "number %i.\n", tid, (*hb_it).instSeqNum); 853 854 // Tell the rename map to set the architected register to the 855 // previous physical register that it was renamed to. 856 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 857 858 // Put the renamed physical register back on the free list. 859 freeList->addReg(hb_it->newPhysReg); 860 861 historyBuffer[tid].erase(hb_it++); 862 863 ++renameUndoneMaps; 864 } 865} 866 867template<class Impl> 868void 869DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 870{ 871 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 872 "history buffer %u (size=%i), until [sn:%lli].\n", 873 tid, tid, historyBuffer[tid].size(), inst_seq_num); 874 875 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end(); 876 877 --hb_it; 878 879 if (historyBuffer[tid].empty()) { 880 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 881 return; 882 } else if (hb_it->instSeqNum > inst_seq_num) { 883 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 884 "that a syscall happened recently.\n", tid); 885 return; 886 } 887 888 // Commit all the renames up until (and including) the committed sequence 889 // number. Some or even all of the committed instructions may not have 890 // rename histories if they did not have destination registers that were 891 // renamed. 892 while (!historyBuffer[tid].empty() && 893 hb_it != historyBuffer[tid].end() && 894 (*hb_it).instSeqNum <= inst_seq_num) { 895 896 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 897 "[sn:%lli].\n", 898 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 899 900 freeList->addReg((*hb_it).prevPhysReg); 901 ++renameCommittedMaps; 902 903 historyBuffer[tid].erase(hb_it--); 904 } 905} 906 907template <class Impl> 908inline void 909DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 910{ 911 assert(renameMap[tid] != 0); 912 913 unsigned num_src_regs = inst->numSrcRegs(); 914 915 // Get the architectual register numbers from the source and 916 // destination operands, and redirect them to the right register. 917 // Will need to mark dependencies though. 918 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 919 RegIndex src_reg = inst->srcRegIdx(src_idx); 920 921 // Look up the source registers to get the phys. register they've 922 // been renamed to, and set the sources to those registers. 923 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg); 924 925 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 926 "physical reg %i.\n", tid, (int)src_reg, 927 (int)renamed_reg); 928 929 inst->renameSrcReg(src_idx, renamed_reg); 930 931 // See if the register is ready or not. 932 if (scoreboard->getReg(renamed_reg) == true) { 933 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 934 935 inst->markSrcRegReady(src_idx); 936 } 937 938 ++renameRenameLookups; 939 } 940} 941 942template <class Impl> 943inline void 944DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 945{ 946 typename RenameMap::RenameInfo rename_result; 947 948 unsigned num_dest_regs = inst->numDestRegs(); 949 950 // Rename the destination registers. 951 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 952 RegIndex dest_reg = inst->destRegIdx(dest_idx); 953 954 // Get the physical register that the destination will be 955 // renamed to. 956 rename_result = renameMap[tid]->rename(dest_reg); 957 958 //Mark Scoreboard entry as not ready 959 scoreboard->unsetReg(rename_result.first); 960 961 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 962 "reg %i.\n", tid, (int)dest_reg, 963 (int)rename_result.first); 964 965 // Record the rename information so that a history can be kept. 966 RenameHistory hb_entry(inst->seqNum, dest_reg, 967 rename_result.first, 968 rename_result.second); 969 970 historyBuffer[tid].push_front(hb_entry); 971 972 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, " 973 "[sn:%lli].\n",tid, 974 (*historyBuffer[tid].begin()).instSeqNum); 975 976 // Tell the instruction to rename the appropriate destination 977 // register (dest_idx) to the new physical register 978 // (rename_result.first), and record the previous physical 979 // register that the same logical register was renamed to 980 // (rename_result.second). 981 inst->renameDestReg(dest_idx, 982 rename_result.first, 983 rename_result.second); 984 985 ++renameRenamedOperands; 986 } 987} 988 989template <class Impl> 990inline int 991DefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 992{ 993 int num_free = freeEntries[tid].robEntries - 994 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 995 996 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 997 998 return num_free; 999} 1000 1001template <class Impl> 1002inline int 1003DefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 1004{ 1005 int num_free = freeEntries[tid].iqEntries - 1006 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1007 1008 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1009 1010 return num_free; 1011} 1012 1013template <class Impl> 1014inline int 1015DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 1016{ 1017 int num_free = freeEntries[tid].lsqEntries - 1018 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1019 1020 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1021 1022 return num_free; 1023} 1024 1025template <class Impl> 1026unsigned 1027DefaultRename<Impl>::validInsts() 1028{ 1029 unsigned inst_count = 0; 1030 1031 for (int i=0; i<fromDecode->size; i++) { 1032 if (!fromDecode->insts[i]->squashed) 1033 inst_count++; 1034 } 1035 1036 return inst_count; 1037} 1038 1039template <class Impl> 1040void 1041DefaultRename<Impl>::readStallSignals(unsigned tid) 1042{ 1043 if (fromIEW->iewBlock[tid]) { 1044 stalls[tid].iew = true; 1045 } 1046 1047 if (fromIEW->iewUnblock[tid]) { 1048 assert(stalls[tid].iew); 1049 stalls[tid].iew = false; 1050 } 1051 1052 if (fromCommit->commitBlock[tid]) { 1053 stalls[tid].commit = true; 1054 } 1055 1056 if (fromCommit->commitUnblock[tid]) { 1057 assert(stalls[tid].commit); 1058 stalls[tid].commit = false; 1059 } 1060} 1061 1062template <class Impl> 1063bool 1064DefaultRename<Impl>::checkStall(unsigned tid) 1065{ 1066 bool ret_val = false; 1067 1068 if (stalls[tid].iew) { 1069 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1070 ret_val = true; 1071 } else if (stalls[tid].commit) { 1072 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1073 ret_val = true; 1074 } else if (calcFreeROBEntries(tid) <= 0) { 1075 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1076 ret_val = true; 1077 } else if (calcFreeIQEntries(tid) <= 0) { 1078 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1079 ret_val = true; 1080 } else if (calcFreeLSQEntries(tid) <= 0) { 1081 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1082 ret_val = true; 1083 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1084 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1085 ret_val = true; 1086 } else if (renameStatus[tid] == SerializeStall && 1087 (!emptyROB[tid] || instsInProgress[tid])) { 1088 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1089 "empty.\n", 1090 tid); 1091 ret_val = true; 1092 } 1093 1094 return ret_val; 1095} 1096 1097template <class Impl> 1098void 1099DefaultRename<Impl>::readFreeEntries(unsigned tid) 1100{ 1101 bool updated = false; 1102 if (fromIEW->iewInfo[tid].usedIQ) { 1103 freeEntries[tid].iqEntries = 1104 fromIEW->iewInfo[tid].freeIQEntries; 1105 updated = true; 1106 } 1107 1108 if (fromIEW->iewInfo[tid].usedLSQ) { 1109 freeEntries[tid].lsqEntries = 1110 fromIEW->iewInfo[tid].freeLSQEntries; 1111 updated = true; 1112 } 1113 1114 if (fromCommit->commitInfo[tid].usedROB) { 1115 freeEntries[tid].robEntries = 1116 fromCommit->commitInfo[tid].freeROBEntries; 1117 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1118 updated = true; 1119 } 1120 1121 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1122 tid, 1123 freeEntries[tid].iqEntries, 1124 freeEntries[tid].robEntries, 1125 freeEntries[tid].lsqEntries); 1126 1127 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1128 tid, instsInProgress[tid]); 1129} 1130 1131template <class Impl> 1132bool 1133DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 1134{ 1135 // Check if there's a squash signal, squash if there is 1136 // Check stall signals, block if necessary. 1137 // If status was blocked 1138 // check if stall conditions have passed 1139 // if so then go to unblocking 1140 // If status was Squashing 1141 // check if squashing is not high. Switch to running this cycle. 1142 // If status was serialize stall 1143 // check if ROB is empty and no insts are in flight to the ROB 1144 1145 readFreeEntries(tid); 1146 readStallSignals(tid); 1147 1148 if (fromCommit->commitInfo[tid].squash) { 1149 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1150 "commit.\n", tid); 1151 1152 squash(tid); 1153 1154 return true; 1155 } 1156 1157 if (fromCommit->commitInfo[tid].robSquashing) { 1158 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1159 1160 renameStatus[tid] = Squashing; 1161 1162 return true; 1163 } 1164 1165 if (checkStall(tid)) { 1166 return block(tid); 1167 } 1168 1169 if (renameStatus[tid] == Blocked) { 1170 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1171 tid); 1172 1173 renameStatus[tid] = Unblocking; 1174 1175 unblock(tid); 1176 1177 return true; 1178 } 1179 1180 if (renameStatus[tid] == Squashing) { 1181 // Switch status to running if rename isn't being told to block or 1182 // squash this cycle. 1183 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1184 tid); 1185 1186 renameStatus[tid] = Running; 1187 1188 return false; 1189 } 1190 1191 if (renameStatus[tid] == SerializeStall) { 1192 // Stall ends once the ROB is free. 1193 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1194 "unblocking.\n", tid); 1195 1196 DynInstPtr serial_inst = serializeInst[tid]; 1197 1198 renameStatus[tid] = Unblocking; 1199 1200 unblock(tid); 1201 1202 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1203 "PC %#x.\n", 1204 tid, serial_inst->seqNum, serial_inst->readPC()); 1205 1206 // Put instruction into queue here. 1207 serial_inst->clearSerializeBefore(); 1208 1209 if (!skidBuffer[tid].empty()) { 1210 skidBuffer[tid].push_front(serial_inst); 1211 } else { 1212 insts[tid].push_front(serial_inst); 1213 } 1214 1215 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1216 " Adding to front of list.", tid); 1217 1218 serializeInst[tid] = NULL; 1219 1220 return true; 1221 } 1222 1223 // If we've reached this point, we have not gotten any signals that 1224 // cause rename to change its status. Rename remains the same as before. 1225 return false; 1226} 1227 1228template<class Impl> 1229void 1230DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 1231 unsigned tid) 1232{ 1233 if (inst_list.empty()) { 1234 // Mark a bit to say that I must serialize on the next instruction. 1235 serializeOnNextInst[tid] = true; 1236 return; 1237 } 1238 1239 // Set the next instruction as serializing. 1240 inst_list.front()->setSerializeBefore(); 1241} 1242 1243template <class Impl> 1244inline void 1245DefaultRename<Impl>::incrFullStat(const FullSource &source) 1246{ 1247 switch (source) { 1248 case ROB: 1249 ++renameROBFullEvents; 1250 break; 1251 case IQ: 1252 ++renameIQFullEvents; 1253 break; 1254 case LSQ: 1255 ++renameLSQFullEvents; 1256 break; 1257 default: 1258 panic("Rename full stall stat should be incremented for a reason!"); 1259 break; 1260 } 1261} 1262 1263template <class Impl> 1264void 1265DefaultRename<Impl>::dumpHistory() 1266{ 1267 typename list<RenameHistory>::iterator buf_it; 1268 1269 for (int i = 0; i < numThreads; i++) { 1270 1271 buf_it = historyBuffer[i].begin(); 1272 1273 while (buf_it != historyBuffer[i].end()) { 1274 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1275 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1276 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1277 1278 buf_it++; 1279 } 1280 } 1281} 1282