rename_impl.hh revision 2301
12315SN/A/* 212107SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 39913Ssteve.reinhardt@amd.com * All rights reserved. 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * Redistribution and use in source and binary forms, with or without 68733Sgeoffrey.blake@arm.com * modification, are permitted provided that the following conditions are 78733Sgeoffrey.blake@arm.com * met: redistributions of source code must retain the above copyright 88733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer; 98733Sgeoffrey.blake@arm.com * redistributions in binary form must reproduce the above copyright 108733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer in the 118733Sgeoffrey.blake@arm.com * documentation and/or other materials provided with the distribution; 128733Sgeoffrey.blake@arm.com * neither the name of the copyright holders nor the names of its 138733Sgeoffrey.blake@arm.com * contributors may be used to endorse or promote products derived from 148733Sgeoffrey.blake@arm.com * this software without specific prior written permission. 152332SN/A * 162315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272315SN/A */ 282315SN/A 292315SN/A#include <list> 302315SN/A 312315SN/A#include "config/full_system.hh" 322315SN/A#include "cpu/o3/rename.hh" 332315SN/A 342315SN/Ausing namespace std; 352315SN/A 362315SN/Atemplate <class Impl> 372315SN/ADefaultRename<Impl>::DefaultRename(Params *params) 382315SN/A : iewToRenameDelay(params->iewToRenameDelay), 392315SN/A decodeToRenameDelay(params->decodeToRenameDelay), 402689SN/A commitToRenameDelay(params->commitToRenameDelay), 412689SN/A renameWidth(params->renameWidth), 428733Sgeoffrey.blake@arm.com commitWidth(params->commitWidth), 432315SN/A numThreads(params->numberOfThreads) 442315SN/A{ 459944Smatt.horsnell@ARM.com _status = Inactive; 469944Smatt.horsnell@ARM.com 479944Smatt.horsnell@ARM.com for (int i=0; i< numThreads; i++) { 482315SN/A renameStatus[i] = Idle; 492315SN/A 502315SN/A freeEntries[i].iqEntries = 0; 518888Sgeoffrey.blake@arm.com freeEntries[i].lsqEntries = 0; 528793Sgblack@eecs.umich.edu freeEntries[i].robEntries = 0; 532315SN/A 546658Snate@binkert.org stalls[i].iew = false; 552315SN/A stalls[i].commit = false; 568733Sgeoffrey.blake@arm.com serializeInst[i] = NULL; 579913Ssteve.reinhardt@amd.com 582683SN/A instsInProgress[i] = 0; 598229Snate@binkert.org 602680SN/A emptyROB[i] = true; 618733Sgeoffrey.blake@arm.com 628733Sgeoffrey.blake@arm.com serializeOnNextInst[i] = false; 638793Sgblack@eecs.umich.edu } 642315SN/A 652315SN/A // @todo: Make into a parameter. 662315SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 672315SN/A} 688733Sgeoffrey.blake@arm.com 692315SN/Atemplate <class Impl> 708733Sgeoffrey.blake@arm.comstd::string 712315SN/ADefaultRename<Impl>::name() const 7210379Sandreas.hansson@arm.com{ 738733Sgeoffrey.blake@arm.com return cpu->name() + ".rename"; 748733Sgeoffrey.blake@arm.com} 758733Sgeoffrey.blake@arm.com 768733Sgeoffrey.blake@arm.comtemplate <class Impl> 779023Sgblack@eecs.umich.eduvoid 788733Sgeoffrey.blake@arm.comDefaultRename<Impl>::regStats() 798733Sgeoffrey.blake@arm.com{ 808733Sgeoffrey.blake@arm.com renameSquashCycles 818733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:SquashCycles") 828733Sgeoffrey.blake@arm.com .desc("Number of cycles rename is squashing") 838733Sgeoffrey.blake@arm.com .prereq(renameSquashCycles); 848733Sgeoffrey.blake@arm.com renameIdleCycles 858733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:IdleCycles") 868733Sgeoffrey.blake@arm.com .desc("Number of cycles rename is idle") 878733Sgeoffrey.blake@arm.com .prereq(renameIdleCycles); 888733Sgeoffrey.blake@arm.com renameBlockCycles 898733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:BlockCycles") 908733Sgeoffrey.blake@arm.com .desc("Number of cycles rename is blocking") 918733Sgeoffrey.blake@arm.com .prereq(renameBlockCycles); 928733Sgeoffrey.blake@arm.com renameSerializeStallCycles 938733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:serializeStallCycles") 948733Sgeoffrey.blake@arm.com .desc("count of cycles rename stalled for serializing inst") 958733Sgeoffrey.blake@arm.com .flags(Stats::total); 968733Sgeoffrey.blake@arm.com renameRunCycles 978733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:RunCycles") 988733Sgeoffrey.blake@arm.com .desc("Number of cycles rename is running") 998733Sgeoffrey.blake@arm.com .prereq(renameIdleCycles); 1008733Sgeoffrey.blake@arm.com renameUnblockCycles 1018733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:UnblockCycles") 1028733Sgeoffrey.blake@arm.com .desc("Number of cycles rename is unblocking") 1038733Sgeoffrey.blake@arm.com .prereq(renameUnblockCycles); 1048733Sgeoffrey.blake@arm.com renameRenamedInsts 1058733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:RenamedInsts") 1068733Sgeoffrey.blake@arm.com .desc("Number of instructions processed by rename") 1078733Sgeoffrey.blake@arm.com .prereq(renameRenamedInsts); 1088733Sgeoffrey.blake@arm.com renameSquashedInsts 1098733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:SquashedInsts") 1108733Sgeoffrey.blake@arm.com .desc("Number of squashed instructions processed by rename") 1118733Sgeoffrey.blake@arm.com .prereq(renameSquashedInsts); 1128733Sgeoffrey.blake@arm.com renameROBFullEvents 1138733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:ROBFullEvents") 1148733Sgeoffrey.blake@arm.com .desc("Number of times rename has blocked due to ROB full") 1158733Sgeoffrey.blake@arm.com .prereq(renameROBFullEvents); 1168733Sgeoffrey.blake@arm.com renameIQFullEvents 1178733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:IQFullEvents") 1188733Sgeoffrey.blake@arm.com .desc("Number of times rename has blocked due to IQ full") 1198733Sgeoffrey.blake@arm.com .prereq(renameIQFullEvents); 1208733Sgeoffrey.blake@arm.com renameLSQFullEvents 1219023Sgblack@eecs.umich.edu .name(name() + ".RENAME:LSQFullEvents") 1228733Sgeoffrey.blake@arm.com .desc("Number of times rename has blocked due to LSQ full") 1238733Sgeoffrey.blake@arm.com .prereq(renameLSQFullEvents); 1248733Sgeoffrey.blake@arm.com renameFullRegistersEvents 1258733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:FullRegisterEvents") 1268733Sgeoffrey.blake@arm.com .desc("Number of times there has been no free registers") 1278733Sgeoffrey.blake@arm.com .prereq(renameFullRegistersEvents); 1282315SN/A renameRenamedOperands 1292315SN/A .name(name() + ".RENAME:RenamedOperands") 1302315SN/A .desc("Number of destination operands rename has renamed") 1318733Sgeoffrey.blake@arm.com .prereq(renameRenamedOperands); 1328733Sgeoffrey.blake@arm.com renameRenameLookups 1338733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:RenameLookups") 1348733Sgeoffrey.blake@arm.com .desc("Number of register rename lookups that rename has made") 1358733Sgeoffrey.blake@arm.com .prereq(renameRenameLookups); 1368733Sgeoffrey.blake@arm.com renameCommittedMaps 1378733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:CommittedMaps") 1388733Sgeoffrey.blake@arm.com .desc("Number of HB maps that are committed") 1398733Sgeoffrey.blake@arm.com .prereq(renameCommittedMaps); 1408733Sgeoffrey.blake@arm.com renameUndoneMaps 1418733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:UndoneMaps") 1428733Sgeoffrey.blake@arm.com .desc("Number of HB maps that are undone due to squashing") 1432332SN/A .prereq(renameUndoneMaps); 1442332SN/A renamedSerializing 1452332SN/A .name(name() + ".RENAME:serializingInsts") 1462332SN/A .desc("count of serializing insts renamed") 1472332SN/A .flags(Stats::total) 1482315SN/A ; 1492315SN/A renamedTempSerializing 1508733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:tempSerializingInsts") 1518733Sgeoffrey.blake@arm.com .desc("count of temporary serializing insts renamed") 1522315SN/A .flags(Stats::total) 1532315SN/A ; 1542315SN/A} 1552315SN/A 1562315SN/Atemplate <class Impl> 1572315SN/Avoid 1582315SN/ADefaultRename<Impl>::setCPU(FullCPU *cpu_ptr) 1592315SN/A{ 1602315SN/A DPRINTF(Rename, "Setting CPU pointer.\n"); 1612315SN/A cpu = cpu_ptr; 1622315SN/A} 1632315SN/A 1642315SN/Atemplate <class Impl> 1658733Sgeoffrey.blake@arm.comvoid 1668733Sgeoffrey.blake@arm.comDefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1672315SN/A{ 1682315SN/A DPRINTF(Rename, "Setting time buffer pointer.\n"); 1692315SN/A timeBuffer = tb_ptr; 1702315SN/A 1712315SN/A // Setup wire to read information from time buffer, from IEW stage. 1722315SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1732315SN/A 1742315SN/A // Setup wire to read infromation from time buffer, from commit stage. 1752315SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1762315SN/A 1772315SN/A // Setup wire to write information to previous stages. 1782315SN/A toDecode = timeBuffer->getWire(0); 1792315SN/A} 1802315SN/A 1818733Sgeoffrey.blake@arm.comtemplate <class Impl> 1828733Sgeoffrey.blake@arm.comvoid 1838733Sgeoffrey.blake@arm.comDefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1848733Sgeoffrey.blake@arm.com{ 1858733Sgeoffrey.blake@arm.com DPRINTF(Rename, "Setting rename queue pointer.\n"); 1868733Sgeoffrey.blake@arm.com renameQueue = rq_ptr; 1878733Sgeoffrey.blake@arm.com 1882354SN/A // Setup wire to write information to future stages. 1898733Sgeoffrey.blake@arm.com toIEW = renameQueue->getWire(0); 1902354SN/A} 1912332SN/A 1922332SN/Atemplate <class Impl> 1932332SN/Avoid 1942315SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1958733Sgeoffrey.blake@arm.com{ 1968733Sgeoffrey.blake@arm.com DPRINTF(Rename, "Setting decode queue pointer.\n"); 1978733Sgeoffrey.blake@arm.com decodeQueue = dq_ptr; 1988733Sgeoffrey.blake@arm.com 1998733Sgeoffrey.blake@arm.com // Setup wire to get information from decode. 2008733Sgeoffrey.blake@arm.com fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2018733Sgeoffrey.blake@arm.com} 2028733Sgeoffrey.blake@arm.com 2038733Sgeoffrey.blake@arm.comtemplate <class Impl> 2042315SN/Avoid 2052315SN/ADefaultRename<Impl>::initStage() 2062315SN/A{ 2072315SN/A for (int tid=0; tid < numThreads; tid++) { 2082315SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2092683SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2108888Sgeoffrey.blake@arm.com freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2118888Sgeoffrey.blake@arm.com emptyROB[tid] = true; 2128888Sgeoffrey.blake@arm.com } 2132315SN/A 2142332SN/A // Clear these pointers so they are not accidentally used in 2152332SN/A // non-initialization code. 2162332SN/A iew_ptr = NULL; 2172315SN/A commit_ptr = NULL; 2188733Sgeoffrey.blake@arm.com} 2198733Sgeoffrey.blake@arm.com 2202315SN/Atemplate<class Impl> 2218733Sgeoffrey.blake@arm.comvoid 2222315SN/ADefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr) 2232315SN/A{ 2242332SN/A DPRINTF(Rename, "Setting active threads list pointer.\n"); 2258733Sgeoffrey.blake@arm.com activeThreads = at_ptr; 2268733Sgeoffrey.blake@arm.com} 2272732SN/A 2282315SN/A 2292315SN/Atemplate <class Impl> 2302315SN/Avoid 2312315SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2322315SN/A{ 2332315SN/A DPRINTF(Rename, "Setting rename map pointers.\n"); 2342332SN/A 2358733Sgeoffrey.blake@arm.com for (int i=0; i<numThreads; i++) { 2368733Sgeoffrey.blake@arm.com renameMap[i] = &rm_ptr[i]; 2372332SN/A } 2388733Sgeoffrey.blake@arm.com} 2398733Sgeoffrey.blake@arm.com 2408733Sgeoffrey.blake@arm.comtemplate <class Impl> 2412332SN/Avoid 2429023Sgblack@eecs.umich.eduDefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2439023Sgblack@eecs.umich.edu{ 2448733Sgeoffrey.blake@arm.com DPRINTF(Rename, "Setting free list pointer.\n"); 2458733Sgeoffrey.blake@arm.com freeList = fl_ptr; 2468733Sgeoffrey.blake@arm.com} 24712749Sgiacomo.travaglini@arm.com 24812749Sgiacomo.travaglini@arm.comtemplate<class Impl> 24912749Sgiacomo.travaglini@arm.comvoid 25012749Sgiacomo.travaglini@arm.comDefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2512679SN/A{ 25212749Sgiacomo.travaglini@arm.com DPRINTF(Rename, "Setting scoreboard pointer.\n"); 25312749Sgiacomo.travaglini@arm.com scoreboard = _scoreboard; 25412749Sgiacomo.travaglini@arm.com} 2552315SN/A 25612749Sgiacomo.travaglini@arm.comtemplate <class Impl> 25712749Sgiacomo.travaglini@arm.comvoid 2582315SN/ADefaultRename<Impl>::squash(unsigned tid) 2598733Sgeoffrey.blake@arm.com{ 2608733Sgeoffrey.blake@arm.com DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 2618733Sgeoffrey.blake@arm.com 2628733Sgeoffrey.blake@arm.com // Clear the stall signal if rename was blocked or unblocking before. 2638733Sgeoffrey.blake@arm.com // If it still needs to block, the blocking should happen the next 2648733Sgeoffrey.blake@arm.com // cycle and there should be space to hold everything due to the squash. 2658733Sgeoffrey.blake@arm.com if (renameStatus[tid] == Blocked || 2668733Sgeoffrey.blake@arm.com renameStatus[tid] == Unblocking || 2678733Sgeoffrey.blake@arm.com renameStatus[tid] == SerializeStall) { 2688733Sgeoffrey.blake@arm.com#if !FULL_SYSTEM 2692315SN/A // In syscall emulation, we can have both a block and a squash due 2708733Sgeoffrey.blake@arm.com // to a syscall in the same cycle. This would cause both signals to 2718733Sgeoffrey.blake@arm.com // be high. This shouldn't happen in full system. 2722315SN/A if (toDecode->renameBlock[tid]) { 2738733Sgeoffrey.blake@arm.com toDecode->renameBlock[tid] = 0; 2748733Sgeoffrey.blake@arm.com } else { 2758733Sgeoffrey.blake@arm.com toDecode->renameUnblock[tid] = 1; 2768733Sgeoffrey.blake@arm.com } 2778733Sgeoffrey.blake@arm.com#else 2788733Sgeoffrey.blake@arm.com toDecode->renameUnblock[tid] = 1; 2798733Sgeoffrey.blake@arm.com#endif 2808733Sgeoffrey.blake@arm.com serializeInst[tid] = NULL; 2818733Sgeoffrey.blake@arm.com } 2828733Sgeoffrey.blake@arm.com 2838733Sgeoffrey.blake@arm.com // Set the status to Squashing. 28412749Sgiacomo.travaglini@arm.com renameStatus[tid] = Squashing; 2858733Sgeoffrey.blake@arm.com 2868733Sgeoffrey.blake@arm.com // Clear the skid buffer in case it has any data in it. 2878733Sgeoffrey.blake@arm.com unsigned squashCount = 0; 2888733Sgeoffrey.blake@arm.com 2898733Sgeoffrey.blake@arm.com for (int i=0; i<fromDecode->size; i++) { 2908733Sgeoffrey.blake@arm.com if (fromDecode->insts[i]->threadNumber == tid) { 2918733Sgeoffrey.blake@arm.com fromDecode->insts[i]->squashed = true; 2928733Sgeoffrey.blake@arm.com wroteToTimeBuffer = true; 2938733Sgeoffrey.blake@arm.com squashCount++; 2948733Sgeoffrey.blake@arm.com } 2958733Sgeoffrey.blake@arm.com } 2968733Sgeoffrey.blake@arm.com 2978733Sgeoffrey.blake@arm.com insts[tid].clear(); 2988733Sgeoffrey.blake@arm.com 2998733Sgeoffrey.blake@arm.com // Clear the skid buffer in case it has any data in it. 3008733Sgeoffrey.blake@arm.com skidBuffer[tid].clear(); 3018733Sgeoffrey.blake@arm.com 3028733Sgeoffrey.blake@arm.com doSquash(tid); 30310417Sandreas.hansson@arm.com} 3048733Sgeoffrey.blake@arm.com 3058733Sgeoffrey.blake@arm.comtemplate <class Impl> 3068733Sgeoffrey.blake@arm.comvoid 3078733Sgeoffrey.blake@arm.comDefaultRename<Impl>::tick() 3089023Sgblack@eecs.umich.edu{ 3098733Sgeoffrey.blake@arm.com // Rename will need to try to rename as many instructions as it 3108733Sgeoffrey.blake@arm.com // has bandwidth, unless it is blocked. 3118733Sgeoffrey.blake@arm.com 3128733Sgeoffrey.blake@arm.com wroteToTimeBuffer = false; 3139023Sgblack@eecs.umich.edu 3148733Sgeoffrey.blake@arm.com blockThisCycle = false; 3159023Sgblack@eecs.umich.edu 3168733Sgeoffrey.blake@arm.com bool status_change = false; 3178733Sgeoffrey.blake@arm.com 3188733Sgeoffrey.blake@arm.com toIEWIndex = 0; 3198733Sgeoffrey.blake@arm.com 3208733Sgeoffrey.blake@arm.com sortInsts(); 3218733Sgeoffrey.blake@arm.com 3228733Sgeoffrey.blake@arm.com list<unsigned>::iterator threads = (*activeThreads).begin(); 3238733Sgeoffrey.blake@arm.com 3248733Sgeoffrey.blake@arm.com // Check stall and squash signals. 3258733Sgeoffrey.blake@arm.com while (threads != (*activeThreads).end()) { 3268733Sgeoffrey.blake@arm.com unsigned tid = *threads++; 3278733Sgeoffrey.blake@arm.com 3288733Sgeoffrey.blake@arm.com DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3298733Sgeoffrey.blake@arm.com 3308733Sgeoffrey.blake@arm.com status_change = checkSignalsAndUpdate(tid) || status_change; 3318733Sgeoffrey.blake@arm.com 3328733Sgeoffrey.blake@arm.com rename(status_change, tid); 3338733Sgeoffrey.blake@arm.com } 3348733Sgeoffrey.blake@arm.com 3358733Sgeoffrey.blake@arm.com if (status_change) { 3368733Sgeoffrey.blake@arm.com updateStatus(); 3372323SN/A } 3382315SN/A 3399023Sgblack@eecs.umich.edu if (wroteToTimeBuffer) { 3409023Sgblack@eecs.umich.edu DPRINTF(Activity, "Activity this cycle.\n"); 3412315SN/A cpu->activityThisCycle(); 3428733Sgeoffrey.blake@arm.com } 3438733Sgeoffrey.blake@arm.com 3448733Sgeoffrey.blake@arm.com threads = (*activeThreads).begin(); 3452323SN/A 3468733Sgeoffrey.blake@arm.com while (threads != (*activeThreads).end()) { 3472679SN/A unsigned tid = *threads++; 3482323SN/A 3492323SN/A // If we committed this cycle then doneSeqNum will be > 0 3508733Sgeoffrey.blake@arm.com if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 3512323SN/A !fromCommit->commitInfo[tid].squash && 3522315SN/A renameStatus[tid] != Squashing) { 3538733Sgeoffrey.blake@arm.com 3548733Sgeoffrey.blake@arm.com removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 3558733Sgeoffrey.blake@arm.com tid); 3562679SN/A } 3572315SN/A } 3582315SN/A 3592315SN/A // @todo: make into updateProgress function 3602315SN/A for (int tid=0; tid < numThreads; tid++) { 3618733Sgeoffrey.blake@arm.com instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 3628733Sgeoffrey.blake@arm.com 3638733Sgeoffrey.blake@arm.com assert(instsInProgress[tid] >=0); 3648733Sgeoffrey.blake@arm.com } 3658733Sgeoffrey.blake@arm.com 3668733Sgeoffrey.blake@arm.com} 3678733Sgeoffrey.blake@arm.com 3688733Sgeoffrey.blake@arm.comtemplate<class Impl> 3698733Sgeoffrey.blake@arm.comvoid 3708733Sgeoffrey.blake@arm.comDefaultRename<Impl>::rename(bool &status_change, unsigned tid) 3718733Sgeoffrey.blake@arm.com{ 3728733Sgeoffrey.blake@arm.com // If status is Running or idle, 3738733Sgeoffrey.blake@arm.com // call renameInsts() 3742315SN/A // If status is Unblocking, 3758733Sgeoffrey.blake@arm.com // buffer any instructions coming from decode 3768733Sgeoffrey.blake@arm.com // continue trying to empty skid buffer 3778733Sgeoffrey.blake@arm.com // check if stall conditions have passed 3788733Sgeoffrey.blake@arm.com 3792315SN/A if (renameStatus[tid] == Blocked) { 3808733Sgeoffrey.blake@arm.com ++renameBlockCycles; 3818733Sgeoffrey.blake@arm.com } else if (renameStatus[tid] == Squashing) { 3828733Sgeoffrey.blake@arm.com ++renameSquashCycles; 3838733Sgeoffrey.blake@arm.com } else if (renameStatus[tid] == SerializeStall) { 3848733Sgeoffrey.blake@arm.com ++renameSerializeStallCycles; 3858733Sgeoffrey.blake@arm.com } 3868733Sgeoffrey.blake@arm.com 3878733Sgeoffrey.blake@arm.com if (renameStatus[tid] == Running || 3888733Sgeoffrey.blake@arm.com renameStatus[tid] == Idle) { 3898733Sgeoffrey.blake@arm.com DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 3908733Sgeoffrey.blake@arm.com "stage.\n", tid); 3912315SN/A 3922315SN/A renameInsts(tid); 3932315SN/A } else if (renameStatus[tid] == Unblocking) { 3948733Sgeoffrey.blake@arm.com renameInsts(tid); 3952315SN/A 3968887Sgeoffrey.blake@arm.com ++renameUnblockCycles; 3978887Sgeoffrey.blake@arm.com 3988887Sgeoffrey.blake@arm.com if (validInsts()) { 3998887Sgeoffrey.blake@arm.com // Add the current inputs to the skid buffer so they can be 4008887Sgeoffrey.blake@arm.com // reprocessed when this stage unblocks. 4018887Sgeoffrey.blake@arm.com skidInsert(tid); 4028887Sgeoffrey.blake@arm.com } 4032315SN/A 4048733Sgeoffrey.blake@arm.com // If we switched over to blocking, then there's a potential for 4052315SN/A // an overall status change. 4062315SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4078793Sgblack@eecs.umich.edu } 4088793Sgblack@eecs.umich.edu} 4098793Sgblack@eecs.umich.edu 41010426Smitch.hayenga@arm.comtemplate <class Impl> 4118793Sgblack@eecs.umich.eduvoid 4128793Sgblack@eecs.umich.eduDefaultRename<Impl>::renameInsts(unsigned tid) 4138793Sgblack@eecs.umich.edu{ 4148809Sgblack@eecs.umich.edu // Instructions can be either in the skid buffer or the queue of 4158793Sgblack@eecs.umich.edu // instructions coming from decode, depending on the status. 4168793Sgblack@eecs.umich.edu int insts_available = renameStatus[tid] == Unblocking ? 4178809Sgblack@eecs.umich.edu skidBuffer[tid].size() : insts[tid].size(); 4188793Sgblack@eecs.umich.edu 4198793Sgblack@eecs.umich.edu // Check the decode queue to see if instructions are available. 4208809Sgblack@eecs.umich.edu // If there are no available instructions to rename, then do nothing. 4218809Sgblack@eecs.umich.edu if (insts_available == 0) { 4228793Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4232315SN/A tid); 4242315SN/A // Should I change status to idle? 4252332SN/A ++renameIdleCycles; 4262315SN/A return; 4272315SN/A } else if (renameStatus[tid] == Unblocking) { 4282315SN/A ++renameUnblockCycles; 4292332SN/A } else if (renameStatus[tid] == Running) { 4302332SN/A ++renameRunCycles; 4312315SN/A } 4322315SN/A 4332315SN/A DynInstPtr inst; 4348733Sgeoffrey.blake@arm.com 4358733Sgeoffrey.blake@arm.com // Will have to do a different calculation for the number of free 4362315SN/A // entries. 4372315SN/A int free_rob_entries = calcFreeROBEntries(tid); 4382315SN/A int free_iq_entries = calcFreeIQEntries(tid); 4392315SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 4402315SN/A int min_free_entries = free_rob_entries; 4412354SN/A 4422315SN/A FullSource source = ROB; 4432315SN/A 4448733Sgeoffrey.blake@arm.com if (free_iq_entries < min_free_entries) { 4452315SN/A min_free_entries = free_iq_entries; 4468733Sgeoffrey.blake@arm.com source = IQ; 4472315SN/A } 4482315SN/A 4492315SN/A if (free_lsq_entries < min_free_entries) { 4502315SN/A min_free_entries = free_lsq_entries; 4518733Sgeoffrey.blake@arm.com source = LSQ; 4522315SN/A } 4538733Sgeoffrey.blake@arm.com 4542315SN/A // Check if there's any space left. 4552315SN/A if (min_free_entries <= 0) { 4562315SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 4578733Sgeoffrey.blake@arm.com "entries.\n" 4582315SN/A "ROB has %i free entries.\n" 4598733Sgeoffrey.blake@arm.com "IQ has %i free entries.\n" 4602315SN/A "LSQ has %i free entries.\n", 4618733Sgeoffrey.blake@arm.com tid, 4628733Sgeoffrey.blake@arm.com free_rob_entries, 4638733Sgeoffrey.blake@arm.com free_iq_entries, 4642315SN/A free_lsq_entries); 4652332SN/A 4667823Ssteve.reinhardt@amd.com blockThisCycle = true; 4672315SN/A 4682732SN/A block(tid); 4692315SN/A 4702315SN/A incrFullStat(source); 4712315SN/A 4729023Sgblack@eecs.umich.edu return; 4739023Sgblack@eecs.umich.edu } else if (min_free_entries < insts_available) { 4749023Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 4752315SN/A "%i insts available, but only %i insts can be " 4762315SN/A "renamed due to ROB/IQ/LSQ limits.\n", 4772315SN/A tid, insts_available, min_free_entries); 4788733Sgeoffrey.blake@arm.com 4792315SN/A insts_available = min_free_entries; 4808733Sgeoffrey.blake@arm.com 4812315SN/A blockThisCycle = true; 48212107SRekai.GonzalezAlberquilla@arm.com 48312107SRekai.GonzalezAlberquilla@arm.com incrFullStat(source); 4848733Sgeoffrey.blake@arm.com } 4852732SN/A 48612107SRekai.GonzalezAlberquilla@arm.com InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 48712109SRekai.GonzalezAlberquilla@arm.com skidBuffer[tid] : insts[tid]; 4888733Sgeoffrey.blake@arm.com 4898733Sgeoffrey.blake@arm.com DPRINTF(Rename, "[tid:%u]: %i available instructions to " 4908733Sgeoffrey.blake@arm.com "send iew.\n", tid, insts_available); 4918733Sgeoffrey.blake@arm.com 4928733Sgeoffrey.blake@arm.com DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 49312107SRekai.GonzalezAlberquilla@arm.com "dispatched to IQ last cycle.\n", 4948733Sgeoffrey.blake@arm.com tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 4958733Sgeoffrey.blake@arm.com 4968733Sgeoffrey.blake@arm.com // Handle serializing the next instruction if necessary. 4978733Sgeoffrey.blake@arm.com if (serializeOnNextInst[tid]) { 49812107SRekai.GonzalezAlberquilla@arm.com if (emptyROB[tid] && instsInProgress[tid] == 0) { 4998733Sgeoffrey.blake@arm.com // ROB already empty; no need to serialize. 50012107SRekai.GonzalezAlberquilla@arm.com serializeOnNextInst[tid] = false; 50112107SRekai.GonzalezAlberquilla@arm.com } else if (!insts_to_rename.empty()) { 5028733Sgeoffrey.blake@arm.com insts_to_rename.front()->setSerializeBefore(); 5038733Sgeoffrey.blake@arm.com } 5048733Sgeoffrey.blake@arm.com } 50512109SRekai.GonzalezAlberquilla@arm.com 50612109SRekai.GonzalezAlberquilla@arm.com int renamed_insts = 0; 50712109SRekai.GonzalezAlberquilla@arm.com 50812109SRekai.GonzalezAlberquilla@arm.com while (insts_available > 0 && toIEWIndex < renameWidth) { 5098733Sgeoffrey.blake@arm.com DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5102732SN/A 5118733Sgeoffrey.blake@arm.com assert(!insts_to_rename.empty()); 5128733Sgeoffrey.blake@arm.com 5138733Sgeoffrey.blake@arm.com inst = insts_to_rename.front(); 5148733Sgeoffrey.blake@arm.com 5158733Sgeoffrey.blake@arm.com insts_to_rename.pop_front(); 5162732SN/A 5172732SN/A //Use skidBuffer with oldest instructions 51812107SRekai.GonzalezAlberquilla@arm.com if (renameStatus[tid] == Unblocking) { 51912107SRekai.GonzalezAlberquilla@arm.com DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 52012107SRekai.GonzalezAlberquilla@arm.com "skidBuffer\n", 52112107SRekai.GonzalezAlberquilla@arm.com tid, inst->seqNum, inst->readPC()); 52212107SRekai.GonzalezAlberquilla@arm.com } 52312107SRekai.GonzalezAlberquilla@arm.com 5242732SN/A if (inst->isSquashed()) { 5252732SN/A DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 5262732SN/A "squashed, skipping.\n", 5272732SN/A tid, inst->seqNum, inst->threadNumber,inst->readPC()); 5282732SN/A 5292732SN/A ++renameSquashedInsts; 5308733Sgeoffrey.blake@arm.com 5318733Sgeoffrey.blake@arm.com // Decrement how many instructions are available. 5322732SN/A --insts_available; 53310935Snilay@cs.wisc.edu 5342732SN/A continue; 5352732SN/A } 5362315SN/A 5372315SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 5382315SN/A "PC %#x.\n", 5398733Sgeoffrey.blake@arm.com tid, inst->seqNum, inst->readPC()); 5402332SN/A 5412332SN/A // Handle serializeAfter/serializeBefore instructions. 5428733Sgeoffrey.blake@arm.com // serializeAfter marks the next instruction as serializeBefore. 5432732SN/A // serializeBefore makes the instruction wait in rename until the ROB 5442315SN/A // is empty. 5452315SN/A if (inst->isSerializeBefore() && !inst->isSerializeHandled()) { 5462315SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 5472315SN/A 5482315SN/A if (!inst->isTempSerializeBefore()) { 5492315SN/A renamedSerializing++; 5502315SN/A inst->setSerializeHandled(); 5512315SN/A } else { 5522315SN/A renamedTempSerializing++; 5532315SN/A } 5542315SN/A 5554172Ssaidi@eecs.umich.edu // Change status over to SerializeStall so that other stages know 5564172Ssaidi@eecs.umich.edu // what this is blocked on. 5572332SN/A renameStatus[tid] = SerializeStall; 5582332SN/A 5597823Ssteve.reinhardt@amd.com serializeInst[tid] = inst; 5604172Ssaidi@eecs.umich.edu 5614172Ssaidi@eecs.umich.edu blockThisCycle = true; 5622732SN/A 5632315SN/A break; 5642315SN/A } else if (inst->isSerializeAfter() && !inst->isSerializeHandled()) { 5652315SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 5662315SN/A 5678733Sgeoffrey.blake@arm.com inst->setSerializeHandled(); 5688733Sgeoffrey.blake@arm.com 5698733Sgeoffrey.blake@arm.com serializeAfter(insts_to_rename, tid); 5708733Sgeoffrey.blake@arm.com } 5718733Sgeoffrey.blake@arm.com 5722315SN/A // Check here to make sure there are enough destination registers 5738733Sgeoffrey.blake@arm.com // to rename to. Otherwise block. 5742315SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 5752354SN/A DPRINTF(Rename, "Blocking due to lack of free " 5768733Sgeoffrey.blake@arm.com "physical registers to rename to.\n"); 5778733Sgeoffrey.blake@arm.com blockThisCycle = true; 5788733Sgeoffrey.blake@arm.com 5798733Sgeoffrey.blake@arm.com ++renameFullRegistersEvents; 5808733Sgeoffrey.blake@arm.com 5819382SAli.Saidi@ARM.com break; 5829382SAli.Saidi@ARM.com } 5838733Sgeoffrey.blake@arm.com 5842354SN/A renameSrcRegs(inst, inst->threadNumber); 5853126Sktlim@umich.edu 5869382SAli.Saidi@ARM.com renameDestRegs(inst, inst->threadNumber); 5878733Sgeoffrey.blake@arm.com 5888733Sgeoffrey.blake@arm.com ++renamed_insts; 5898733Sgeoffrey.blake@arm.com 5902356SN/A // Put instruction in rename queue. 5918733Sgeoffrey.blake@arm.com toIEW->insts[toIEWIndex] = inst; 5922354SN/A ++(toIEW->size); 5933126Sktlim@umich.edu 5942315SN/A // Increment which instruction we're on. 5952315SN/A ++toIEWIndex; 5968733Sgeoffrey.blake@arm.com 5972315SN/A ++renameRenamedInsts; 59812107SRekai.GonzalezAlberquilla@arm.com 5998733Sgeoffrey.blake@arm.com // Decrement how many instructions are available. 6002732SN/A --insts_available; 6018733Sgeoffrey.blake@arm.com } 6028733Sgeoffrey.blake@arm.com 6038733Sgeoffrey.blake@arm.com instsInProgress[tid] += renamed_insts; 60412106SRekai.GonzalezAlberquilla@arm.com 60512106SRekai.GonzalezAlberquilla@arm.com // If we wrote to the time buffer, record this. 6069913Ssteve.reinhardt@amd.com if (toIEWIndex) { 60712107SRekai.GonzalezAlberquilla@arm.com wroteToTimeBuffer = true; 60812107SRekai.GonzalezAlberquilla@arm.com } 6099913Ssteve.reinhardt@amd.com 6109913Ssteve.reinhardt@amd.com // Check if there's any instructions left that haven't yet been renamed. 61112107SRekai.GonzalezAlberquilla@arm.com // If so then block. 61212107SRekai.GonzalezAlberquilla@arm.com if (insts_available) { 6139913Ssteve.reinhardt@amd.com blockThisCycle = true; 61412109SRekai.GonzalezAlberquilla@arm.com } 61512109SRekai.GonzalezAlberquilla@arm.com 61612109SRekai.GonzalezAlberquilla@arm.com if (blockThisCycle) { 61712109SRekai.GonzalezAlberquilla@arm.com block(tid); 61812109SRekai.GonzalezAlberquilla@arm.com toDecode->renameUnblock[tid] = false; 61912109SRekai.GonzalezAlberquilla@arm.com } 62012109SRekai.GonzalezAlberquilla@arm.com} 62112109SRekai.GonzalezAlberquilla@arm.com 62212109SRekai.GonzalezAlberquilla@arm.comtemplate<class Impl> 6239920Syasuko.eckert@amd.comvoid 62412107SRekai.GonzalezAlberquilla@arm.comDefaultRename<Impl>::skidInsert(unsigned tid) 62512107SRekai.GonzalezAlberquilla@arm.com{ 6269920Syasuko.eckert@amd.com DynInstPtr inst = NULL; 6279913Ssteve.reinhardt@amd.com 62812107SRekai.GonzalezAlberquilla@arm.com while (!insts[tid].empty()) { 62912107SRekai.GonzalezAlberquilla@arm.com inst = insts[tid].front(); 6309913Ssteve.reinhardt@amd.com 63112109SRekai.GonzalezAlberquilla@arm.com insts[tid].pop_front(); 63212109SRekai.GonzalezAlberquilla@arm.com 6338733Sgeoffrey.blake@arm.com assert(tid == inst->threadNumber); 6348733Sgeoffrey.blake@arm.com 6358733Sgeoffrey.blake@arm.com DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 63612107SRekai.GonzalezAlberquilla@arm.com "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 6378733Sgeoffrey.blake@arm.com 63812106SRekai.GonzalezAlberquilla@arm.com skidBuffer[tid].push_back(inst); 63912107SRekai.GonzalezAlberquilla@arm.com } 64012106SRekai.GonzalezAlberquilla@arm.com 64110935Snilay@cs.wisc.edu if (skidBuffer[tid].size() > skidBufferMax) 64212107SRekai.GonzalezAlberquilla@arm.com panic("Skidbuffer Exceeded Max Size"); 64312107SRekai.GonzalezAlberquilla@arm.com} 64410935Snilay@cs.wisc.edu 64510935Snilay@cs.wisc.edutemplate <class Impl> 64612107SRekai.GonzalezAlberquilla@arm.comvoid 64712107SRekai.GonzalezAlberquilla@arm.comDefaultRename<Impl>::sortInsts() 64810935Snilay@cs.wisc.edu{ 64912109SRekai.GonzalezAlberquilla@arm.com int insts_from_decode = fromDecode->size; 65012109SRekai.GonzalezAlberquilla@arm.com 65112109SRekai.GonzalezAlberquilla@arm.com for (int i=0; i < numThreads; i++) 65212109SRekai.GonzalezAlberquilla@arm.com assert(insts[i].empty()); 65312109SRekai.GonzalezAlberquilla@arm.com 65412109SRekai.GonzalezAlberquilla@arm.com for (int i = 0; i < insts_from_decode; ++i) { 65512109SRekai.GonzalezAlberquilla@arm.com DynInstPtr inst = fromDecode->insts[i]; 65612109SRekai.GonzalezAlberquilla@arm.com insts[inst->threadNumber].push_back(inst); 65710935Snilay@cs.wisc.edu } 65812107SRekai.GonzalezAlberquilla@arm.com} 65912107SRekai.GonzalezAlberquilla@arm.com 66010935Snilay@cs.wisc.edutemplate<class Impl> 66110935Snilay@cs.wisc.edubool 66212107SRekai.GonzalezAlberquilla@arm.comDefaultRename<Impl>::skidsEmpty() 66310935Snilay@cs.wisc.edu{ 66412107SRekai.GonzalezAlberquilla@arm.com list<unsigned>::iterator threads = (*activeThreads).begin(); 66510935Snilay@cs.wisc.edu 6669913Ssteve.reinhardt@amd.com while (threads != (*activeThreads).end()) { 66712109SRekai.GonzalezAlberquilla@arm.com if (!skidBuffer[*threads++].empty()) 66812109SRekai.GonzalezAlberquilla@arm.com return false; 6699913Ssteve.reinhardt@amd.com } 6702732SN/A 6712732SN/A return true; 6722732SN/A} 6738733Sgeoffrey.blake@arm.com 6742732SN/Atemplate<class Impl> 6758733Sgeoffrey.blake@arm.comvoid 6762732SN/ADefaultRename<Impl>::updateStatus() 6772732SN/A{ 6788733Sgeoffrey.blake@arm.com bool any_unblocking = false; 6792732SN/A 6808733Sgeoffrey.blake@arm.com list<unsigned>::iterator threads = (*activeThreads).begin(); 6818733Sgeoffrey.blake@arm.com 6822732SN/A threads = (*activeThreads).begin(); 6832732SN/A 6842732SN/A while (threads != (*activeThreads).end()) { 6852732SN/A unsigned tid = *threads++; 6862732SN/A 6872732SN/A if (renameStatus[tid] == Unblocking) { 6882732SN/A any_unblocking = true; 6898733Sgeoffrey.blake@arm.com break; 6902732SN/A } 6918733Sgeoffrey.blake@arm.com } 6922315SN/A 6932315SN/A // Rename will have activity if it's unblocking. 6942315SN/A if (any_unblocking) { 6952315SN/A if (_status == Inactive) { 6962315SN/A _status = Active; 6972315SN/A 6982315SN/A DPRINTF(Activity, "Activating stage.\n"); 6992315SN/A 7002315SN/A cpu->activateStage(FullCPU::RenameIdx); 7012315SN/A } 7022315SN/A } else { 7032315SN/A // If it's not unblocking, then rename will not have any internal 7048733Sgeoffrey.blake@arm.com // activity. Switch it to inactive. 7052315SN/A if (_status == Active) { 7068733Sgeoffrey.blake@arm.com _status = Inactive; 7072315SN/A DPRINTF(Activity, "Deactivating stage.\n"); 7082315SN/A 7092315SN/A cpu->deactivateStage(FullCPU::RenameIdx); 7102315SN/A } 7112315SN/A } 7122315SN/A} 7132315SN/A 7142315SN/Atemplate <class Impl> 7152315SN/Abool 7162315SN/ADefaultRename<Impl>::block(unsigned tid) 7172315SN/A{ 7189944Smatt.horsnell@ARM.com DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 7199944Smatt.horsnell@ARM.com 720 // Add the current inputs onto the skid buffer, so they can be 721 // reprocessed when this stage unblocks. 722 skidInsert(tid); 723 724 // Only signal backwards to block if the previous stages do not think 725 // rename is already blocked. 726 if (renameStatus[tid] != Blocked) { 727 if (renameStatus[tid] != Unblocking) { 728 toDecode->renameBlock[tid] = true; 729 toDecode->renameUnblock[tid] = false; 730 wroteToTimeBuffer = true; 731 } 732 733 // Rename can not go from SerializeStall to Blocked, otherwise it would 734 // not know to complete the serialize stall. 735 if (renameStatus[tid] != SerializeStall) { 736 // Set status to Blocked. 737 renameStatus[tid] = Blocked; 738 return true; 739 } 740 } 741 742 return false; 743} 744 745template <class Impl> 746bool 747DefaultRename<Impl>::unblock(unsigned tid) 748{ 749 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 750 751 // Rename is done unblocking if the skid buffer is empty. 752 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 753 754 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 755 756 toDecode->renameUnblock[tid] = true; 757 wroteToTimeBuffer = true; 758 759 renameStatus[tid] = Running; 760 return true; 761 } 762 763 return false; 764} 765 766template <class Impl> 767void 768DefaultRename<Impl>::doSquash(unsigned tid) 769{ 770 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin(); 771 772 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 773 774//#if FULL_SYSTEM 775// assert(!historyBuffer[tid].empty()); 776//#else 777 // After a syscall squashes everything, the history buffer may be empty 778 // but the ROB may still be squashing instructions. 779 if (historyBuffer[tid].empty()) { 780 return; 781 } 782//#endif // FULL_SYSTEM 783 784 // Go through the most recent instructions, undoing the mappings 785 // they did and freeing up the registers. 786 while (!historyBuffer[tid].empty() && 787 (*hb_it).instSeqNum > squashed_seq_num) { 788 assert(hb_it != historyBuffer[tid].end()); 789 790 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 791 "number %i.\n", tid, (*hb_it).instSeqNum); 792 793 // Tell the rename map to set the architected register to the 794 // previous physical register that it was renamed to. 795 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 796 797 // Put the renamed physical register back on the free list. 798 freeList->addReg(hb_it->newPhysReg); 799 800 historyBuffer[tid].erase(hb_it++); 801 802 ++renameUndoneMaps; 803 } 804} 805 806template<class Impl> 807void 808DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 809{ 810 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 811 "history buffer %u (size=%i), until [sn:%lli].\n", 812 tid, tid, historyBuffer[tid].size(), inst_seq_num); 813 814 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end(); 815 816 --hb_it; 817 818 if (historyBuffer[tid].empty()) { 819 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 820 return; 821 } else if (hb_it->instSeqNum > inst_seq_num) { 822 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 823 "that a syscall happened recently.\n", tid); 824 return; 825 } 826 827 // Commit all the renames up until (and including) the committed sequence 828 // number. Some or even all of the committed instructions may not have 829 // rename histories if they did not have destination registers that were 830 // renamed. 831 while (!historyBuffer[tid].empty() && 832 hb_it != historyBuffer[tid].end() && 833 (*hb_it).instSeqNum <= inst_seq_num) { 834 835 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, sequence" 836 " number %i.\n", 837 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 838 839 freeList->addReg((*hb_it).prevPhysReg); 840 ++renameCommittedMaps; 841 842 historyBuffer[tid].erase(hb_it--); 843 } 844} 845 846template <class Impl> 847inline void 848DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 849{ 850 assert(renameMap[tid] != 0); 851 852 unsigned num_src_regs = inst->numSrcRegs(); 853 854 // Get the architectual register numbers from the source and 855 // destination operands, and redirect them to the right register. 856 // Will need to mark dependencies though. 857 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 858 RegIndex src_reg = inst->srcRegIdx(src_idx); 859 860 // Look up the source registers to get the phys. register they've 861 // been renamed to, and set the sources to those registers. 862 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg); 863 864 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 865 "physical reg %i.\n", tid, (int)src_reg, 866 (int)renamed_reg); 867 868 inst->renameSrcReg(src_idx, renamed_reg); 869 870 // See if the register is ready or not. 871 if (scoreboard->getReg(renamed_reg) == true) { 872 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 873 874 inst->markSrcRegReady(src_idx); 875 } 876 877 ++renameRenameLookups; 878 } 879} 880 881template <class Impl> 882inline void 883DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 884{ 885 typename RenameMap::RenameInfo rename_result; 886 887 unsigned num_dest_regs = inst->numDestRegs(); 888 889 // Rename the destination registers. 890 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 891 RegIndex dest_reg = inst->destRegIdx(dest_idx); 892 893 // Get the physical register that the destination will be 894 // renamed to. 895 rename_result = renameMap[tid]->rename(dest_reg); 896 897 //Mark Scoreboard entry as not ready 898 scoreboard->unsetReg(rename_result.first); 899 900 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 901 "reg %i.\n", tid, (int)dest_reg, 902 (int)rename_result.first); 903 904 // Record the rename information so that a history can be kept. 905 RenameHistory hb_entry(inst->seqNum, dest_reg, 906 rename_result.first, 907 rename_result.second); 908 909 historyBuffer[tid].push_front(hb_entry); 910 911 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, " 912 "[sn:%lli].\n",tid, 913 (*historyBuffer[tid].begin()).instSeqNum); 914 915 // Tell the instruction to rename the appropriate destination 916 // register (dest_idx) to the new physical register 917 // (rename_result.first), and record the previous physical 918 // register that the same logical register was renamed to 919 // (rename_result.second). 920 inst->renameDestReg(dest_idx, 921 rename_result.first, 922 rename_result.second); 923 924 ++renameRenamedOperands; 925 } 926} 927 928template <class Impl> 929inline int 930DefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 931{ 932 int num_free = freeEntries[tid].robEntries - 933 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 934 935 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 936 937 return num_free; 938} 939 940template <class Impl> 941inline int 942DefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 943{ 944 int num_free = freeEntries[tid].iqEntries - 945 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 946 947 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 948 949 return num_free; 950} 951 952template <class Impl> 953inline int 954DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 955{ 956 int num_free = freeEntries[tid].lsqEntries - 957 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 958 959 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 960 961 return num_free; 962} 963 964template <class Impl> 965unsigned 966DefaultRename<Impl>::validInsts() 967{ 968 unsigned inst_count = 0; 969 970 for (int i=0; i<fromDecode->size; i++) { 971 if (!fromDecode->insts[i]->squashed) 972 inst_count++; 973 } 974 975 return inst_count; 976} 977 978template <class Impl> 979void 980DefaultRename<Impl>::readStallSignals(unsigned tid) 981{ 982 if (fromIEW->iewBlock[tid]) { 983 stalls[tid].iew = true; 984 } 985 986 if (fromIEW->iewUnblock[tid]) { 987 assert(stalls[tid].iew); 988 stalls[tid].iew = false; 989 } 990 991 if (fromCommit->commitBlock[tid]) { 992 stalls[tid].commit = true; 993 } 994 995 if (fromCommit->commitUnblock[tid]) { 996 assert(stalls[tid].commit); 997 stalls[tid].commit = false; 998 } 999} 1000 1001template <class Impl> 1002bool 1003DefaultRename<Impl>::checkStall(unsigned tid) 1004{ 1005 bool ret_val = false; 1006 1007 if (stalls[tid].iew) { 1008 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1009 ret_val = true; 1010 } else if (stalls[tid].commit) { 1011 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1012 ret_val = true; 1013 } else if (calcFreeROBEntries(tid) <= 0) { 1014 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1015 ret_val = true; 1016 } else if (calcFreeIQEntries(tid) <= 0) { 1017 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1018 ret_val = true; 1019 } else if (calcFreeLSQEntries(tid) <= 0) { 1020 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1021 ret_val = true; 1022 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1023 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1024 ret_val = true; 1025 } else if (renameStatus[tid] == SerializeStall && 1026 (!emptyROB[tid] || instsInProgress[tid])) { 1027 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1028 "empty.\n", 1029 tid); 1030 ret_val = true; 1031 } 1032 1033 return ret_val; 1034} 1035 1036template <class Impl> 1037void 1038DefaultRename<Impl>::readFreeEntries(unsigned tid) 1039{ 1040 bool updated = false; 1041 if (fromIEW->iewInfo[tid].usedIQ) { 1042 freeEntries[tid].iqEntries = 1043 fromIEW->iewInfo[tid].freeIQEntries; 1044 updated = true; 1045 } 1046 1047 if (fromIEW->iewInfo[tid].usedLSQ) { 1048 freeEntries[tid].lsqEntries = 1049 fromIEW->iewInfo[tid].freeLSQEntries; 1050 updated = true; 1051 } 1052 1053 if (fromCommit->commitInfo[tid].usedROB) { 1054 freeEntries[tid].robEntries = 1055 fromCommit->commitInfo[tid].freeROBEntries; 1056 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1057 updated = true; 1058 } 1059 1060 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1061 tid, 1062 freeEntries[tid].iqEntries, 1063 freeEntries[tid].robEntries, 1064 freeEntries[tid].lsqEntries); 1065 1066 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1067 tid, instsInProgress[tid]); 1068} 1069 1070template <class Impl> 1071bool 1072DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 1073{ 1074 // Check if there's a squash signal, squash if there is 1075 // Check stall signals, block if necessary. 1076 // If status was blocked 1077 // check if stall conditions have passed 1078 // if so then go to unblocking 1079 // If status was Squashing 1080 // check if squashing is not high. Switch to running this cycle. 1081 // If status was serialize stall 1082 // check if ROB is empty and no insts are in flight to the ROB 1083 1084 readFreeEntries(tid); 1085 readStallSignals(tid); 1086 1087 if (fromCommit->commitInfo[tid].squash) { 1088 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1089 "commit.\n", tid); 1090 1091 squash(tid); 1092 1093 return true; 1094 } 1095 1096 if (fromCommit->commitInfo[tid].robSquashing) { 1097 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1098 1099 renameStatus[tid] = Squashing; 1100 1101 return true; 1102 } 1103 1104 if (checkStall(tid)) { 1105 return block(tid); 1106 } 1107 1108 if (renameStatus[tid] == Blocked) { 1109 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1110 tid); 1111 1112 renameStatus[tid] = Unblocking; 1113 1114 unblock(tid); 1115 1116 return true; 1117 } 1118 1119 if (renameStatus[tid] == Squashing) { 1120 // Switch status to running if rename isn't being told to block or 1121 // squash this cycle. 1122 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1123 tid); 1124 1125 renameStatus[tid] = Running; 1126 1127 return false; 1128 } 1129 1130 if (renameStatus[tid] == SerializeStall) { 1131 // Stall ends once the ROB is free. 1132 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1133 "unblocking.\n", tid); 1134 1135 DynInstPtr serial_inst = serializeInst[tid]; 1136 1137 renameStatus[tid] = Unblocking; 1138 1139 unblock(tid); 1140 1141 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1142 "PC %#x.\n", 1143 tid, serial_inst->seqNum, serial_inst->readPC()); 1144 1145 // Put instruction into queue here. 1146 serial_inst->clearSerializeBefore(); 1147 1148 if (!skidBuffer[tid].empty()) { 1149 skidBuffer[tid].push_front(serial_inst); 1150 } else { 1151 insts[tid].push_front(serial_inst); 1152 } 1153 1154 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1155 " Adding to front of list.", tid); 1156 1157 serializeInst[tid] = NULL; 1158 1159 return true; 1160 } 1161 1162 // If we've reached this point, we have not gotten any signals that 1163 // cause rename to change its status. Rename remains the same as before. 1164 return false; 1165} 1166 1167template<class Impl> 1168void 1169DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 1170 unsigned tid) 1171{ 1172 if (inst_list.empty()) { 1173 // Mark a bit to say that I must serialize on the next instruction. 1174 serializeOnNextInst[tid] = true; 1175 return; 1176 } 1177 1178 // Set the next instruction as serializing. 1179 inst_list.front()->setSerializeBefore(); 1180} 1181 1182template <class Impl> 1183inline void 1184DefaultRename<Impl>::incrFullStat(const FullSource &source) 1185{ 1186 switch (source) { 1187 case ROB: 1188 ++renameROBFullEvents; 1189 break; 1190 case IQ: 1191 ++renameIQFullEvents; 1192 break; 1193 case LSQ: 1194 ++renameLSQFullEvents; 1195 break; 1196 default: 1197 panic("Rename full stall stat should be incremented for a reason!"); 1198 break; 1199 } 1200} 1201 1202template <class Impl> 1203void 1204DefaultRename<Impl>::dumpHistory() 1205{ 1206 typename list<RenameHistory>::iterator buf_it; 1207 1208 for (int i = 0; i < numThreads; i++) { 1209 1210 buf_it = historyBuffer[i].begin(); 1211 1212 while (buf_it != historyBuffer[i].end()) { 1213 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1214 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1215 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1216 1217 buf_it++; 1218 } 1219 } 1220} 1221