rename_impl.hh revision 2301
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <list> 30 31#include "config/full_system.hh" 32#include "cpu/o3/rename.hh" 33 34using namespace std; 35 36template <class Impl> 37DefaultRename<Impl>::DefaultRename(Params *params) 38 : iewToRenameDelay(params->iewToRenameDelay), 39 decodeToRenameDelay(params->decodeToRenameDelay), 40 commitToRenameDelay(params->commitToRenameDelay), 41 renameWidth(params->renameWidth), 42 commitWidth(params->commitWidth), 43 numThreads(params->numberOfThreads) 44{ 45 _status = Inactive; 46 47 for (int i=0; i< numThreads; i++) { 48 renameStatus[i] = Idle; 49 50 freeEntries[i].iqEntries = 0; 51 freeEntries[i].lsqEntries = 0; 52 freeEntries[i].robEntries = 0; 53 54 stalls[i].iew = false; 55 stalls[i].commit = false; 56 serializeInst[i] = NULL; 57 58 instsInProgress[i] = 0; 59 60 emptyROB[i] = true; 61 62 serializeOnNextInst[i] = false; 63 } 64 65 // @todo: Make into a parameter. 66 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 67} 68 69template <class Impl> 70std::string 71DefaultRename<Impl>::name() const 72{ 73 return cpu->name() + ".rename"; 74} 75 76template <class Impl> 77void 78DefaultRename<Impl>::regStats() 79{ 80 renameSquashCycles 81 .name(name() + ".RENAME:SquashCycles") 82 .desc("Number of cycles rename is squashing") 83 .prereq(renameSquashCycles); 84 renameIdleCycles 85 .name(name() + ".RENAME:IdleCycles") 86 .desc("Number of cycles rename is idle") 87 .prereq(renameIdleCycles); 88 renameBlockCycles 89 .name(name() + ".RENAME:BlockCycles") 90 .desc("Number of cycles rename is blocking") 91 .prereq(renameBlockCycles); 92 renameSerializeStallCycles 93 .name(name() + ".RENAME:serializeStallCycles") 94 .desc("count of cycles rename stalled for serializing inst") 95 .flags(Stats::total); 96 renameRunCycles 97 .name(name() + ".RENAME:RunCycles") 98 .desc("Number of cycles rename is running") 99 .prereq(renameIdleCycles); 100 renameUnblockCycles 101 .name(name() + ".RENAME:UnblockCycles") 102 .desc("Number of cycles rename is unblocking") 103 .prereq(renameUnblockCycles); 104 renameRenamedInsts 105 .name(name() + ".RENAME:RenamedInsts") 106 .desc("Number of instructions processed by rename") 107 .prereq(renameRenamedInsts); 108 renameSquashedInsts 109 .name(name() + ".RENAME:SquashedInsts") 110 .desc("Number of squashed instructions processed by rename") 111 .prereq(renameSquashedInsts); 112 renameROBFullEvents 113 .name(name() + ".RENAME:ROBFullEvents") 114 .desc("Number of times rename has blocked due to ROB full") 115 .prereq(renameROBFullEvents); 116 renameIQFullEvents 117 .name(name() + ".RENAME:IQFullEvents") 118 .desc("Number of times rename has blocked due to IQ full") 119 .prereq(renameIQFullEvents); 120 renameLSQFullEvents 121 .name(name() + ".RENAME:LSQFullEvents") 122 .desc("Number of times rename has blocked due to LSQ full") 123 .prereq(renameLSQFullEvents); 124 renameFullRegistersEvents 125 .name(name() + ".RENAME:FullRegisterEvents") 126 .desc("Number of times there has been no free registers") 127 .prereq(renameFullRegistersEvents); 128 renameRenamedOperands 129 .name(name() + ".RENAME:RenamedOperands") 130 .desc("Number of destination operands rename has renamed") 131 .prereq(renameRenamedOperands); 132 renameRenameLookups 133 .name(name() + ".RENAME:RenameLookups") 134 .desc("Number of register rename lookups that rename has made") 135 .prereq(renameRenameLookups); 136 renameCommittedMaps 137 .name(name() + ".RENAME:CommittedMaps") 138 .desc("Number of HB maps that are committed") 139 .prereq(renameCommittedMaps); 140 renameUndoneMaps 141 .name(name() + ".RENAME:UndoneMaps") 142 .desc("Number of HB maps that are undone due to squashing") 143 .prereq(renameUndoneMaps); 144 renamedSerializing 145 .name(name() + ".RENAME:serializingInsts") 146 .desc("count of serializing insts renamed") 147 .flags(Stats::total) 148 ; 149 renamedTempSerializing 150 .name(name() + ".RENAME:tempSerializingInsts") 151 .desc("count of temporary serializing insts renamed") 152 .flags(Stats::total) 153 ; 154} 155 156template <class Impl> 157void 158DefaultRename<Impl>::setCPU(FullCPU *cpu_ptr) 159{ 160 DPRINTF(Rename, "Setting CPU pointer.\n"); 161 cpu = cpu_ptr; 162} 163 164template <class Impl> 165void 166DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 167{ 168 DPRINTF(Rename, "Setting time buffer pointer.\n"); 169 timeBuffer = tb_ptr; 170 171 // Setup wire to read information from time buffer, from IEW stage. 172 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 173 174 // Setup wire to read infromation from time buffer, from commit stage. 175 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 176 177 // Setup wire to write information to previous stages. 178 toDecode = timeBuffer->getWire(0); 179} 180 181template <class Impl> 182void 183DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 184{ 185 DPRINTF(Rename, "Setting rename queue pointer.\n"); 186 renameQueue = rq_ptr; 187 188 // Setup wire to write information to future stages. 189 toIEW = renameQueue->getWire(0); 190} 191 192template <class Impl> 193void 194DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 195{ 196 DPRINTF(Rename, "Setting decode queue pointer.\n"); 197 decodeQueue = dq_ptr; 198 199 // Setup wire to get information from decode. 200 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 201} 202 203template <class Impl> 204void 205DefaultRename<Impl>::initStage() 206{ 207 for (int tid=0; tid < numThreads; tid++) { 208 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 209 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 210 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 211 emptyROB[tid] = true; 212 } 213 214 // Clear these pointers so they are not accidentally used in 215 // non-initialization code. 216 iew_ptr = NULL; 217 commit_ptr = NULL; 218} 219 220template<class Impl> 221void 222DefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr) 223{ 224 DPRINTF(Rename, "Setting active threads list pointer.\n"); 225 activeThreads = at_ptr; 226} 227 228 229template <class Impl> 230void 231DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 232{ 233 DPRINTF(Rename, "Setting rename map pointers.\n"); 234 235 for (int i=0; i<numThreads; i++) { 236 renameMap[i] = &rm_ptr[i]; 237 } 238} 239 240template <class Impl> 241void 242DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 243{ 244 DPRINTF(Rename, "Setting free list pointer.\n"); 245 freeList = fl_ptr; 246} 247 248template<class Impl> 249void 250DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 251{ 252 DPRINTF(Rename, "Setting scoreboard pointer.\n"); 253 scoreboard = _scoreboard; 254} 255 256template <class Impl> 257void 258DefaultRename<Impl>::squash(unsigned tid) 259{ 260 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 261 262 // Clear the stall signal if rename was blocked or unblocking before. 263 // If it still needs to block, the blocking should happen the next 264 // cycle and there should be space to hold everything due to the squash. 265 if (renameStatus[tid] == Blocked || 266 renameStatus[tid] == Unblocking || 267 renameStatus[tid] == SerializeStall) { 268#if !FULL_SYSTEM 269 // In syscall emulation, we can have both a block and a squash due 270 // to a syscall in the same cycle. This would cause both signals to 271 // be high. This shouldn't happen in full system. 272 if (toDecode->renameBlock[tid]) { 273 toDecode->renameBlock[tid] = 0; 274 } else { 275 toDecode->renameUnblock[tid] = 1; 276 } 277#else 278 toDecode->renameUnblock[tid] = 1; 279#endif 280 serializeInst[tid] = NULL; 281 } 282 283 // Set the status to Squashing. 284 renameStatus[tid] = Squashing; 285 286 // Clear the skid buffer in case it has any data in it. 287 unsigned squashCount = 0; 288 289 for (int i=0; i<fromDecode->size; i++) { 290 if (fromDecode->insts[i]->threadNumber == tid) { 291 fromDecode->insts[i]->squashed = true; 292 wroteToTimeBuffer = true; 293 squashCount++; 294 } 295 } 296 297 insts[tid].clear(); 298 299 // Clear the skid buffer in case it has any data in it. 300 skidBuffer[tid].clear(); 301 302 doSquash(tid); 303} 304 305template <class Impl> 306void 307DefaultRename<Impl>::tick() 308{ 309 // Rename will need to try to rename as many instructions as it 310 // has bandwidth, unless it is blocked. 311 312 wroteToTimeBuffer = false; 313 314 blockThisCycle = false; 315 316 bool status_change = false; 317 318 toIEWIndex = 0; 319 320 sortInsts(); 321 322 list<unsigned>::iterator threads = (*activeThreads).begin(); 323 324 // Check stall and squash signals. 325 while (threads != (*activeThreads).end()) { 326 unsigned tid = *threads++; 327 328 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 329 330 status_change = checkSignalsAndUpdate(tid) || status_change; 331 332 rename(status_change, tid); 333 } 334 335 if (status_change) { 336 updateStatus(); 337 } 338 339 if (wroteToTimeBuffer) { 340 DPRINTF(Activity, "Activity this cycle.\n"); 341 cpu->activityThisCycle(); 342 } 343 344 threads = (*activeThreads).begin(); 345 346 while (threads != (*activeThreads).end()) { 347 unsigned tid = *threads++; 348 349 // If we committed this cycle then doneSeqNum will be > 0 350 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 351 !fromCommit->commitInfo[tid].squash && 352 renameStatus[tid] != Squashing) { 353 354 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 355 tid); 356 } 357 } 358 359 // @todo: make into updateProgress function 360 for (int tid=0; tid < numThreads; tid++) { 361 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 362 363 assert(instsInProgress[tid] >=0); 364 } 365 366} 367 368template<class Impl> 369void 370DefaultRename<Impl>::rename(bool &status_change, unsigned tid) 371{ 372 // If status is Running or idle, 373 // call renameInsts() 374 // If status is Unblocking, 375 // buffer any instructions coming from decode 376 // continue trying to empty skid buffer 377 // check if stall conditions have passed 378 379 if (renameStatus[tid] == Blocked) { 380 ++renameBlockCycles; 381 } else if (renameStatus[tid] == Squashing) { 382 ++renameSquashCycles; 383 } else if (renameStatus[tid] == SerializeStall) { 384 ++renameSerializeStallCycles; 385 } 386 387 if (renameStatus[tid] == Running || 388 renameStatus[tid] == Idle) { 389 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 390 "stage.\n", tid); 391 392 renameInsts(tid); 393 } else if (renameStatus[tid] == Unblocking) { 394 renameInsts(tid); 395 396 ++renameUnblockCycles; 397 398 if (validInsts()) { 399 // Add the current inputs to the skid buffer so they can be 400 // reprocessed when this stage unblocks. 401 skidInsert(tid); 402 } 403 404 // If we switched over to blocking, then there's a potential for 405 // an overall status change. 406 status_change = unblock(tid) || status_change || blockThisCycle; 407 } 408} 409 410template <class Impl> 411void 412DefaultRename<Impl>::renameInsts(unsigned tid) 413{ 414 // Instructions can be either in the skid buffer or the queue of 415 // instructions coming from decode, depending on the status. 416 int insts_available = renameStatus[tid] == Unblocking ? 417 skidBuffer[tid].size() : insts[tid].size(); 418 419 // Check the decode queue to see if instructions are available. 420 // If there are no available instructions to rename, then do nothing. 421 if (insts_available == 0) { 422 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 423 tid); 424 // Should I change status to idle? 425 ++renameIdleCycles; 426 return; 427 } else if (renameStatus[tid] == Unblocking) { 428 ++renameUnblockCycles; 429 } else if (renameStatus[tid] == Running) { 430 ++renameRunCycles; 431 } 432 433 DynInstPtr inst; 434 435 // Will have to do a different calculation for the number of free 436 // entries. 437 int free_rob_entries = calcFreeROBEntries(tid); 438 int free_iq_entries = calcFreeIQEntries(tid); 439 int free_lsq_entries = calcFreeLSQEntries(tid); 440 int min_free_entries = free_rob_entries; 441 442 FullSource source = ROB; 443 444 if (free_iq_entries < min_free_entries) { 445 min_free_entries = free_iq_entries; 446 source = IQ; 447 } 448 449 if (free_lsq_entries < min_free_entries) { 450 min_free_entries = free_lsq_entries; 451 source = LSQ; 452 } 453 454 // Check if there's any space left. 455 if (min_free_entries <= 0) { 456 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 457 "entries.\n" 458 "ROB has %i free entries.\n" 459 "IQ has %i free entries.\n" 460 "LSQ has %i free entries.\n", 461 tid, 462 free_rob_entries, 463 free_iq_entries, 464 free_lsq_entries); 465 466 blockThisCycle = true; 467 468 block(tid); 469 470 incrFullStat(source); 471 472 return; 473 } else if (min_free_entries < insts_available) { 474 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 475 "%i insts available, but only %i insts can be " 476 "renamed due to ROB/IQ/LSQ limits.\n", 477 tid, insts_available, min_free_entries); 478 479 insts_available = min_free_entries; 480 481 blockThisCycle = true; 482 483 incrFullStat(source); 484 } 485 486 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 487 skidBuffer[tid] : insts[tid]; 488 489 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 490 "send iew.\n", tid, insts_available); 491 492 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 493 "dispatched to IQ last cycle.\n", 494 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 495 496 // Handle serializing the next instruction if necessary. 497 if (serializeOnNextInst[tid]) { 498 if (emptyROB[tid] && instsInProgress[tid] == 0) { 499 // ROB already empty; no need to serialize. 500 serializeOnNextInst[tid] = false; 501 } else if (!insts_to_rename.empty()) { 502 insts_to_rename.front()->setSerializeBefore(); 503 } 504 } 505 506 int renamed_insts = 0; 507 508 while (insts_available > 0 && toIEWIndex < renameWidth) { 509 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 510 511 assert(!insts_to_rename.empty()); 512 513 inst = insts_to_rename.front(); 514 515 insts_to_rename.pop_front(); 516 517 //Use skidBuffer with oldest instructions 518 if (renameStatus[tid] == Unblocking) { 519 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 520 "skidBuffer\n", 521 tid, inst->seqNum, inst->readPC()); 522 } 523 524 if (inst->isSquashed()) { 525 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 526 "squashed, skipping.\n", 527 tid, inst->seqNum, inst->threadNumber,inst->readPC()); 528 529 ++renameSquashedInsts; 530 531 // Decrement how many instructions are available. 532 --insts_available; 533 534 continue; 535 } 536 537 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 538 "PC %#x.\n", 539 tid, inst->seqNum, inst->readPC()); 540 541 // Handle serializeAfter/serializeBefore instructions. 542 // serializeAfter marks the next instruction as serializeBefore. 543 // serializeBefore makes the instruction wait in rename until the ROB 544 // is empty. 545 if (inst->isSerializeBefore() && !inst->isSerializeHandled()) { 546 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 547 548 if (!inst->isTempSerializeBefore()) { 549 renamedSerializing++; 550 inst->setSerializeHandled(); 551 } else { 552 renamedTempSerializing++; 553 } 554 555 // Change status over to SerializeStall so that other stages know 556 // what this is blocked on. 557 renameStatus[tid] = SerializeStall; 558 559 serializeInst[tid] = inst; 560 561 blockThisCycle = true; 562 563 break; 564 } else if (inst->isSerializeAfter() && !inst->isSerializeHandled()) { 565 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 566 567 inst->setSerializeHandled(); 568 569 serializeAfter(insts_to_rename, tid); 570 } 571 572 // Check here to make sure there are enough destination registers 573 // to rename to. Otherwise block. 574 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 575 DPRINTF(Rename, "Blocking due to lack of free " 576 "physical registers to rename to.\n"); 577 blockThisCycle = true; 578 579 ++renameFullRegistersEvents; 580 581 break; 582 } 583 584 renameSrcRegs(inst, inst->threadNumber); 585 586 renameDestRegs(inst, inst->threadNumber); 587 588 ++renamed_insts; 589 590 // Put instruction in rename queue. 591 toIEW->insts[toIEWIndex] = inst; 592 ++(toIEW->size); 593 594 // Increment which instruction we're on. 595 ++toIEWIndex; 596 597 ++renameRenamedInsts; 598 599 // Decrement how many instructions are available. 600 --insts_available; 601 } 602 603 instsInProgress[tid] += renamed_insts; 604 605 // If we wrote to the time buffer, record this. 606 if (toIEWIndex) { 607 wroteToTimeBuffer = true; 608 } 609 610 // Check if there's any instructions left that haven't yet been renamed. 611 // If so then block. 612 if (insts_available) { 613 blockThisCycle = true; 614 } 615 616 if (blockThisCycle) { 617 block(tid); 618 toDecode->renameUnblock[tid] = false; 619 } 620} 621 622template<class Impl> 623void 624DefaultRename<Impl>::skidInsert(unsigned tid) 625{ 626 DynInstPtr inst = NULL; 627 628 while (!insts[tid].empty()) { 629 inst = insts[tid].front(); 630 631 insts[tid].pop_front(); 632 633 assert(tid == inst->threadNumber); 634 635 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 636 "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 637 638 skidBuffer[tid].push_back(inst); 639 } 640 641 if (skidBuffer[tid].size() > skidBufferMax) 642 panic("Skidbuffer Exceeded Max Size"); 643} 644 645template <class Impl> 646void 647DefaultRename<Impl>::sortInsts() 648{ 649 int insts_from_decode = fromDecode->size; 650 651 for (int i=0; i < numThreads; i++) 652 assert(insts[i].empty()); 653 654 for (int i = 0; i < insts_from_decode; ++i) { 655 DynInstPtr inst = fromDecode->insts[i]; 656 insts[inst->threadNumber].push_back(inst); 657 } 658} 659 660template<class Impl> 661bool 662DefaultRename<Impl>::skidsEmpty() 663{ 664 list<unsigned>::iterator threads = (*activeThreads).begin(); 665 666 while (threads != (*activeThreads).end()) { 667 if (!skidBuffer[*threads++].empty()) 668 return false; 669 } 670 671 return true; 672} 673 674template<class Impl> 675void 676DefaultRename<Impl>::updateStatus() 677{ 678 bool any_unblocking = false; 679 680 list<unsigned>::iterator threads = (*activeThreads).begin(); 681 682 threads = (*activeThreads).begin(); 683 684 while (threads != (*activeThreads).end()) { 685 unsigned tid = *threads++; 686 687 if (renameStatus[tid] == Unblocking) { 688 any_unblocking = true; 689 break; 690 } 691 } 692 693 // Rename will have activity if it's unblocking. 694 if (any_unblocking) { 695 if (_status == Inactive) { 696 _status = Active; 697 698 DPRINTF(Activity, "Activating stage.\n"); 699 700 cpu->activateStage(FullCPU::RenameIdx); 701 } 702 } else { 703 // If it's not unblocking, then rename will not have any internal 704 // activity. Switch it to inactive. 705 if (_status == Active) { 706 _status = Inactive; 707 DPRINTF(Activity, "Deactivating stage.\n"); 708 709 cpu->deactivateStage(FullCPU::RenameIdx); 710 } 711 } 712} 713 714template <class Impl> 715bool 716DefaultRename<Impl>::block(unsigned tid) 717{ 718 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 719 720 // Add the current inputs onto the skid buffer, so they can be 721 // reprocessed when this stage unblocks. 722 skidInsert(tid); 723 724 // Only signal backwards to block if the previous stages do not think 725 // rename is already blocked. 726 if (renameStatus[tid] != Blocked) { 727 if (renameStatus[tid] != Unblocking) { 728 toDecode->renameBlock[tid] = true; 729 toDecode->renameUnblock[tid] = false; 730 wroteToTimeBuffer = true; 731 } 732 733 // Rename can not go from SerializeStall to Blocked, otherwise it would 734 // not know to complete the serialize stall. 735 if (renameStatus[tid] != SerializeStall) { 736 // Set status to Blocked. 737 renameStatus[tid] = Blocked; 738 return true; 739 } 740 } 741 742 return false; 743} 744 745template <class Impl> 746bool 747DefaultRename<Impl>::unblock(unsigned tid) 748{ 749 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 750 751 // Rename is done unblocking if the skid buffer is empty. 752 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 753 754 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 755 756 toDecode->renameUnblock[tid] = true; 757 wroteToTimeBuffer = true; 758 759 renameStatus[tid] = Running; 760 return true; 761 } 762 763 return false; 764} 765 766template <class Impl> 767void 768DefaultRename<Impl>::doSquash(unsigned tid) 769{ 770 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin(); 771 772 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 773 774//#if FULL_SYSTEM 775// assert(!historyBuffer[tid].empty()); 776//#else 777 // After a syscall squashes everything, the history buffer may be empty 778 // but the ROB may still be squashing instructions. 779 if (historyBuffer[tid].empty()) { 780 return; 781 } 782//#endif // FULL_SYSTEM 783 784 // Go through the most recent instructions, undoing the mappings 785 // they did and freeing up the registers. 786 while (!historyBuffer[tid].empty() && 787 (*hb_it).instSeqNum > squashed_seq_num) { 788 assert(hb_it != historyBuffer[tid].end()); 789 790 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 791 "number %i.\n", tid, (*hb_it).instSeqNum); 792 793 // Tell the rename map to set the architected register to the 794 // previous physical register that it was renamed to. 795 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 796 797 // Put the renamed physical register back on the free list. 798 freeList->addReg(hb_it->newPhysReg); 799 800 historyBuffer[tid].erase(hb_it++); 801 802 ++renameUndoneMaps; 803 } 804} 805 806template<class Impl> 807void 808DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 809{ 810 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 811 "history buffer %u (size=%i), until [sn:%lli].\n", 812 tid, tid, historyBuffer[tid].size(), inst_seq_num); 813 814 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end(); 815 816 --hb_it; 817 818 if (historyBuffer[tid].empty()) { 819 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 820 return; 821 } else if (hb_it->instSeqNum > inst_seq_num) { 822 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 823 "that a syscall happened recently.\n", tid); 824 return; 825 } 826 827 // Commit all the renames up until (and including) the committed sequence 828 // number. Some or even all of the committed instructions may not have 829 // rename histories if they did not have destination registers that were 830 // renamed. 831 while (!historyBuffer[tid].empty() && 832 hb_it != historyBuffer[tid].end() && 833 (*hb_it).instSeqNum <= inst_seq_num) { 834 835 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, sequence" 836 " number %i.\n", 837 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 838 839 freeList->addReg((*hb_it).prevPhysReg); 840 ++renameCommittedMaps; 841 842 historyBuffer[tid].erase(hb_it--); 843 } 844} 845 846template <class Impl> 847inline void 848DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 849{ 850 assert(renameMap[tid] != 0); 851 852 unsigned num_src_regs = inst->numSrcRegs(); 853 854 // Get the architectual register numbers from the source and 855 // destination operands, and redirect them to the right register. 856 // Will need to mark dependencies though. 857 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 858 RegIndex src_reg = inst->srcRegIdx(src_idx); 859 860 // Look up the source registers to get the phys. register they've 861 // been renamed to, and set the sources to those registers. 862 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg); 863 864 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 865 "physical reg %i.\n", tid, (int)src_reg, 866 (int)renamed_reg); 867 868 inst->renameSrcReg(src_idx, renamed_reg); 869 870 // See if the register is ready or not. 871 if (scoreboard->getReg(renamed_reg) == true) { 872 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 873 874 inst->markSrcRegReady(src_idx); 875 } 876 877 ++renameRenameLookups; 878 } 879} 880 881template <class Impl> 882inline void 883DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 884{ 885 typename RenameMap::RenameInfo rename_result; 886 887 unsigned num_dest_regs = inst->numDestRegs(); 888 889 // Rename the destination registers. 890 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 891 RegIndex dest_reg = inst->destRegIdx(dest_idx); 892 893 // Get the physical register that the destination will be 894 // renamed to. 895 rename_result = renameMap[tid]->rename(dest_reg); 896 897 //Mark Scoreboard entry as not ready 898 scoreboard->unsetReg(rename_result.first); 899 900 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 901 "reg %i.\n", tid, (int)dest_reg, 902 (int)rename_result.first); 903 904 // Record the rename information so that a history can be kept. 905 RenameHistory hb_entry(inst->seqNum, dest_reg, 906 rename_result.first, 907 rename_result.second); 908 909 historyBuffer[tid].push_front(hb_entry); 910 911 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, " 912 "[sn:%lli].\n",tid, 913 (*historyBuffer[tid].begin()).instSeqNum); 914 915 // Tell the instruction to rename the appropriate destination 916 // register (dest_idx) to the new physical register 917 // (rename_result.first), and record the previous physical 918 // register that the same logical register was renamed to 919 // (rename_result.second). 920 inst->renameDestReg(dest_idx, 921 rename_result.first, 922 rename_result.second); 923 924 ++renameRenamedOperands; 925 } 926} 927 928template <class Impl> 929inline int 930DefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 931{ 932 int num_free = freeEntries[tid].robEntries - 933 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 934 935 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 936 937 return num_free; 938} 939 940template <class Impl> 941inline int 942DefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 943{ 944 int num_free = freeEntries[tid].iqEntries - 945 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 946 947 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 948 949 return num_free; 950} 951 952template <class Impl> 953inline int 954DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 955{ 956 int num_free = freeEntries[tid].lsqEntries - 957 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 958 959 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 960 961 return num_free; 962} 963 964template <class Impl> 965unsigned 966DefaultRename<Impl>::validInsts() 967{ 968 unsigned inst_count = 0; 969 970 for (int i=0; i<fromDecode->size; i++) { 971 if (!fromDecode->insts[i]->squashed) 972 inst_count++; 973 } 974 975 return inst_count; 976} 977 978template <class Impl> 979void 980DefaultRename<Impl>::readStallSignals(unsigned tid) 981{ 982 if (fromIEW->iewBlock[tid]) { 983 stalls[tid].iew = true; 984 } 985 986 if (fromIEW->iewUnblock[tid]) { 987 assert(stalls[tid].iew); 988 stalls[tid].iew = false; 989 } 990 991 if (fromCommit->commitBlock[tid]) { 992 stalls[tid].commit = true; 993 } 994 995 if (fromCommit->commitUnblock[tid]) { 996 assert(stalls[tid].commit); 997 stalls[tid].commit = false; 998 } 999} 1000 1001template <class Impl> 1002bool 1003DefaultRename<Impl>::checkStall(unsigned tid) 1004{ 1005 bool ret_val = false; 1006 1007 if (stalls[tid].iew) { 1008 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1009 ret_val = true; 1010 } else if (stalls[tid].commit) { 1011 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1012 ret_val = true; 1013 } else if (calcFreeROBEntries(tid) <= 0) { 1014 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1015 ret_val = true; 1016 } else if (calcFreeIQEntries(tid) <= 0) { 1017 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1018 ret_val = true; 1019 } else if (calcFreeLSQEntries(tid) <= 0) { 1020 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1021 ret_val = true; 1022 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1023 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1024 ret_val = true; 1025 } else if (renameStatus[tid] == SerializeStall && 1026 (!emptyROB[tid] || instsInProgress[tid])) { 1027 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1028 "empty.\n", 1029 tid); 1030 ret_val = true; 1031 } 1032 1033 return ret_val; 1034} 1035 1036template <class Impl> 1037void 1038DefaultRename<Impl>::readFreeEntries(unsigned tid) 1039{ 1040 bool updated = false; 1041 if (fromIEW->iewInfo[tid].usedIQ) { 1042 freeEntries[tid].iqEntries = 1043 fromIEW->iewInfo[tid].freeIQEntries; 1044 updated = true; 1045 } 1046 1047 if (fromIEW->iewInfo[tid].usedLSQ) { 1048 freeEntries[tid].lsqEntries = 1049 fromIEW->iewInfo[tid].freeLSQEntries; 1050 updated = true; 1051 } 1052 1053 if (fromCommit->commitInfo[tid].usedROB) { 1054 freeEntries[tid].robEntries = 1055 fromCommit->commitInfo[tid].freeROBEntries; 1056 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1057 updated = true; 1058 } 1059 1060 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1061 tid, 1062 freeEntries[tid].iqEntries, 1063 freeEntries[tid].robEntries, 1064 freeEntries[tid].lsqEntries); 1065 1066 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1067 tid, instsInProgress[tid]); 1068} 1069 1070template <class Impl> 1071bool 1072DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 1073{ 1074 // Check if there's a squash signal, squash if there is 1075 // Check stall signals, block if necessary. 1076 // If status was blocked 1077 // check if stall conditions have passed 1078 // if so then go to unblocking 1079 // If status was Squashing 1080 // check if squashing is not high. Switch to running this cycle. 1081 // If status was serialize stall 1082 // check if ROB is empty and no insts are in flight to the ROB 1083 1084 readFreeEntries(tid); 1085 readStallSignals(tid); 1086 1087 if (fromCommit->commitInfo[tid].squash) { 1088 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1089 "commit.\n", tid); 1090 1091 squash(tid); 1092 1093 return true; 1094 } 1095 1096 if (fromCommit->commitInfo[tid].robSquashing) { 1097 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1098 1099 renameStatus[tid] = Squashing; 1100 1101 return true; 1102 } 1103 1104 if (checkStall(tid)) { 1105 return block(tid); 1106 } 1107 1108 if (renameStatus[tid] == Blocked) { 1109 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1110 tid); 1111 1112 renameStatus[tid] = Unblocking; 1113 1114 unblock(tid); 1115 1116 return true; 1117 } 1118 1119 if (renameStatus[tid] == Squashing) { 1120 // Switch status to running if rename isn't being told to block or 1121 // squash this cycle. 1122 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1123 tid); 1124 1125 renameStatus[tid] = Running; 1126 1127 return false; 1128 } 1129 1130 if (renameStatus[tid] == SerializeStall) { 1131 // Stall ends once the ROB is free. 1132 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1133 "unblocking.\n", tid); 1134 1135 DynInstPtr serial_inst = serializeInst[tid]; 1136 1137 renameStatus[tid] = Unblocking; 1138 1139 unblock(tid); 1140 1141 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1142 "PC %#x.\n", 1143 tid, serial_inst->seqNum, serial_inst->readPC()); 1144 1145 // Put instruction into queue here. 1146 serial_inst->clearSerializeBefore(); 1147 1148 if (!skidBuffer[tid].empty()) { 1149 skidBuffer[tid].push_front(serial_inst); 1150 } else { 1151 insts[tid].push_front(serial_inst); 1152 } 1153 1154 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1155 " Adding to front of list.", tid); 1156 1157 serializeInst[tid] = NULL; 1158 1159 return true; 1160 } 1161 1162 // If we've reached this point, we have not gotten any signals that 1163 // cause rename to change its status. Rename remains the same as before. 1164 return false; 1165} 1166 1167template<class Impl> 1168void 1169DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 1170 unsigned tid) 1171{ 1172 if (inst_list.empty()) { 1173 // Mark a bit to say that I must serialize on the next instruction. 1174 serializeOnNextInst[tid] = true; 1175 return; 1176 } 1177 1178 // Set the next instruction as serializing. 1179 inst_list.front()->setSerializeBefore(); 1180} 1181 1182template <class Impl> 1183inline void 1184DefaultRename<Impl>::incrFullStat(const FullSource &source) 1185{ 1186 switch (source) { 1187 case ROB: 1188 ++renameROBFullEvents; 1189 break; 1190 case IQ: 1191 ++renameIQFullEvents; 1192 break; 1193 case LSQ: 1194 ++renameLSQFullEvents; 1195 break; 1196 default: 1197 panic("Rename full stall stat should be incremented for a reason!"); 1198 break; 1199 } 1200} 1201 1202template <class Impl> 1203void 1204DefaultRename<Impl>::dumpHistory() 1205{ 1206 typename list<RenameHistory>::iterator buf_it; 1207 1208 for (int i = 0; i < numThreads; i++) { 1209 1210 buf_it = historyBuffer[i].begin(); 1211 1212 while (buf_it != historyBuffer[i].end()) { 1213 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1214 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1215 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1216 1217 buf_it++; 1218 } 1219 } 1220} 1221