rename_impl.hh revision 12104
11689SN/A/* 210715SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2010-2012, 2014-2015 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47854SAli.Saidi@ARM.com * All rights reserved. 57854SAli.Saidi@ARM.com * 67854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147854SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422935Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_RENAME_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_RENAME_IMPL_HH__ 479944Smatt.horsnell@ARM.com 481060SN/A#include <list> 491060SN/A 503773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 516329Sgblack@eecs.umich.edu#include "arch/registers.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 531717SN/A#include "cpu/o3/rename.hh" 549913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 558232Snate@binkert.org#include "debug/Activity.hh" 568232Snate@binkert.org#include "debug/Rename.hh" 579527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 585529Snate@binkert.org#include "params/DerivO3CPU.hh" 591060SN/A 606221Snate@binkert.orgusing namespace std; 616221Snate@binkert.org 621061SN/Atemplate <class Impl> 635529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 644329Sktlim@umich.edu : cpu(_cpu), 654329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 662292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 672292SN/A commitToRenameDelay(params->commitToRenameDelay), 682292SN/A renameWidth(params->renameWidth), 692292SN/A commitWidth(params->commitWidth), 705529Snate@binkert.org numThreads(params->numThreads), 719920Syasuko.eckert@amd.com maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs 7210935Snilay@cs.wisc.edu + params->numPhysCCRegs) 731060SN/A{ 7410172Sdam.sunwoo@arm.com if (renameWidth > Impl::MaxWidth) 7510172Sdam.sunwoo@arm.com fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 7610172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 7710172Sdam.sunwoo@arm.com renameWidth, static_cast<int>(Impl::MaxWidth)); 7810172Sdam.sunwoo@arm.com 792292SN/A // @todo: Make into a parameter. 8010328Smitch.hayenga@arm.com skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 812292SN/A} 822292SN/A 832292SN/Atemplate <class Impl> 842292SN/Astd::string 852292SN/ADefaultRename<Impl>::name() const 862292SN/A{ 872292SN/A return cpu->name() + ".rename"; 881060SN/A} 891060SN/A 901061SN/Atemplate <class Impl> 911060SN/Avoid 922292SN/ADefaultRename<Impl>::regStats() 931062SN/A{ 941062SN/A renameSquashCycles 958240Snate@binkert.org .name(name() + ".SquashCycles") 961062SN/A .desc("Number of cycles rename is squashing") 971062SN/A .prereq(renameSquashCycles); 981062SN/A renameIdleCycles 998240Snate@binkert.org .name(name() + ".IdleCycles") 1001062SN/A .desc("Number of cycles rename is idle") 1011062SN/A .prereq(renameIdleCycles); 1021062SN/A renameBlockCycles 1038240Snate@binkert.org .name(name() + ".BlockCycles") 1041062SN/A .desc("Number of cycles rename is blocking") 1051062SN/A .prereq(renameBlockCycles); 1062301SN/A renameSerializeStallCycles 1078240Snate@binkert.org .name(name() + ".serializeStallCycles") 1082301SN/A .desc("count of cycles rename stalled for serializing inst") 1092301SN/A .flags(Stats::total); 1102292SN/A renameRunCycles 1118240Snate@binkert.org .name(name() + ".RunCycles") 1122292SN/A .desc("Number of cycles rename is running") 1132292SN/A .prereq(renameIdleCycles); 1141062SN/A renameUnblockCycles 1158240Snate@binkert.org .name(name() + ".UnblockCycles") 1161062SN/A .desc("Number of cycles rename is unblocking") 1171062SN/A .prereq(renameUnblockCycles); 1181062SN/A renameRenamedInsts 1198240Snate@binkert.org .name(name() + ".RenamedInsts") 1201062SN/A .desc("Number of instructions processed by rename") 1211062SN/A .prereq(renameRenamedInsts); 1221062SN/A renameSquashedInsts 1238240Snate@binkert.org .name(name() + ".SquashedInsts") 1241062SN/A .desc("Number of squashed instructions processed by rename") 1251062SN/A .prereq(renameSquashedInsts); 1261062SN/A renameROBFullEvents 1278240Snate@binkert.org .name(name() + ".ROBFullEvents") 1282292SN/A .desc("Number of times rename has blocked due to ROB full") 1291062SN/A .prereq(renameROBFullEvents); 1301062SN/A renameIQFullEvents 1318240Snate@binkert.org .name(name() + ".IQFullEvents") 1322292SN/A .desc("Number of times rename has blocked due to IQ full") 1331062SN/A .prereq(renameIQFullEvents); 13410239Sbinhpham@cs.rutgers.edu renameLQFullEvents 13510239Sbinhpham@cs.rutgers.edu .name(name() + ".LQFullEvents") 13610239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to LQ full") 13710239Sbinhpham@cs.rutgers.edu .prereq(renameLQFullEvents); 13810239Sbinhpham@cs.rutgers.edu renameSQFullEvents 13910239Sbinhpham@cs.rutgers.edu .name(name() + ".SQFullEvents") 14010239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to SQ full") 14110239Sbinhpham@cs.rutgers.edu .prereq(renameSQFullEvents); 1421062SN/A renameFullRegistersEvents 1438240Snate@binkert.org .name(name() + ".FullRegisterEvents") 1441062SN/A .desc("Number of times there has been no free registers") 1451062SN/A .prereq(renameFullRegistersEvents); 1461062SN/A renameRenamedOperands 1478240Snate@binkert.org .name(name() + ".RenamedOperands") 1481062SN/A .desc("Number of destination operands rename has renamed") 1491062SN/A .prereq(renameRenamedOperands); 1501062SN/A renameRenameLookups 1518240Snate@binkert.org .name(name() + ".RenameLookups") 1521062SN/A .desc("Number of register rename lookups that rename has made") 1531062SN/A .prereq(renameRenameLookups); 1541062SN/A renameCommittedMaps 1558240Snate@binkert.org .name(name() + ".CommittedMaps") 1561062SN/A .desc("Number of HB maps that are committed") 1571062SN/A .prereq(renameCommittedMaps); 1581062SN/A renameUndoneMaps 1598240Snate@binkert.org .name(name() + ".UndoneMaps") 1601062SN/A .desc("Number of HB maps that are undone due to squashing") 1611062SN/A .prereq(renameUndoneMaps); 1622301SN/A renamedSerializing 1638240Snate@binkert.org .name(name() + ".serializingInsts") 1642301SN/A .desc("count of serializing insts renamed") 1652301SN/A .flags(Stats::total) 1662301SN/A ; 1672301SN/A renamedTempSerializing 1688240Snate@binkert.org .name(name() + ".tempSerializingInsts") 1692301SN/A .desc("count of temporary serializing insts renamed") 1702301SN/A .flags(Stats::total) 1712301SN/A ; 1722307SN/A renameSkidInsts 1738240Snate@binkert.org .name(name() + ".skidInsts") 1742307SN/A .desc("count of insts added to the skid buffer") 1752307SN/A .flags(Stats::total) 1762307SN/A ; 1777897Shestness@cs.utexas.edu intRenameLookups 1788240Snate@binkert.org .name(name() + ".int_rename_lookups") 1797897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1807897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1817897Shestness@cs.utexas.edu fpRenameLookups 1828240Snate@binkert.org .name(name() + ".fp_rename_lookups") 1837897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1847897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 1851062SN/A} 1861062SN/A 1871062SN/Atemplate <class Impl> 1881062SN/Avoid 18911246Sradhika.jagtap@ARM.comDefaultRename<Impl>::regProbePoints() 19011246Sradhika.jagtap@ARM.com{ 19111246Sradhika.jagtap@ARM.com ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 19211246Sradhika.jagtap@ARM.com ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), 19311246Sradhika.jagtap@ARM.com "SquashInRename"); 19411246Sradhika.jagtap@ARM.com} 19511246Sradhika.jagtap@ARM.com 19611246Sradhika.jagtap@ARM.comtemplate <class Impl> 19711246Sradhika.jagtap@ARM.comvoid 1982292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1991060SN/A{ 2001060SN/A timeBuffer = tb_ptr; 2011060SN/A 2021060SN/A // Setup wire to read information from time buffer, from IEW stage. 2031060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 2041060SN/A 2051060SN/A // Setup wire to read infromation from time buffer, from commit stage. 2061060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 2071060SN/A 2081060SN/A // Setup wire to write information to previous stages. 2091060SN/A toDecode = timeBuffer->getWire(0); 2101060SN/A} 2111060SN/A 2121061SN/Atemplate <class Impl> 2131060SN/Avoid 2142292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2151060SN/A{ 2161060SN/A renameQueue = rq_ptr; 2171060SN/A 2181060SN/A // Setup wire to write information to future stages. 2191060SN/A toIEW = renameQueue->getWire(0); 2201060SN/A} 2211060SN/A 2221061SN/Atemplate <class Impl> 2231060SN/Avoid 2242292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2251060SN/A{ 2261060SN/A decodeQueue = dq_ptr; 2271060SN/A 2281060SN/A // Setup wire to get information from decode. 2291060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2301060SN/A} 2311060SN/A 2321061SN/Atemplate <class Impl> 2331060SN/Avoid 2349427SAndreas.Sandberg@ARM.comDefaultRename<Impl>::startupStage() 2351060SN/A{ 2369444SAndreas.Sandberg@ARM.com resetStage(); 2379444SAndreas.Sandberg@ARM.com} 2389444SAndreas.Sandberg@ARM.com 2399444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2409444SAndreas.Sandberg@ARM.comvoid 2419444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::resetStage() 2429444SAndreas.Sandberg@ARM.com{ 2439444SAndreas.Sandberg@ARM.com _status = Inactive; 2449444SAndreas.Sandberg@ARM.com 2459444SAndreas.Sandberg@ARM.com resumeSerialize = false; 2469444SAndreas.Sandberg@ARM.com resumeUnblocking = false; 2479444SAndreas.Sandberg@ARM.com 2482329SN/A // Grab the number of free entries directly from the stages. 2496221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2509444SAndreas.Sandberg@ARM.com renameStatus[tid] = Idle; 2519444SAndreas.Sandberg@ARM.com 2522292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 25310239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 25410239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 2552292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2562292SN/A emptyROB[tid] = true; 2579444SAndreas.Sandberg@ARM.com 2589444SAndreas.Sandberg@ARM.com stalls[tid].iew = false; 2599444SAndreas.Sandberg@ARM.com serializeInst[tid] = NULL; 2609444SAndreas.Sandberg@ARM.com 2619444SAndreas.Sandberg@ARM.com instsInProgress[tid] = 0; 26210239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] = 0; 26310239Sbinhpham@cs.rutgers.edu storesInProgress[tid] = 0; 2649444SAndreas.Sandberg@ARM.com 2659444SAndreas.Sandberg@ARM.com serializeOnNextInst[tid] = false; 2662292SN/A } 2671060SN/A} 2681060SN/A 2692292SN/Atemplate<class Impl> 2702292SN/Avoid 2716221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2722292SN/A{ 2732292SN/A activeThreads = at_ptr; 2742292SN/A} 2752292SN/A 2762292SN/A 2771061SN/Atemplate <class Impl> 2781060SN/Avoid 2792292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2801060SN/A{ 2816221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2826221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 2831060SN/A} 2841060SN/A 2851061SN/Atemplate <class Impl> 2861060SN/Avoid 2872292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2881060SN/A{ 2892292SN/A freeList = fl_ptr; 2902292SN/A} 2911060SN/A 2922292SN/Atemplate<class Impl> 2932292SN/Avoid 2942292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2952292SN/A{ 2962292SN/A scoreboard = _scoreboard; 2971060SN/A} 2981060SN/A 2991061SN/Atemplate <class Impl> 3002863Sktlim@umich.edubool 3019444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::isDrained() const 3021060SN/A{ 3039444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3049444SAndreas.Sandberg@ARM.com if (instsInProgress[tid] != 0 || 3059444SAndreas.Sandberg@ARM.com !historyBuffer[tid].empty() || 3069444SAndreas.Sandberg@ARM.com !skidBuffer[tid].empty() || 30711650Srekai.gonzalezalberquilla@arm.com !insts[tid].empty() || 30811650Srekai.gonzalezalberquilla@arm.com (renameStatus[tid] != Idle && renameStatus[tid] != Running)) 3099444SAndreas.Sandberg@ARM.com return false; 3109444SAndreas.Sandberg@ARM.com } 3112863Sktlim@umich.edu return true; 3122316SN/A} 3131060SN/A 3142316SN/Atemplate <class Impl> 3152316SN/Avoid 3162307SN/ADefaultRename<Impl>::takeOverFrom() 3171060SN/A{ 3189444SAndreas.Sandberg@ARM.com resetStage(); 3199444SAndreas.Sandberg@ARM.com} 3201060SN/A 3219444SAndreas.Sandberg@ARM.comtemplate <class Impl> 3229444SAndreas.Sandberg@ARM.comvoid 3239444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::drainSanityCheck() const 3249444SAndreas.Sandberg@ARM.com{ 3256221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3269444SAndreas.Sandberg@ARM.com assert(historyBuffer[tid].empty()); 3279444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 3289444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 3299444SAndreas.Sandberg@ARM.com assert(instsInProgress[tid] == 0); 3302307SN/A } 3312307SN/A} 3322307SN/A 3332307SN/Atemplate <class Impl> 3342307SN/Avoid 3356221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3361858SN/A{ 3372292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3381858SN/A 3392292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3402292SN/A // If it still needs to block, the blocking should happen the next 3412292SN/A // cycle and there should be space to hold everything due to the squash. 3422292SN/A if (renameStatus[tid] == Blocked || 3433788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3442292SN/A toDecode->renameUnblock[tid] = 1; 3452698Sktlim@umich.edu 3463788Sgblack@eecs.umich.edu resumeSerialize = false; 3472301SN/A serializeInst[tid] = NULL; 3483788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3493788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3503788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3513788Sgblack@eecs.umich.edu resumeSerialize = true; 3523788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3533788Sgblack@eecs.umich.edu } else { 3543788Sgblack@eecs.umich.edu resumeSerialize = false; 3553788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3563788Sgblack@eecs.umich.edu 3573788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3583788Sgblack@eecs.umich.edu } 3592292SN/A } 3602292SN/A 3612292SN/A // Set the status to Squashing. 3622292SN/A renameStatus[tid] = Squashing; 3632292SN/A 3642329SN/A // Squash any instructions from decode. 3652292SN/A for (int i=0; i<fromDecode->size; i++) { 3662935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3672935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3682731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3692292SN/A wroteToTimeBuffer = true; 3702292SN/A } 3712935Sksewell@umich.edu 3722292SN/A } 3732292SN/A 3742935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3754632Sgblack@eecs.umich.edu // insts in them. 3763093Sksewell@umich.edu insts[tid].clear(); 3772292SN/A 3782292SN/A // Clear the skid buffer in case it has any data in it. 3793093Sksewell@umich.edu skidBuffer[tid].clear(); 3804632Sgblack@eecs.umich.edu 3812935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3822292SN/A} 3832292SN/A 3842292SN/Atemplate <class Impl> 3852292SN/Avoid 3862292SN/ADefaultRename<Impl>::tick() 3872292SN/A{ 3882292SN/A wroteToTimeBuffer = false; 3892292SN/A 3902292SN/A blockThisCycle = false; 3912292SN/A 3922292SN/A bool status_change = false; 3932292SN/A 3942292SN/A toIEWIndex = 0; 3952292SN/A 3962292SN/A sortInsts(); 3972292SN/A 3986221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3996221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4002292SN/A 4012292SN/A // Check stall and squash signals. 4023867Sbinkertn@umich.edu while (threads != end) { 4036221Snate@binkert.org ThreadID tid = *threads++; 4042292SN/A 4052292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4062292SN/A 4072292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4082292SN/A 4092292SN/A rename(status_change, tid); 4102292SN/A } 4112292SN/A 4122292SN/A if (status_change) { 4132292SN/A updateStatus(); 4142292SN/A } 4152292SN/A 4162292SN/A if (wroteToTimeBuffer) { 4172292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4182292SN/A cpu->activityThisCycle(); 4192292SN/A } 4202292SN/A 4213867Sbinkertn@umich.edu threads = activeThreads->begin(); 4222292SN/A 4233867Sbinkertn@umich.edu while (threads != end) { 4246221Snate@binkert.org ThreadID tid = *threads++; 4252292SN/A 4262292SN/A // If we committed this cycle then doneSeqNum will be > 0 4272292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4282292SN/A !fromCommit->commitInfo[tid].squash && 4292292SN/A renameStatus[tid] != Squashing) { 4302292SN/A 4312292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4322292SN/A tid); 4332292SN/A } 4342292SN/A } 4352292SN/A 4362292SN/A // @todo: make into updateProgress function 4376221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4382292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 43910239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 44010239Sbinhpham@cs.rutgers.edu storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 44110239Sbinhpham@cs.rutgers.edu assert(loadsInProgress[tid] >= 0); 44210239Sbinhpham@cs.rutgers.edu assert(storesInProgress[tid] >= 0); 4432292SN/A assert(instsInProgress[tid] >=0); 4442292SN/A } 4452292SN/A 4462292SN/A} 4472292SN/A 4482292SN/Atemplate<class Impl> 4492292SN/Avoid 4506221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4512292SN/A{ 4522292SN/A // If status is Running or idle, 4532292SN/A // call renameInsts() 4542292SN/A // If status is Unblocking, 4552292SN/A // buffer any instructions coming from decode 4562292SN/A // continue trying to empty skid buffer 4572292SN/A // check if stall conditions have passed 4582292SN/A 4592292SN/A if (renameStatus[tid] == Blocked) { 4602292SN/A ++renameBlockCycles; 4612292SN/A } else if (renameStatus[tid] == Squashing) { 4622292SN/A ++renameSquashCycles; 4632301SN/A } else if (renameStatus[tid] == SerializeStall) { 4642301SN/A ++renameSerializeStallCycles; 4653788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4663788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4673788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4683788Sgblack@eecs.umich.edu if (resumeSerialize) { 4693788Sgblack@eecs.umich.edu resumeSerialize = false; 4703788Sgblack@eecs.umich.edu block(tid); 4713788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4723788Sgblack@eecs.umich.edu } 4733798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4743798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4753798Sgblack@eecs.umich.edu block(tid); 4763798Sgblack@eecs.umich.edu resumeUnblocking = false; 4773798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4783798Sgblack@eecs.umich.edu } 4792292SN/A } 4802292SN/A 4812292SN/A if (renameStatus[tid] == Running || 4822292SN/A renameStatus[tid] == Idle) { 4832292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4842292SN/A "stage.\n", tid); 4852292SN/A 4862292SN/A renameInsts(tid); 4872292SN/A } else if (renameStatus[tid] == Unblocking) { 4882292SN/A renameInsts(tid); 4892292SN/A 4902292SN/A if (validInsts()) { 4912292SN/A // Add the current inputs to the skid buffer so they can be 4922292SN/A // reprocessed when this stage unblocks. 4932292SN/A skidInsert(tid); 4942292SN/A } 4952292SN/A 4962292SN/A // If we switched over to blocking, then there's a potential for 4972292SN/A // an overall status change. 4982292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4991858SN/A } 5001858SN/A} 5011858SN/A 5021858SN/Atemplate <class Impl> 5031858SN/Avoid 5046221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 5051858SN/A{ 5062292SN/A // Instructions can be either in the skid buffer or the queue of 5072292SN/A // instructions coming from decode, depending on the status. 5082292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5092292SN/A skidBuffer[tid].size() : insts[tid].size(); 5101858SN/A 5112292SN/A // Check the decode queue to see if instructions are available. 5122292SN/A // If there are no available instructions to rename, then do nothing. 5132292SN/A if (insts_available == 0) { 5142292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5152292SN/A tid); 5162292SN/A // Should I change status to idle? 5172292SN/A ++renameIdleCycles; 5182292SN/A return; 5192292SN/A } else if (renameStatus[tid] == Unblocking) { 5202292SN/A ++renameUnblockCycles; 5212292SN/A } else if (renameStatus[tid] == Running) { 5222292SN/A ++renameRunCycles; 5232292SN/A } 5241858SN/A 5252292SN/A DynInstPtr inst; 5262292SN/A 5272292SN/A // Will have to do a different calculation for the number of free 5282292SN/A // entries. 5292292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5302292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5312292SN/A int min_free_entries = free_rob_entries; 5322292SN/A 5332292SN/A FullSource source = ROB; 5342292SN/A 5352292SN/A if (free_iq_entries < min_free_entries) { 5362292SN/A min_free_entries = free_iq_entries; 5372292SN/A source = IQ; 5382292SN/A } 5392292SN/A 5402292SN/A // Check if there's any space left. 5412292SN/A if (min_free_entries <= 0) { 54210239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " 5432292SN/A "entries.\n" 5442292SN/A "ROB has %i free entries.\n" 54510239Sbinhpham@cs.rutgers.edu "IQ has %i free entries.\n", 5462292SN/A tid, 5472292SN/A free_rob_entries, 54810239Sbinhpham@cs.rutgers.edu free_iq_entries); 5492292SN/A 5502292SN/A blockThisCycle = true; 5512292SN/A 5522292SN/A block(tid); 5532292SN/A 5542292SN/A incrFullStat(source); 5552292SN/A 5562292SN/A return; 5572292SN/A } else if (min_free_entries < insts_available) { 5582292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5592292SN/A "%i insts available, but only %i insts can be " 5602292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5612292SN/A tid, insts_available, min_free_entries); 5622292SN/A 5632292SN/A insts_available = min_free_entries; 5642292SN/A 5652292SN/A blockThisCycle = true; 5662292SN/A 5672292SN/A incrFullStat(source); 5682292SN/A } 5692292SN/A 5702292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5712292SN/A skidBuffer[tid] : insts[tid]; 5722292SN/A 5732292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5742292SN/A "send iew.\n", tid, insts_available); 5752292SN/A 5762292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5772292SN/A "dispatched to IQ last cycle.\n", 5782292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5792292SN/A 5802292SN/A // Handle serializing the next instruction if necessary. 5812292SN/A if (serializeOnNextInst[tid]) { 5822292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5832292SN/A // ROB already empty; no need to serialize. 5842292SN/A serializeOnNextInst[tid] = false; 5852292SN/A } else if (!insts_to_rename.empty()) { 5862292SN/A insts_to_rename.front()->setSerializeBefore(); 5872292SN/A } 5882292SN/A } 5892292SN/A 5902292SN/A int renamed_insts = 0; 5912292SN/A 5922292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 5932292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5942292SN/A 5952292SN/A assert(!insts_to_rename.empty()); 5962292SN/A 5972292SN/A inst = insts_to_rename.front(); 5982292SN/A 59910239Sbinhpham@cs.rutgers.edu //For all kind of instructions, check ROB and IQ first 60010239Sbinhpham@cs.rutgers.edu //For load instruction, check LQ size and take into account the inflight loads 60110239Sbinhpham@cs.rutgers.edu //For store instruction, check SQ size and take into account the inflight stores 60210239Sbinhpham@cs.rutgers.edu 60310239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 60410933Snilay@cs.wisc.edu if (calcFreeLQEntries(tid) <= 0) { 60510933Snilay@cs.wisc.edu DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 60610933Snilay@cs.wisc.edu source = LQ; 60710933Snilay@cs.wisc.edu incrFullStat(source); 60810933Snilay@cs.wisc.edu break; 60910933Snilay@cs.wisc.edu } 61010239Sbinhpham@cs.rutgers.edu } 61110239Sbinhpham@cs.rutgers.edu 61210239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 61310933Snilay@cs.wisc.edu if (calcFreeSQEntries(tid) <= 0) { 61410933Snilay@cs.wisc.edu DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 61510933Snilay@cs.wisc.edu source = SQ; 61610933Snilay@cs.wisc.edu incrFullStat(source); 61710933Snilay@cs.wisc.edu break; 61810933Snilay@cs.wisc.edu } 61910239Sbinhpham@cs.rutgers.edu } 62010239Sbinhpham@cs.rutgers.edu 6212292SN/A insts_to_rename.pop_front(); 6222292SN/A 6232292SN/A if (renameStatus[tid] == Unblocking) { 6247720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 6257720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 6262292SN/A } 6272292SN/A 6282292SN/A if (inst->isSquashed()) { 6297720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 6307720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 6317720Sgblack@eecs.umich.edu inst->pcState()); 6322292SN/A 6332292SN/A ++renameSquashedInsts; 6342292SN/A 6352292SN/A // Decrement how many instructions are available. 6362292SN/A --insts_available; 6372292SN/A 6382292SN/A continue; 6392292SN/A } 6402292SN/A 6412292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6427720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6432292SN/A 6449531Sgeoffrey.blake@arm.com // Check here to make sure there are enough destination registers 6459531Sgeoffrey.blake@arm.com // to rename to. Otherwise block. 64610715SRekai.GonzalezAlberquilla@arm.com if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 64710715SRekai.GonzalezAlberquilla@arm.com inst->numFPDestRegs(), 64810935Snilay@cs.wisc.edu inst->numCCDestRegs())) { 6499531Sgeoffrey.blake@arm.com DPRINTF(Rename, "Blocking due to lack of free " 6509531Sgeoffrey.blake@arm.com "physical registers to rename to.\n"); 6519531Sgeoffrey.blake@arm.com blockThisCycle = true; 6529531Sgeoffrey.blake@arm.com insts_to_rename.push_front(inst); 6539531Sgeoffrey.blake@arm.com ++renameFullRegistersEvents; 6549531Sgeoffrey.blake@arm.com 6559531Sgeoffrey.blake@arm.com break; 6569531Sgeoffrey.blake@arm.com } 6579531Sgeoffrey.blake@arm.com 6582292SN/A // Handle serializeAfter/serializeBefore instructions. 6592292SN/A // serializeAfter marks the next instruction as serializeBefore. 6602292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6612292SN/A // is empty. 6622336SN/A 6632336SN/A // In this model, IPR accesses are serialize before 6642336SN/A // instructions, and store conditionals are serialize after 6652336SN/A // instructions. This is mainly due to lack of support for 6662336SN/A // out-of-order operations of either of those classes of 6672336SN/A // instructions. 6682336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6692336SN/A !inst->isSerializeHandled()) { 6702292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6712292SN/A 6722301SN/A if (!inst->isTempSerializeBefore()) { 6732301SN/A renamedSerializing++; 6742292SN/A inst->setSerializeHandled(); 6752301SN/A } else { 6762301SN/A renamedTempSerializing++; 6772301SN/A } 6782292SN/A 6792301SN/A // Change status over to SerializeStall so that other stages know 6802292SN/A // what this is blocked on. 6812301SN/A renameStatus[tid] = SerializeStall; 6822292SN/A 6832301SN/A serializeInst[tid] = inst; 6842292SN/A 6852292SN/A blockThisCycle = true; 6862292SN/A 6872292SN/A break; 6882336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6892336SN/A !inst->isSerializeHandled()) { 6902292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6912292SN/A 6922307SN/A renamedSerializing++; 6932307SN/A 6942292SN/A inst->setSerializeHandled(); 6952292SN/A 6962292SN/A serializeAfter(insts_to_rename, tid); 6972292SN/A } 6982292SN/A 6992292SN/A renameSrcRegs(inst, inst->threadNumber); 7002292SN/A 7012292SN/A renameDestRegs(inst, inst->threadNumber); 7022292SN/A 70310239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 70410239Sbinhpham@cs.rutgers.edu loadsInProgress[tid]++; 70510239Sbinhpham@cs.rutgers.edu } 70610239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 70710239Sbinhpham@cs.rutgers.edu storesInProgress[tid]++; 70810239Sbinhpham@cs.rutgers.edu } 7092292SN/A ++renamed_insts; 71011246Sradhika.jagtap@ARM.com // Notify potential listeners that source and destination registers for 71111246Sradhika.jagtap@ARM.com // this instruction have been renamed. 71211246Sradhika.jagtap@ARM.com ppRename->notify(inst); 7138471SGiacomo.Gabrielli@arm.com 7142292SN/A // Put instruction in rename queue. 7152292SN/A toIEW->insts[toIEWIndex] = inst; 7162292SN/A ++(toIEW->size); 7172292SN/A 7182292SN/A // Increment which instruction we're on. 7192292SN/A ++toIEWIndex; 7202292SN/A 7212292SN/A // Decrement how many instructions are available. 7222292SN/A --insts_available; 7232292SN/A } 7242292SN/A 7252292SN/A instsInProgress[tid] += renamed_insts; 7262307SN/A renameRenamedInsts += renamed_insts; 7272292SN/A 7282292SN/A // If we wrote to the time buffer, record this. 7292292SN/A if (toIEWIndex) { 7302292SN/A wroteToTimeBuffer = true; 7312292SN/A } 7322292SN/A 7332292SN/A // Check if there's any instructions left that haven't yet been renamed. 7342292SN/A // If so then block. 7352292SN/A if (insts_available) { 7362292SN/A blockThisCycle = true; 7372292SN/A } 7382292SN/A 7392292SN/A if (blockThisCycle) { 7402292SN/A block(tid); 7412292SN/A toDecode->renameUnblock[tid] = false; 7422292SN/A } 7432292SN/A} 7442292SN/A 7452292SN/Atemplate<class Impl> 7462292SN/Avoid 7476221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 7482292SN/A{ 7492292SN/A DynInstPtr inst = NULL; 7502292SN/A 7512292SN/A while (!insts[tid].empty()) { 7522292SN/A inst = insts[tid].front(); 7532292SN/A 7542292SN/A insts[tid].pop_front(); 7552292SN/A 7562292SN/A assert(tid == inst->threadNumber); 7572292SN/A 7587720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 7597720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 7602292SN/A 7612307SN/A ++renameSkidInsts; 7622307SN/A 7632292SN/A skidBuffer[tid].push_back(inst); 7642292SN/A } 7652292SN/A 7662292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7673798Sgblack@eecs.umich.edu { 7683798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7693798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 77011321Ssteve.reinhardt@amd.com for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7713798Sgblack@eecs.umich.edu { 7723798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7737720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 7743798Sgblack@eecs.umich.edu (*it)->seqNum); 7753798Sgblack@eecs.umich.edu } 7762292SN/A panic("Skidbuffer Exceeded Max Size"); 7773798Sgblack@eecs.umich.edu } 7782292SN/A} 7792292SN/A 7802292SN/Atemplate <class Impl> 7812292SN/Avoid 7822292SN/ADefaultRename<Impl>::sortInsts() 7832292SN/A{ 7842292SN/A int insts_from_decode = fromDecode->size; 7852292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7862292SN/A DynInstPtr inst = fromDecode->insts[i]; 7872292SN/A insts[inst->threadNumber].push_back(inst); 7889527SMatt.Horsnell@arm.com#if TRACING_ON 7899527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 7909527SMatt.Horsnell@arm.com inst->renameTick = curTick() - inst->fetchTick; 7919527SMatt.Horsnell@arm.com } 7929527SMatt.Horsnell@arm.com#endif 7932292SN/A } 7942292SN/A} 7952292SN/A 7962292SN/Atemplate<class Impl> 7972292SN/Abool 7982292SN/ADefaultRename<Impl>::skidsEmpty() 7992292SN/A{ 8006221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8016221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8022292SN/A 8033867Sbinkertn@umich.edu while (threads != end) { 8046221Snate@binkert.org ThreadID tid = *threads++; 8053867Sbinkertn@umich.edu 8063867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 8072292SN/A return false; 8082292SN/A } 8092292SN/A 8102292SN/A return true; 8112292SN/A} 8122292SN/A 8132292SN/Atemplate<class Impl> 8142292SN/Avoid 8152292SN/ADefaultRename<Impl>::updateStatus() 8162292SN/A{ 8172292SN/A bool any_unblocking = false; 8182292SN/A 8196221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8206221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8212292SN/A 8223867Sbinkertn@umich.edu while (threads != end) { 8236221Snate@binkert.org ThreadID tid = *threads++; 8242292SN/A 8252292SN/A if (renameStatus[tid] == Unblocking) { 8262292SN/A any_unblocking = true; 8272292SN/A break; 8282292SN/A } 8292292SN/A } 8302292SN/A 8312292SN/A // Rename will have activity if it's unblocking. 8322292SN/A if (any_unblocking) { 8332292SN/A if (_status == Inactive) { 8342292SN/A _status = Active; 8352292SN/A 8362292SN/A DPRINTF(Activity, "Activating stage.\n"); 8372292SN/A 8382733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8392292SN/A } 8402292SN/A } else { 8412292SN/A // If it's not unblocking, then rename will not have any internal 8422292SN/A // activity. Switch it to inactive. 8432292SN/A if (_status == Active) { 8442292SN/A _status = Inactive; 8452292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8462292SN/A 8472733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8482292SN/A } 8492292SN/A } 8502292SN/A} 8512292SN/A 8522292SN/Atemplate <class Impl> 8532292SN/Abool 8546221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8552292SN/A{ 8562292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8572292SN/A 8582292SN/A // Add the current inputs onto the skid buffer, so they can be 8592292SN/A // reprocessed when this stage unblocks. 8602292SN/A skidInsert(tid); 8612292SN/A 8622292SN/A // Only signal backwards to block if the previous stages do not think 8632292SN/A // rename is already blocked. 8642292SN/A if (renameStatus[tid] != Blocked) { 8653798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8663798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8673798Sgblack@eecs.umich.edu // stages to block. 8683798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8692292SN/A toDecode->renameBlock[tid] = true; 8702292SN/A toDecode->renameUnblock[tid] = false; 8712292SN/A wroteToTimeBuffer = true; 8722292SN/A } 8732292SN/A 8742329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8752329SN/A // it would not know to complete the serialize stall. 8762301SN/A if (renameStatus[tid] != SerializeStall) { 8772292SN/A // Set status to Blocked. 8782292SN/A renameStatus[tid] = Blocked; 8792292SN/A return true; 8802292SN/A } 8812292SN/A } 8822292SN/A 8832292SN/A return false; 8842292SN/A} 8852292SN/A 8862292SN/Atemplate <class Impl> 8872292SN/Abool 8886221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 8892292SN/A{ 8902292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8912292SN/A 8922292SN/A // Rename is done unblocking if the skid buffer is empty. 8932301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8942292SN/A 8952292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8962292SN/A 8972292SN/A toDecode->renameUnblock[tid] = true; 8982292SN/A wroteToTimeBuffer = true; 8992292SN/A 9002292SN/A renameStatus[tid] = Running; 9012292SN/A return true; 9022292SN/A } 9032292SN/A 9042292SN/A return false; 9052292SN/A} 9062292SN/A 9072292SN/Atemplate <class Impl> 9082292SN/Avoid 9096221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 9102292SN/A{ 9112980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9122980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 9132292SN/A 9141060SN/A // After a syscall squashes everything, the history buffer may be empty 9151060SN/A // but the ROB may still be squashing instructions. 9162292SN/A if (historyBuffer[tid].empty()) { 9171060SN/A return; 9181060SN/A } 9191060SN/A 9201060SN/A // Go through the most recent instructions, undoing the mappings 9211060SN/A // they did and freeing up the registers. 9222292SN/A while (!historyBuffer[tid].empty() && 9239919Ssteve.reinhardt@amd.com hb_it->instSeqNum > squashed_seq_num) { 9242292SN/A assert(hb_it != historyBuffer[tid].end()); 9251062SN/A 9262292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 9279919Ssteve.reinhardt@amd.com "number %i.\n", tid, hb_it->instSeqNum); 9281060SN/A 9299919Ssteve.reinhardt@amd.com // Undo the rename mapping only if it was really a change. 9309919Ssteve.reinhardt@amd.com // Special regs that are not really renamed (like misc regs 9319919Ssteve.reinhardt@amd.com // and the zero reg) can be recognized because the new mapping 9329919Ssteve.reinhardt@amd.com // is the same as the old one. While it would be merely a 9339919Ssteve.reinhardt@amd.com // waste of time to update the rename table, we definitely 9349919Ssteve.reinhardt@amd.com // don't want to put these on the free list. 9359919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 9369919Ssteve.reinhardt@amd.com // Tell the rename map to set the architected register to the 9379919Ssteve.reinhardt@amd.com // previous physical register that it was renamed to. 9389919Ssteve.reinhardt@amd.com renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 9391060SN/A 9409919Ssteve.reinhardt@amd.com // Put the renamed physical register back on the free list. 9419919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->newPhysReg); 9429919Ssteve.reinhardt@amd.com } 9431062SN/A 94411246Sradhika.jagtap@ARM.com // Notify potential listeners that the register mapping needs to be 94511246Sradhika.jagtap@ARM.com // removed because the instruction it was mapped to got squashed. Note 94611246Sradhika.jagtap@ARM.com // that this is done before hb_it is incremented. 94711246Sradhika.jagtap@ARM.com ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, 94811246Sradhika.jagtap@ARM.com hb_it->newPhysReg)); 94911246Sradhika.jagtap@ARM.com 9502292SN/A historyBuffer[tid].erase(hb_it++); 9511061SN/A 9521062SN/A ++renameUndoneMaps; 9531060SN/A } 9541060SN/A} 9551060SN/A 9561060SN/Atemplate<class Impl> 9571060SN/Avoid 9586221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9591060SN/A{ 9602292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9612292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9622292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9632292SN/A 9642980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9652980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9661060SN/A 9671061SN/A --hb_it; 9681060SN/A 9692292SN/A if (historyBuffer[tid].empty()) { 9702292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9712292SN/A return; 9722292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9732292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9742292SN/A "that a syscall happened recently.\n", tid); 9751060SN/A return; 9761060SN/A } 9771060SN/A 9782292SN/A // Commit all the renames up until (and including) the committed sequence 9792292SN/A // number. Some or even all of the committed instructions may not have 9802292SN/A // rename histories if they did not have destination registers that were 9812292SN/A // renamed. 9822292SN/A while (!historyBuffer[tid].empty() && 9832292SN/A hb_it != historyBuffer[tid].end() && 9849919Ssteve.reinhardt@amd.com hb_it->instSeqNum <= inst_seq_num) { 9851060SN/A 9862329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9872329SN/A "[sn:%lli].\n", 9889919Ssteve.reinhardt@amd.com tid, hb_it->prevPhysReg, hb_it->instSeqNum); 9891061SN/A 9909919Ssteve.reinhardt@amd.com // Don't free special phys regs like misc and zero regs, which 9919919Ssteve.reinhardt@amd.com // can be recognized because the new mapping is the same as 9929919Ssteve.reinhardt@amd.com // the old one. 9939919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 9949919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->prevPhysReg); 9959919Ssteve.reinhardt@amd.com } 9969919Ssteve.reinhardt@amd.com 9972292SN/A ++renameCommittedMaps; 9981061SN/A 9992292SN/A historyBuffer[tid].erase(hb_it--); 10001060SN/A } 10011060SN/A} 10021060SN/A 10031061SN/Atemplate <class Impl> 10041061SN/Ainline void 10056221Snate@binkert.orgDefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 10061061SN/A{ 10079919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 10089919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 10091061SN/A unsigned num_src_regs = inst->numSrcRegs(); 10101061SN/A 10111061SN/A // Get the architectual register numbers from the source and 10129919Ssteve.reinhardt@amd.com // operands, and redirect them to the right physical register. 10132292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 101412104Snathanael.premillieu@arm.com RegId src_reg = inst->srcRegIdx(src_idx); 101512104Snathanael.premillieu@arm.com RegIndex flat_src_reg; 10169919Ssteve.reinhardt@amd.com PhysRegIndex renamed_reg; 10179919Ssteve.reinhardt@amd.com 101812104Snathanael.premillieu@arm.com switch (src_reg.regClass) { 10199913Ssteve.reinhardt@amd.com case IntRegClass: 102012104Snathanael.premillieu@arm.com flat_src_reg = tc->flattenIntIndex(src_reg.regIdx); 102112104Snathanael.premillieu@arm.com renamed_reg = map->lookupInt(flat_src_reg); 10229919Ssteve.reinhardt@amd.com intRenameLookups++; 10239913Ssteve.reinhardt@amd.com break; 10249913Ssteve.reinhardt@amd.com 10259913Ssteve.reinhardt@amd.com case FloatRegClass: 102612104Snathanael.premillieu@arm.com flat_src_reg = tc->flattenFloatIndex(src_reg.regIdx); 102712104Snathanael.premillieu@arm.com renamed_reg = map->lookupFloat(flat_src_reg); 10289919Ssteve.reinhardt@amd.com fpRenameLookups++; 10299913Ssteve.reinhardt@amd.com break; 10309913Ssteve.reinhardt@amd.com 10319920Syasuko.eckert@amd.com case CCRegClass: 103212104Snathanael.premillieu@arm.com flat_src_reg = tc->flattenCCIndex(src_reg.regIdx); 103312104Snathanael.premillieu@arm.com renamed_reg = map->lookupCC(flat_src_reg); 10349920Syasuko.eckert@amd.com break; 10359920Syasuko.eckert@amd.com 10369913Ssteve.reinhardt@amd.com case MiscRegClass: 10379919Ssteve.reinhardt@amd.com // misc regs don't get flattened 103812104Snathanael.premillieu@arm.com flat_src_reg = src_reg.regIdx; 103912104Snathanael.premillieu@arm.com renamed_reg = map->lookupMisc(flat_src_reg); 10409913Ssteve.reinhardt@amd.com break; 10419913Ssteve.reinhardt@amd.com 10429913Ssteve.reinhardt@amd.com default: 104312104Snathanael.premillieu@arm.com panic("Invalid register class: %d.", src_reg.regClass); 10443773Sgblack@eecs.umich.edu } 10454352Sgblack@eecs.umich.edu 10469919Ssteve.reinhardt@amd.com DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), " 104712104Snathanael.premillieu@arm.com "got phys reg %i\n", tid, RegClassStrings[src_reg.regClass], 104812104Snathanael.premillieu@arm.com (int)src_reg.regIdx, (int)flat_src_reg, (int)renamed_reg); 10491061SN/A 10501061SN/A inst->renameSrcReg(src_idx, renamed_reg); 10511061SN/A 10522292SN/A // See if the register is ready or not. 10539919Ssteve.reinhardt@amd.com if (scoreboard->getReg(renamed_reg)) { 10547767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 10557767Sgblack@eecs.umich.edu tid, renamed_reg); 10561061SN/A 10571061SN/A inst->markSrcRegReady(src_idx); 10584636Sgblack@eecs.umich.edu } else { 10597767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 10607767Sgblack@eecs.umich.edu tid, renamed_reg); 10611061SN/A } 10621062SN/A 10631062SN/A ++renameRenameLookups; 10641061SN/A } 10651061SN/A} 10661061SN/A 10671061SN/Atemplate <class Impl> 10681061SN/Ainline void 10696221Snate@binkert.orgDefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 10701061SN/A{ 10719919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 10729919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 10731061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10741061SN/A 10752292SN/A // Rename the destination registers. 10762292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 107712104Snathanael.premillieu@arm.com RegId dest_reg = inst->destRegIdx(dest_idx); 107812104Snathanael.premillieu@arm.com RegIndex flat_dest_reg; 10799919Ssteve.reinhardt@amd.com typename RenameMap::RenameInfo rename_result; 10809919Ssteve.reinhardt@amd.com 108112104Snathanael.premillieu@arm.com switch (dest_reg.regClass) { 10829913Ssteve.reinhardt@amd.com case IntRegClass: 108312104Snathanael.premillieu@arm.com flat_dest_reg = tc->flattenIntIndex(dest_reg.regIdx); 108412104Snathanael.premillieu@arm.com rename_result = map->renameInt(flat_dest_reg); 10859913Ssteve.reinhardt@amd.com break; 10869913Ssteve.reinhardt@amd.com 10879913Ssteve.reinhardt@amd.com case FloatRegClass: 108812104Snathanael.premillieu@arm.com flat_dest_reg = tc->flattenFloatIndex(dest_reg.regIdx); 108912104Snathanael.premillieu@arm.com rename_result = map->renameFloat(flat_dest_reg); 10909913Ssteve.reinhardt@amd.com break; 10919913Ssteve.reinhardt@amd.com 10929920Syasuko.eckert@amd.com case CCRegClass: 109312104Snathanael.premillieu@arm.com flat_dest_reg = tc->flattenCCIndex(dest_reg.regIdx); 109412104Snathanael.premillieu@arm.com rename_result = map->renameCC(flat_dest_reg); 10959920Syasuko.eckert@amd.com break; 10969920Syasuko.eckert@amd.com 10979913Ssteve.reinhardt@amd.com case MiscRegClass: 10989919Ssteve.reinhardt@amd.com // misc regs don't get flattened 109912104Snathanael.premillieu@arm.com flat_dest_reg = dest_reg.regIdx; 110012104Snathanael.premillieu@arm.com rename_result = map->renameMisc(dest_reg.regIdx); 11019913Ssteve.reinhardt@amd.com break; 11029913Ssteve.reinhardt@amd.com 11039913Ssteve.reinhardt@amd.com default: 110412104Snathanael.premillieu@arm.com panic("Invalid register class: %d.", dest_reg.regClass); 11053773Sgblack@eecs.umich.edu } 11063773Sgblack@eecs.umich.edu 110712104Snathanael.premillieu@arm.com RegId flat_uni_dest_reg(dest_reg.regClass, flat_dest_reg); 110812104Snathanael.premillieu@arm.com 11099919Ssteve.reinhardt@amd.com inst->flattenDestReg(dest_idx, flat_uni_dest_reg); 11101061SN/A 11119919Ssteve.reinhardt@amd.com // Mark Scoreboard entry as not ready 11129916Ssteve.reinhardt@amd.com scoreboard->unsetReg(rename_result.first); 11131062SN/A 11142292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 111512104Snathanael.premillieu@arm.com "reg %i.\n", tid, (int)flat_dest_reg, 11162292SN/A (int)rename_result.first); 11171062SN/A 11182292SN/A // Record the rename information so that a history can be kept. 11199919Ssteve.reinhardt@amd.com RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, 11202292SN/A rename_result.first, 11212292SN/A rename_result.second); 11221062SN/A 11232292SN/A historyBuffer[tid].push_front(hb_entry); 11241062SN/A 11252935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 11262935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 11272935Sksewell@umich.edu historyBuffer[tid].size(), 11282292SN/A (*historyBuffer[tid].begin()).instSeqNum); 11291062SN/A 11302292SN/A // Tell the instruction to rename the appropriate destination 11312292SN/A // register (dest_idx) to the new physical register 11322292SN/A // (rename_result.first), and record the previous physical 11332292SN/A // register that the same logical register was renamed to 11342292SN/A // (rename_result.second). 11352292SN/A inst->renameDestReg(dest_idx, 11362292SN/A rename_result.first, 11372292SN/A rename_result.second); 11381062SN/A 11392292SN/A ++renameRenamedOperands; 11401061SN/A } 11411061SN/A} 11421061SN/A 11431061SN/Atemplate <class Impl> 11441061SN/Ainline int 11456221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 11461061SN/A{ 11472292SN/A int num_free = freeEntries[tid].robEntries - 11482292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11492292SN/A 11502292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 11512292SN/A 11522292SN/A return num_free; 11531061SN/A} 11541061SN/A 11551061SN/Atemplate <class Impl> 11561061SN/Ainline int 11576221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 11581061SN/A{ 11592292SN/A int num_free = freeEntries[tid].iqEntries - 11602292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11612292SN/A 11622292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11632292SN/A 11642292SN/A return num_free; 11652292SN/A} 11662292SN/A 11672292SN/Atemplate <class Impl> 11682292SN/Ainline int 116910239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 11702292SN/A{ 117110239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].lqEntries - 117210935Snilay@cs.wisc.edu (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 117310239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 117410239Sbinhpham@cs.rutgers.edu "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 117510239Sbinhpham@cs.rutgers.edu loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 117610239Sbinhpham@cs.rutgers.edu return num_free; 117710239Sbinhpham@cs.rutgers.edu} 11782292SN/A 117910239Sbinhpham@cs.rutgers.edutemplate <class Impl> 118010239Sbinhpham@cs.rutgers.eduinline int 118110239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 118210239Sbinhpham@cs.rutgers.edu{ 118310239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].sqEntries - 118410935Snilay@cs.wisc.edu (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 118510239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 118610239Sbinhpham@cs.rutgers.edu "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 118710239Sbinhpham@cs.rutgers.edu storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 118810239Sbinhpham@cs.rutgers.edu return num_free; 11892292SN/A} 11902292SN/A 11912292SN/Atemplate <class Impl> 11922292SN/Aunsigned 11932292SN/ADefaultRename<Impl>::validInsts() 11942292SN/A{ 11952292SN/A unsigned inst_count = 0; 11962292SN/A 11972292SN/A for (int i=0; i<fromDecode->size; i++) { 11982731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11992292SN/A inst_count++; 12002292SN/A } 12012292SN/A 12022292SN/A return inst_count; 12032292SN/A} 12042292SN/A 12052292SN/Atemplate <class Impl> 12062292SN/Avoid 12076221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 12082292SN/A{ 12092292SN/A if (fromIEW->iewBlock[tid]) { 12102292SN/A stalls[tid].iew = true; 12112292SN/A } 12122292SN/A 12132292SN/A if (fromIEW->iewUnblock[tid]) { 12142292SN/A assert(stalls[tid].iew); 12152292SN/A stalls[tid].iew = false; 12162292SN/A } 12172292SN/A} 12182292SN/A 12192292SN/Atemplate <class Impl> 12202292SN/Abool 12216221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 12222292SN/A{ 12232292SN/A bool ret_val = false; 12242292SN/A 12252292SN/A if (stalls[tid].iew) { 12262292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 12272292SN/A ret_val = true; 12282292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 12292292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 12302292SN/A ret_val = true; 12312292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 12322292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 12332292SN/A ret_val = true; 123410239Sbinhpham@cs.rutgers.edu } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 12352292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 12362292SN/A ret_val = true; 12372292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 12382292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 12392292SN/A ret_val = true; 12402301SN/A } else if (renameStatus[tid] == SerializeStall && 12412292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 12422301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 12432292SN/A "empty.\n", 12442292SN/A tid); 12452292SN/A ret_val = true; 12462292SN/A } 12472292SN/A 12482292SN/A return ret_val; 12492292SN/A} 12502292SN/A 12512292SN/Atemplate <class Impl> 12522292SN/Avoid 12536221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 12542292SN/A{ 12558607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedIQ) 12568607Sgblack@eecs.umich.edu freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 12572292SN/A 125810239Sbinhpham@cs.rutgers.edu if (fromIEW->iewInfo[tid].usedLSQ) { 125910239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 126010239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 126110239Sbinhpham@cs.rutgers.edu } 12622292SN/A 12632292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12642292SN/A freeEntries[tid].robEntries = 12652292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12662292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12672292SN/A } 12682292SN/A 126910239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 127010239Sbinhpham@cs.rutgers.edu "Free LQ: %i, Free SQ: %i\n", 12712292SN/A tid, 12722292SN/A freeEntries[tid].iqEntries, 12732292SN/A freeEntries[tid].robEntries, 127410239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries, 127510239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries); 12762292SN/A 12772292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12782292SN/A tid, instsInProgress[tid]); 12792292SN/A} 12802292SN/A 12812292SN/Atemplate <class Impl> 12822292SN/Abool 12836221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12842292SN/A{ 12852292SN/A // Check if there's a squash signal, squash if there is 12862292SN/A // Check stall signals, block if necessary. 12872292SN/A // If status was blocked 12882292SN/A // check if stall conditions have passed 12892292SN/A // if so then go to unblocking 12902292SN/A // If status was Squashing 12912292SN/A // check if squashing is not high. Switch to running this cycle. 12922301SN/A // If status was serialize stall 12932292SN/A // check if ROB is empty and no insts are in flight to the ROB 12942292SN/A 12952292SN/A readFreeEntries(tid); 12962292SN/A readStallSignals(tid); 12972292SN/A 12982292SN/A if (fromCommit->commitInfo[tid].squash) { 12992292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 13002292SN/A "commit.\n", tid); 13012292SN/A 13024632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 13032292SN/A 13042292SN/A return true; 13052292SN/A } 13062292SN/A 13072292SN/A if (checkStall(tid)) { 13082292SN/A return block(tid); 13092292SN/A } 13102292SN/A 13112292SN/A if (renameStatus[tid] == Blocked) { 13122292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 13132292SN/A tid); 13142292SN/A 13152292SN/A renameStatus[tid] = Unblocking; 13162292SN/A 13172292SN/A unblock(tid); 13182292SN/A 13192292SN/A return true; 13202292SN/A } 13212292SN/A 13222292SN/A if (renameStatus[tid] == Squashing) { 13232292SN/A // Switch status to running if rename isn't being told to block or 13242292SN/A // squash this cycle. 13253798Sgblack@eecs.umich.edu if (resumeSerialize) { 13263798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 13273798Sgblack@eecs.umich.edu tid); 13282292SN/A 13293798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 13303798Sgblack@eecs.umich.edu return true; 13313798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 13323798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 13333798Sgblack@eecs.umich.edu tid); 13343798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 13353798Sgblack@eecs.umich.edu return true; 13363798Sgblack@eecs.umich.edu } else { 13373788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 13383788Sgblack@eecs.umich.edu tid); 13392292SN/A 13403788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 13413788Sgblack@eecs.umich.edu return false; 13423788Sgblack@eecs.umich.edu } 13432292SN/A } 13442292SN/A 13452301SN/A if (renameStatus[tid] == SerializeStall) { 13462292SN/A // Stall ends once the ROB is free. 13472301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 13482292SN/A "unblocking.\n", tid); 13492292SN/A 13502301SN/A DynInstPtr serial_inst = serializeInst[tid]; 13512292SN/A 13522292SN/A renameStatus[tid] = Unblocking; 13532292SN/A 13542292SN/A unblock(tid); 13552292SN/A 13562292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13577720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 13582292SN/A 13592292SN/A // Put instruction into queue here. 13602301SN/A serial_inst->clearSerializeBefore(); 13612292SN/A 13622292SN/A if (!skidBuffer[tid].empty()) { 13632301SN/A skidBuffer[tid].push_front(serial_inst); 13642292SN/A } else { 13652301SN/A insts[tid].push_front(serial_inst); 13662292SN/A } 13672292SN/A 13682292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13692703Sktlim@umich.edu " Adding to front of list.\n", tid); 13702292SN/A 13712301SN/A serializeInst[tid] = NULL; 13722292SN/A 13732292SN/A return true; 13742292SN/A } 13752292SN/A 13762292SN/A // If we've reached this point, we have not gotten any signals that 13772292SN/A // cause rename to change its status. Rename remains the same as before. 13782292SN/A return false; 13791061SN/A} 13801061SN/A 13811060SN/Atemplate<class Impl> 13821060SN/Avoid 13836221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13841060SN/A{ 13852292SN/A if (inst_list.empty()) { 13862292SN/A // Mark a bit to say that I must serialize on the next instruction. 13872292SN/A serializeOnNextInst[tid] = true; 13881060SN/A return; 13891060SN/A } 13901060SN/A 13912292SN/A // Set the next instruction as serializing. 13922292SN/A inst_list.front()->setSerializeBefore(); 13932292SN/A} 13942292SN/A 13952292SN/Atemplate <class Impl> 13962292SN/Ainline void 13972292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13982292SN/A{ 13992292SN/A switch (source) { 14002292SN/A case ROB: 14012292SN/A ++renameROBFullEvents; 14022292SN/A break; 14032292SN/A case IQ: 14042292SN/A ++renameIQFullEvents; 14052292SN/A break; 140610239Sbinhpham@cs.rutgers.edu case LQ: 140710239Sbinhpham@cs.rutgers.edu ++renameLQFullEvents; 140810239Sbinhpham@cs.rutgers.edu break; 140910239Sbinhpham@cs.rutgers.edu case SQ: 141010239Sbinhpham@cs.rutgers.edu ++renameSQFullEvents; 14112292SN/A break; 14122292SN/A default: 14132292SN/A panic("Rename full stall stat should be incremented for a reason!"); 14142292SN/A break; 14151060SN/A } 14162292SN/A} 14171060SN/A 14182292SN/Atemplate <class Impl> 14192292SN/Avoid 14202292SN/ADefaultRename<Impl>::dumpHistory() 14212292SN/A{ 14222980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 14231060SN/A 14246221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 14251060SN/A 14266221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 14271060SN/A 14286221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 142912104Snathanael.premillieu@arm.com cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg: %i Old phys " 143012104Snathanael.premillieu@arm.com "reg: %i\n", (*buf_it).instSeqNum, 143112104Snathanael.premillieu@arm.com RegClassStrings[(*buf_it).archReg.regClass], 143212104Snathanael.premillieu@arm.com (*buf_it).archReg.regIdx, 14332292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 14341060SN/A 14352292SN/A buf_it++; 14361062SN/A } 14371060SN/A } 14381060SN/A} 14399944Smatt.horsnell@ARM.com 14409944Smatt.horsnell@ARM.com#endif//__CPU_O3_RENAME_IMPL_HH__ 1441