rename_impl.hh revision 12104
13901Ssaidi@eecs.umich.edu/* 23388Sgblack@eecs.umich.edu * Copyright (c) 2010-2012, 2014-2015 ARM Limited 33388Sgblack@eecs.umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 43388Sgblack@eecs.umich.edu * All rights reserved. 53388Sgblack@eecs.umich.edu * 63388Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 73388Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 83388Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 93388Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 103388Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 113388Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 123388Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 133388Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 143388Sgblack@eecs.umich.edu * 153388Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 163388Sgblack@eecs.umich.edu * All rights reserved. 173388Sgblack@eecs.umich.edu * 183388Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 193388Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 203388Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 213388Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 223388Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 233388Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 243388Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 253388Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 263388Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 273388Sgblack@eecs.umich.edu * this software without specific prior written permission. 283388Sgblack@eecs.umich.edu * 293388Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 303270SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313270SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323270SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333270SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343270SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353270SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363270SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373270SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383270SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 393270SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403270SN/A * 413270SN/A * Authors: Kevin Lim 423270SN/A * Korey Sewell 433270SN/A */ 443388Sgblack@eecs.umich.edu 453388Sgblack@eecs.umich.edu#ifndef __CPU_O3_RENAME_IMPL_HH__ 463270SN/A#define __CPU_O3_RENAME_IMPL_HH__ 473270SN/A 483270SN/A#include <list> 493270SN/A 503270SN/A#include "arch/isa_traits.hh" 513270SN/A#include "arch/registers.hh" 523270SN/A#include "config/the_isa.hh" 533270SN/A#include "cpu/o3/rename.hh" 543388Sgblack@eecs.umich.edu#include "cpu/reg_class.hh" 553388Sgblack@eecs.umich.edu#include "debug/Activity.hh" 563270SN/A#include "debug/Rename.hh" 573270SN/A#include "debug/O3PipeView.hh" 583270SN/A#include "params/DerivO3CPU.hh" 593440Sgblack@eecs.umich.edu 603270SN/Ausing namespace std; 613270SN/A 623270SN/Atemplate <class Impl> 633270SN/ADefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 643270SN/A : cpu(_cpu), 653270SN/A iewToRenameDelay(params->iewToRenameDelay), 663440Sgblack@eecs.umich.edu decodeToRenameDelay(params->decodeToRenameDelay), 673270SN/A commitToRenameDelay(params->commitToRenameDelay), 683270SN/A renameWidth(params->renameWidth), 693270SN/A commitWidth(params->commitWidth), 703270SN/A numThreads(params->numThreads), 713270SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs 723270SN/A + params->numPhysCCRegs) 733270SN/A{ 743270SN/A if (renameWidth > Impl::MaxWidth) 753270SN/A fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 763270SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 773270SN/A renameWidth, static_cast<int>(Impl::MaxWidth)); 783270SN/A 793270SN/A // @todo: Make into a parameter. 803270SN/A skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 813270SN/A} 823270SN/A 833270SN/Atemplate <class Impl> 843270SN/Astd::string 853270SN/ADefaultRename<Impl>::name() const 863270SN/A{ 873270SN/A return cpu->name() + ".rename"; 883270SN/A} 893270SN/A 903270SN/Atemplate <class Impl> 913270SN/Avoid 923270SN/ADefaultRename<Impl>::regStats() 933270SN/A{ 943835Sgblack@eecs.umich.edu renameSquashCycles 953835Sgblack@eecs.umich.edu .name(name() + ".SquashCycles") 963835Sgblack@eecs.umich.edu .desc("Number of cycles rename is squashing") 973835Sgblack@eecs.umich.edu .prereq(renameSquashCycles); 983835Sgblack@eecs.umich.edu renameIdleCycles 993835Sgblack@eecs.umich.edu .name(name() + ".IdleCycles") 1003835Sgblack@eecs.umich.edu .desc("Number of cycles rename is idle") 1013835Sgblack@eecs.umich.edu .prereq(renameIdleCycles); 1023835Sgblack@eecs.umich.edu renameBlockCycles 1033835Sgblack@eecs.umich.edu .name(name() + ".BlockCycles") 1043863Ssaidi@eecs.umich.edu .desc("Number of cycles rename is blocking") 1053835Sgblack@eecs.umich.edu .prereq(renameBlockCycles); 1063835Sgblack@eecs.umich.edu renameSerializeStallCycles 1073835Sgblack@eecs.umich.edu .name(name() + ".serializeStallCycles") 1083835Sgblack@eecs.umich.edu .desc("count of cycles rename stalled for serializing inst") 1093835Sgblack@eecs.umich.edu .flags(Stats::total); 1103835Sgblack@eecs.umich.edu renameRunCycles 1113835Sgblack@eecs.umich.edu .name(name() + ".RunCycles") 1123835Sgblack@eecs.umich.edu .desc("Number of cycles rename is running") 1133835Sgblack@eecs.umich.edu .prereq(renameIdleCycles); 1143835Sgblack@eecs.umich.edu renameUnblockCycles 1153835Sgblack@eecs.umich.edu .name(name() + ".UnblockCycles") 1163835Sgblack@eecs.umich.edu .desc("Number of cycles rename is unblocking") 1173835Sgblack@eecs.umich.edu .prereq(renameUnblockCycles); 1183835Sgblack@eecs.umich.edu renameRenamedInsts 1193835Sgblack@eecs.umich.edu .name(name() + ".RenamedInsts") 1203835Sgblack@eecs.umich.edu .desc("Number of instructions processed by rename") 1213835Sgblack@eecs.umich.edu .prereq(renameRenamedInsts); 1223835Sgblack@eecs.umich.edu renameSquashedInsts 1233835Sgblack@eecs.umich.edu .name(name() + ".SquashedInsts") 1243835Sgblack@eecs.umich.edu .desc("Number of squashed instructions processed by rename") 1253835Sgblack@eecs.umich.edu .prereq(renameSquashedInsts); 1263835Sgblack@eecs.umich.edu renameROBFullEvents 1273835Sgblack@eecs.umich.edu .name(name() + ".ROBFullEvents") 1283835Sgblack@eecs.umich.edu .desc("Number of times rename has blocked due to ROB full") 1293835Sgblack@eecs.umich.edu .prereq(renameROBFullEvents); 1303835Sgblack@eecs.umich.edu renameIQFullEvents 1313835Sgblack@eecs.umich.edu .name(name() + ".IQFullEvents") 1323835Sgblack@eecs.umich.edu .desc("Number of times rename has blocked due to IQ full") 1333835Sgblack@eecs.umich.edu .prereq(renameIQFullEvents); 1343835Sgblack@eecs.umich.edu renameLQFullEvents 1353835Sgblack@eecs.umich.edu .name(name() + ".LQFullEvents") 1363835Sgblack@eecs.umich.edu .desc("Number of times rename has blocked due to LQ full") 1373835Sgblack@eecs.umich.edu .prereq(renameLQFullEvents); 1383835Sgblack@eecs.umich.edu renameSQFullEvents 1393835Sgblack@eecs.umich.edu .name(name() + ".SQFullEvents") 1403835Sgblack@eecs.umich.edu .desc("Number of times rename has blocked due to SQ full") 1413835Sgblack@eecs.umich.edu .prereq(renameSQFullEvents); 1423835Sgblack@eecs.umich.edu renameFullRegistersEvents 1433835Sgblack@eecs.umich.edu .name(name() + ".FullRegisterEvents") 1443835Sgblack@eecs.umich.edu .desc("Number of times there has been no free registers") 1453835Sgblack@eecs.umich.edu .prereq(renameFullRegistersEvents); 1463835Sgblack@eecs.umich.edu renameRenamedOperands 1473835Sgblack@eecs.umich.edu .name(name() + ".RenamedOperands") 1483835Sgblack@eecs.umich.edu .desc("Number of destination operands rename has renamed") 1493835Sgblack@eecs.umich.edu .prereq(renameRenamedOperands); 1503835Sgblack@eecs.umich.edu renameRenameLookups 1513835Sgblack@eecs.umich.edu .name(name() + ".RenameLookups") 1523835Sgblack@eecs.umich.edu .desc("Number of register rename lookups that rename has made") 1533270SN/A .prereq(renameRenameLookups); 1543280SN/A renameCommittedMaps 1553270SN/A .name(name() + ".CommittedMaps") 1563270SN/A .desc("Number of HB maps that are committed") 1573270SN/A .prereq(renameCommittedMaps); 1583270SN/A renameUndoneMaps 1593270SN/A .name(name() + ".UndoneMaps") 1603270SN/A .desc("Number of HB maps that are undone due to squashing") 1613270SN/A .prereq(renameUndoneMaps); 1623270SN/A renamedSerializing 1633270SN/A .name(name() + ".serializingInsts") 1643270SN/A .desc("count of serializing insts renamed") 1653270SN/A .flags(Stats::total) 1663270SN/A ; 1673270SN/A renamedTempSerializing 1683270SN/A .name(name() + ".tempSerializingInsts") 1693270SN/A .desc("count of temporary serializing insts renamed") 1703270SN/A .flags(Stats::total) 1713270SN/A ; 1723270SN/A renameSkidInsts 1733270SN/A .name(name() + ".skidInsts") 1743270SN/A .desc("count of insts added to the skid buffer") 1753270SN/A .flags(Stats::total) 1763270SN/A ; 1773270SN/A intRenameLookups 1783270SN/A .name(name() + ".int_rename_lookups") 1793270SN/A .desc("Number of integer rename lookups") 1803270SN/A .prereq(intRenameLookups); 1813280SN/A fpRenameLookups 1823270SN/A .name(name() + ".fp_rename_lookups") 1833270SN/A .desc("Number of floating rename lookups") 1843270SN/A .prereq(fpRenameLookups); 1853270SN/A} 1863270SN/A 1873270SN/Atemplate <class Impl> 1883270SN/Avoid 1893270SN/ADefaultRename<Impl>::regProbePoints() 1903270SN/A{ 1913379SN/A ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 1923270SN/A ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), 1933270SN/A "SquashInRename"); 1943270SN/A} 1953379SN/A 1963270SN/Atemplate <class Impl> 1973270SN/Avoid 1983270SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1993270SN/A{ 2003270SN/A timeBuffer = tb_ptr; 2013270SN/A 2023270SN/A // Setup wire to read information from time buffer, from IEW stage. 2033270SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 2043270SN/A 2053270SN/A // Setup wire to read infromation from time buffer, from commit stage. 2063270SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 2073270SN/A 2083270SN/A // Setup wire to write information to previous stages. 2093270SN/A toDecode = timeBuffer->getWire(0); 2103270SN/A} 2113852Sgblack@eecs.umich.edu 2123852Sgblack@eecs.umich.edutemplate <class Impl> 2133852Sgblack@eecs.umich.eduvoid 2143852Sgblack@eecs.umich.eduDefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2153852Sgblack@eecs.umich.edu{ 2163852Sgblack@eecs.umich.edu renameQueue = rq_ptr; 2173852Sgblack@eecs.umich.edu 2183852Sgblack@eecs.umich.edu // Setup wire to write information to future stages. 2193852Sgblack@eecs.umich.edu toIEW = renameQueue->getWire(0); 2203852Sgblack@eecs.umich.edu} 2213852Sgblack@eecs.umich.edu 2223852Sgblack@eecs.umich.edutemplate <class Impl> 2233852Sgblack@eecs.umich.eduvoid 2243852Sgblack@eecs.umich.eduDefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2253852Sgblack@eecs.umich.edu{ 2263852Sgblack@eecs.umich.edu decodeQueue = dq_ptr; 2273852Sgblack@eecs.umich.edu 2283852Sgblack@eecs.umich.edu // Setup wire to get information from decode. 2293852Sgblack@eecs.umich.edu fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2303852Sgblack@eecs.umich.edu} 2313852Sgblack@eecs.umich.edu 2323852Sgblack@eecs.umich.edutemplate <class Impl> 2333852Sgblack@eecs.umich.eduvoid 2343852Sgblack@eecs.umich.eduDefaultRename<Impl>::startupStage() 2353852Sgblack@eecs.umich.edu{ 2363852Sgblack@eecs.umich.edu resetStage(); 2373852Sgblack@eecs.umich.edu} 2383852Sgblack@eecs.umich.edu 2393852Sgblack@eecs.umich.edutemplate <class Impl> 2403852Sgblack@eecs.umich.eduvoid 2413852Sgblack@eecs.umich.eduDefaultRename<Impl>::resetStage() 2423852Sgblack@eecs.umich.edu{ 2433852Sgblack@eecs.umich.edu _status = Inactive; 2443852Sgblack@eecs.umich.edu 2453852Sgblack@eecs.umich.edu resumeSerialize = false; 2463852Sgblack@eecs.umich.edu resumeUnblocking = false; 2473852Sgblack@eecs.umich.edu 2483852Sgblack@eecs.umich.edu // Grab the number of free entries directly from the stages. 2493852Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 2503852Sgblack@eecs.umich.edu renameStatus[tid] = Idle; 2513852Sgblack@eecs.umich.edu 2523852Sgblack@eecs.umich.edu freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2533852Sgblack@eecs.umich.edu freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 2543852Sgblack@eecs.umich.edu freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 2553852Sgblack@eecs.umich.edu freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2563852Sgblack@eecs.umich.edu emptyROB[tid] = true; 2573852Sgblack@eecs.umich.edu 2583852Sgblack@eecs.umich.edu stalls[tid].iew = false; 2593852Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 2603852Sgblack@eecs.umich.edu 2613852Sgblack@eecs.umich.edu instsInProgress[tid] = 0; 2623852Sgblack@eecs.umich.edu loadsInProgress[tid] = 0; 2633852Sgblack@eecs.umich.edu storesInProgress[tid] = 0; 2643852Sgblack@eecs.umich.edu 2653852Sgblack@eecs.umich.edu serializeOnNextInst[tid] = false; 2663852Sgblack@eecs.umich.edu } 2673852Sgblack@eecs.umich.edu} 2683852Sgblack@eecs.umich.edu 2693270SN/Atemplate<class Impl> 2703270SN/Avoid 2713270SN/ADefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2723270SN/A{ 2733270SN/A activeThreads = at_ptr; 2743270SN/A} 2753270SN/A 2763270SN/A 2773280SN/Atemplate <class Impl> 2783270SN/Avoid 2793274SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2803270SN/A{ 2813270SN/A for (ThreadID tid = 0; tid < numThreads; tid++) 2823274SN/A renameMap[tid] = &rm_ptr[tid]; 2833270SN/A} 2843280SN/A 2853270SN/Atemplate <class Impl> 2863391Sgblack@eecs.umich.eduvoid 2873391Sgblack@eecs.umich.eduDefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2883270SN/A{ 2893270SN/A freeList = fl_ptr; 2903270SN/A} 2913270SN/A 2923274SN/Atemplate<class Impl> 2933270SN/Avoid 2943280SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2953270SN/A{ 2963391Sgblack@eecs.umich.edu scoreboard = _scoreboard; 2973391Sgblack@eecs.umich.edu} 2983270SN/A 2993270SN/Atemplate <class Impl> 3003270SN/Abool 3013270SN/ADefaultRename<Impl>::isDrained() const 3023274SN/A{ 3033270SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3043280SN/A if (instsInProgress[tid] != 0 || 3053270SN/A !historyBuffer[tid].empty() || 3063391Sgblack@eecs.umich.edu !skidBuffer[tid].empty() || 3073391Sgblack@eecs.umich.edu !insts[tid].empty() || 3083270SN/A (renameStatus[tid] != Idle && renameStatus[tid] != Running)) 3093270SN/A return false; 3103270SN/A } 3113270SN/A return true; 3123274SN/A} 3133270SN/A 3143280SN/Atemplate <class Impl> 3153270SN/Avoid 3163391Sgblack@eecs.umich.eduDefaultRename<Impl>::takeOverFrom() 3173391Sgblack@eecs.umich.edu{ 3183270SN/A resetStage(); 3193270SN/A} 3203270SN/A 3213270SN/Atemplate <class Impl> 3223274SN/Avoid 3233270SN/ADefaultRename<Impl>::drainSanityCheck() const 3243280SN/A{ 3253270SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3263391Sgblack@eecs.umich.edu assert(historyBuffer[tid].empty()); 3273391Sgblack@eecs.umich.edu assert(insts[tid].empty()); 3283270SN/A assert(skidBuffer[tid].empty()); 3293270SN/A assert(instsInProgress[tid] == 0); 3303270SN/A } 3313270SN/A} 3323274SN/A 3333270SN/Atemplate <class Impl> 3343280SN/Avoid 3353270SN/ADefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3363391Sgblack@eecs.umich.edu{ 3373391Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3383270SN/A 3393270SN/A // Clear the stall signal if rename was blocked or unblocking before. 3403270SN/A // If it still needs to block, the blocking should happen the next 3413270SN/A // cycle and there should be space to hold everything due to the squash. 3423274SN/A if (renameStatus[tid] == Blocked || 3433270SN/A renameStatus[tid] == Unblocking) { 3443280SN/A toDecode->renameUnblock[tid] = 1; 3453270SN/A 3463391Sgblack@eecs.umich.edu resumeSerialize = false; 3473391Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3483270SN/A } else if (renameStatus[tid] == SerializeStall) { 3493270SN/A if (serializeInst[tid]->seqNum <= squash_seq_num) { 3503270SN/A DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3513270SN/A resumeSerialize = true; 3523274SN/A assert(serializeInst[tid]); 3533270SN/A } else { 3543280SN/A resumeSerialize = false; 3553270SN/A toDecode->renameUnblock[tid] = 1; 3563391Sgblack@eecs.umich.edu 3573391Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3583270SN/A } 3593270SN/A } 3603270SN/A 3613270SN/A // Set the status to Squashing. 3623835Sgblack@eecs.umich.edu renameStatus[tid] = Squashing; 3633835Sgblack@eecs.umich.edu 3643835Sgblack@eecs.umich.edu // Squash any instructions from decode. 3653835Sgblack@eecs.umich.edu for (int i=0; i<fromDecode->size; i++) { 3663835Sgblack@eecs.umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3673835Sgblack@eecs.umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3683835Sgblack@eecs.umich.edu fromDecode->insts[i]->setSquashed(); 3693835Sgblack@eecs.umich.edu wroteToTimeBuffer = true; 3703835Sgblack@eecs.umich.edu } 3713835Sgblack@eecs.umich.edu 3723835Sgblack@eecs.umich.edu } 3733835Sgblack@eecs.umich.edu 3743835Sgblack@eecs.umich.edu // Clear the instruction list and skid buffer in case they have any 3753835Sgblack@eecs.umich.edu // insts in them. 3763835Sgblack@eecs.umich.edu insts[tid].clear(); 3773835Sgblack@eecs.umich.edu 3783835Sgblack@eecs.umich.edu // Clear the skid buffer in case it has any data in it. 3793835Sgblack@eecs.umich.edu skidBuffer[tid].clear(); 3803835Sgblack@eecs.umich.edu 3813835Sgblack@eecs.umich.edu doSquash(squash_seq_num, tid); 3823835Sgblack@eecs.umich.edu} 3833835Sgblack@eecs.umich.edu 3843835Sgblack@eecs.umich.edutemplate <class Impl> 3853835Sgblack@eecs.umich.eduvoid 3863835Sgblack@eecs.umich.eduDefaultRename<Impl>::tick() 3873835Sgblack@eecs.umich.edu{ 3883835Sgblack@eecs.umich.edu wroteToTimeBuffer = false; 3893835Sgblack@eecs.umich.edu 3903835Sgblack@eecs.umich.edu blockThisCycle = false; 3913835Sgblack@eecs.umich.edu 3923835Sgblack@eecs.umich.edu bool status_change = false; 3933835Sgblack@eecs.umich.edu 3943835Sgblack@eecs.umich.edu toIEWIndex = 0; 3953270SN/A 3963270SN/A sortInsts(); 3973280SN/A 3983388Sgblack@eecs.umich.edu list<ThreadID>::iterator threads = activeThreads->begin(); 3993270SN/A list<ThreadID>::iterator end = activeThreads->end(); 4003270SN/A 4013274SN/A // Check stall and squash signals. 4023274SN/A while (threads != end) { 4033274SN/A ThreadID tid = *threads++; 4043274SN/A 4053274SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4063274SN/A 4073274SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4083274SN/A 4093270SN/A rename(status_change, tid); 4103270SN/A } 4113270SN/A 4123835Sgblack@eecs.umich.edu if (status_change) { 4133835Sgblack@eecs.umich.edu updateStatus(); 4143835Sgblack@eecs.umich.edu } 4153835Sgblack@eecs.umich.edu 4163835Sgblack@eecs.umich.edu if (wroteToTimeBuffer) { 4173835Sgblack@eecs.umich.edu DPRINTF(Activity, "Activity this cycle.\n"); 4183835Sgblack@eecs.umich.edu cpu->activityThisCycle(); 4193835Sgblack@eecs.umich.edu } 4203835Sgblack@eecs.umich.edu 4213835Sgblack@eecs.umich.edu threads = activeThreads->begin(); 4223835Sgblack@eecs.umich.edu 4233280SN/A while (threads != end) { 4243280SN/A ThreadID tid = *threads++; 4253280SN/A 4263280SN/A // If we committed this cycle then doneSeqNum will be > 0 4273280SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4283280SN/A !fromCommit->commitInfo[tid].squash && 4293280SN/A renameStatus[tid] != Squashing) { 4303280SN/A 4313280SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4323280SN/A tid); 4333280SN/A } 4343280SN/A } 4353270SN/A 4363270SN/A // @todo: make into updateProgress function 4373810Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 4383270SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4393270SN/A loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 4403270SN/A storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 4413379SN/A assert(loadsInProgress[tid] >= 0); 4423379SN/A assert(storesInProgress[tid] >= 0); 4433274SN/A assert(instsInProgress[tid] >=0); 4443274SN/A } 4453270SN/A 4463270SN/A} 4473270SN/A 4483274SN/Atemplate<class Impl> 4493274SN/Avoid 4503391Sgblack@eecs.umich.eduDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4513280SN/A{ 4523391Sgblack@eecs.umich.edu // If status is Running or idle, 4533388Sgblack@eecs.umich.edu // call renameInsts() 4543901Ssaidi@eecs.umich.edu // If status is Unblocking, 4553901Ssaidi@eecs.umich.edu // buffer any instructions coming from decode 4563440Sgblack@eecs.umich.edu // continue trying to empty skid buffer 4573440Sgblack@eecs.umich.edu // check if stall conditions have passed 4583391Sgblack@eecs.umich.edu 4593274SN/A if (renameStatus[tid] == Blocked) { 4603274SN/A ++renameBlockCycles; 4613391Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Squashing) { 4623280SN/A ++renameSquashCycles; 4633274SN/A } else if (renameStatus[tid] == SerializeStall) { 4643274SN/A ++renameSerializeStallCycles; 4653391Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4663280SN/A // was set, then that means that we are resuming serializing 4673280SN/A // this cycle. Tell the previous stages to block. 4683280SN/A if (resumeSerialize) { 4693439Sgblack@eecs.umich.edu resumeSerialize = false; 4703391Sgblack@eecs.umich.edu block(tid); 4713391Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4723391Sgblack@eecs.umich.edu } 4733391Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4743391Sgblack@eecs.umich.edu if (resumeUnblocking) { 4753810Sgblack@eecs.umich.edu block(tid); 4763391Sgblack@eecs.umich.edu resumeUnblocking = false; 4773270SN/A toDecode->renameUnblock[tid] = false; 4783835Sgblack@eecs.umich.edu } 4793835Sgblack@eecs.umich.edu } 4803835Sgblack@eecs.umich.edu 4813835Sgblack@eecs.umich.edu if (renameStatus[tid] == Running || 4823835Sgblack@eecs.umich.edu renameStatus[tid] == Idle) { 4833835Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4843835Sgblack@eecs.umich.edu "stage.\n", tid); 4853835Sgblack@eecs.umich.edu 4863835Sgblack@eecs.umich.edu renameInsts(tid); 4873835Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4883835Sgblack@eecs.umich.edu renameInsts(tid); 4893835Sgblack@eecs.umich.edu 4903835Sgblack@eecs.umich.edu if (validInsts()) { 4913835Sgblack@eecs.umich.edu // Add the current inputs to the skid buffer so they can be 4923835Sgblack@eecs.umich.edu // reprocessed when this stage unblocks. 4933835Sgblack@eecs.umich.edu skidInsert(tid); 4943835Sgblack@eecs.umich.edu } 4953835Sgblack@eecs.umich.edu 4963835Sgblack@eecs.umich.edu // If we switched over to blocking, then there's a potential for 4973901Ssaidi@eecs.umich.edu // an overall status change. 4983835Sgblack@eecs.umich.edu status_change = unblock(tid) || status_change || blockThisCycle; 4993835Sgblack@eecs.umich.edu } 5003835Sgblack@eecs.umich.edu} 5013835Sgblack@eecs.umich.edu 5023835Sgblack@eecs.umich.edutemplate <class Impl> 5033835Sgblack@eecs.umich.eduvoid 5043835Sgblack@eecs.umich.eduDefaultRename<Impl>::renameInsts(ThreadID tid) 5053835Sgblack@eecs.umich.edu{ 5063835Sgblack@eecs.umich.edu // Instructions can be either in the skid buffer or the queue of 5073835Sgblack@eecs.umich.edu // instructions coming from decode, depending on the status. 5083835Sgblack@eecs.umich.edu int insts_available = renameStatus[tid] == Unblocking ? 5093835Sgblack@eecs.umich.edu skidBuffer[tid].size() : insts[tid].size(); 5103852Sgblack@eecs.umich.edu 5113835Sgblack@eecs.umich.edu // Check the decode queue to see if instructions are available. 5123835Sgblack@eecs.umich.edu // If there are no available instructions to rename, then do nothing. 5133835Sgblack@eecs.umich.edu if (insts_available == 0) { 5143835Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5153835Sgblack@eecs.umich.edu tid); 5163835Sgblack@eecs.umich.edu // Should I change status to idle? 5173835Sgblack@eecs.umich.edu ++renameIdleCycles; 5183835Sgblack@eecs.umich.edu return; 5193270SN/A } else if (renameStatus[tid] == Unblocking) { 5203270SN/A ++renameUnblockCycles; 5213810Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Running) { 5223391Sgblack@eecs.umich.edu ++renameRunCycles; 5233391Sgblack@eecs.umich.edu } 5243391Sgblack@eecs.umich.edu 5253391Sgblack@eecs.umich.edu DynInstPtr inst; 5263270SN/A 5273270SN/A // Will have to do a different calculation for the number of free 5283270SN/A // entries. 5293391Sgblack@eecs.umich.edu int free_rob_entries = calcFreeROBEntries(tid); 5303810Sgblack@eecs.umich.edu int free_iq_entries = calcFreeIQEntries(tid); 5313270SN/A int min_free_entries = free_rob_entries; 5323270SN/A 5333810Sgblack@eecs.umich.edu FullSource source = ROB; 5343391Sgblack@eecs.umich.edu 5353391Sgblack@eecs.umich.edu if (free_iq_entries < min_free_entries) { 5363391Sgblack@eecs.umich.edu min_free_entries = free_iq_entries; 5373391Sgblack@eecs.umich.edu source = IQ; 5383270SN/A } 5393270SN/A 5403270SN/A // Check if there's any space left. 5413391Sgblack@eecs.umich.edu if (min_free_entries <= 0) { 5423810Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " 5433270SN/A "entries.\n" 5443835Sgblack@eecs.umich.edu "ROB has %i free entries.\n" 5453835Sgblack@eecs.umich.edu "IQ has %i free entries.\n", 5463835Sgblack@eecs.umich.edu tid, 5473835Sgblack@eecs.umich.edu free_rob_entries, 5483835Sgblack@eecs.umich.edu free_iq_entries); 5493835Sgblack@eecs.umich.edu 5503835Sgblack@eecs.umich.edu blockThisCycle = true; 5513835Sgblack@eecs.umich.edu 552 block(tid); 553 554 incrFullStat(source); 555 556 return; 557 } else if (min_free_entries < insts_available) { 558 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 559 "%i insts available, but only %i insts can be " 560 "renamed due to ROB/IQ/LSQ limits.\n", 561 tid, insts_available, min_free_entries); 562 563 insts_available = min_free_entries; 564 565 blockThisCycle = true; 566 567 incrFullStat(source); 568 } 569 570 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 571 skidBuffer[tid] : insts[tid]; 572 573 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 574 "send iew.\n", tid, insts_available); 575 576 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 577 "dispatched to IQ last cycle.\n", 578 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 579 580 // Handle serializing the next instruction if necessary. 581 if (serializeOnNextInst[tid]) { 582 if (emptyROB[tid] && instsInProgress[tid] == 0) { 583 // ROB already empty; no need to serialize. 584 serializeOnNextInst[tid] = false; 585 } else if (!insts_to_rename.empty()) { 586 insts_to_rename.front()->setSerializeBefore(); 587 } 588 } 589 590 int renamed_insts = 0; 591 592 while (insts_available > 0 && toIEWIndex < renameWidth) { 593 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 594 595 assert(!insts_to_rename.empty()); 596 597 inst = insts_to_rename.front(); 598 599 //For all kind of instructions, check ROB and IQ first 600 //For load instruction, check LQ size and take into account the inflight loads 601 //For store instruction, check SQ size and take into account the inflight stores 602 603 if (inst->isLoad()) { 604 if (calcFreeLQEntries(tid) <= 0) { 605 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 606 source = LQ; 607 incrFullStat(source); 608 break; 609 } 610 } 611 612 if (inst->isStore()) { 613 if (calcFreeSQEntries(tid) <= 0) { 614 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 615 source = SQ; 616 incrFullStat(source); 617 break; 618 } 619 } 620 621 insts_to_rename.pop_front(); 622 623 if (renameStatus[tid] == Unblocking) { 624 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 625 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 626 } 627 628 if (inst->isSquashed()) { 629 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 630 "squashed, skipping.\n", tid, inst->seqNum, 631 inst->pcState()); 632 633 ++renameSquashedInsts; 634 635 // Decrement how many instructions are available. 636 --insts_available; 637 638 continue; 639 } 640 641 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 642 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 643 644 // Check here to make sure there are enough destination registers 645 // to rename to. Otherwise block. 646 if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 647 inst->numFPDestRegs(), 648 inst->numCCDestRegs())) { 649 DPRINTF(Rename, "Blocking due to lack of free " 650 "physical registers to rename to.\n"); 651 blockThisCycle = true; 652 insts_to_rename.push_front(inst); 653 ++renameFullRegistersEvents; 654 655 break; 656 } 657 658 // Handle serializeAfter/serializeBefore instructions. 659 // serializeAfter marks the next instruction as serializeBefore. 660 // serializeBefore makes the instruction wait in rename until the ROB 661 // is empty. 662 663 // In this model, IPR accesses are serialize before 664 // instructions, and store conditionals are serialize after 665 // instructions. This is mainly due to lack of support for 666 // out-of-order operations of either of those classes of 667 // instructions. 668 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 669 !inst->isSerializeHandled()) { 670 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 671 672 if (!inst->isTempSerializeBefore()) { 673 renamedSerializing++; 674 inst->setSerializeHandled(); 675 } else { 676 renamedTempSerializing++; 677 } 678 679 // Change status over to SerializeStall so that other stages know 680 // what this is blocked on. 681 renameStatus[tid] = SerializeStall; 682 683 serializeInst[tid] = inst; 684 685 blockThisCycle = true; 686 687 break; 688 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 689 !inst->isSerializeHandled()) { 690 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 691 692 renamedSerializing++; 693 694 inst->setSerializeHandled(); 695 696 serializeAfter(insts_to_rename, tid); 697 } 698 699 renameSrcRegs(inst, inst->threadNumber); 700 701 renameDestRegs(inst, inst->threadNumber); 702 703 if (inst->isLoad()) { 704 loadsInProgress[tid]++; 705 } 706 if (inst->isStore()) { 707 storesInProgress[tid]++; 708 } 709 ++renamed_insts; 710 // Notify potential listeners that source and destination registers for 711 // this instruction have been renamed. 712 ppRename->notify(inst); 713 714 // Put instruction in rename queue. 715 toIEW->insts[toIEWIndex] = inst; 716 ++(toIEW->size); 717 718 // Increment which instruction we're on. 719 ++toIEWIndex; 720 721 // Decrement how many instructions are available. 722 --insts_available; 723 } 724 725 instsInProgress[tid] += renamed_insts; 726 renameRenamedInsts += renamed_insts; 727 728 // If we wrote to the time buffer, record this. 729 if (toIEWIndex) { 730 wroteToTimeBuffer = true; 731 } 732 733 // Check if there's any instructions left that haven't yet been renamed. 734 // If so then block. 735 if (insts_available) { 736 blockThisCycle = true; 737 } 738 739 if (blockThisCycle) { 740 block(tid); 741 toDecode->renameUnblock[tid] = false; 742 } 743} 744 745template<class Impl> 746void 747DefaultRename<Impl>::skidInsert(ThreadID tid) 748{ 749 DynInstPtr inst = NULL; 750 751 while (!insts[tid].empty()) { 752 inst = insts[tid].front(); 753 754 insts[tid].pop_front(); 755 756 assert(tid == inst->threadNumber); 757 758 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 759 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 760 761 ++renameSkidInsts; 762 763 skidBuffer[tid].push_back(inst); 764 } 765 766 if (skidBuffer[tid].size() > skidBufferMax) 767 { 768 typename InstQueue::iterator it; 769 warn("Skidbuffer contents:\n"); 770 for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 771 { 772 warn("[tid:%u]: %s [sn:%i].\n", tid, 773 (*it)->staticInst->disassemble(inst->instAddr()), 774 (*it)->seqNum); 775 } 776 panic("Skidbuffer Exceeded Max Size"); 777 } 778} 779 780template <class Impl> 781void 782DefaultRename<Impl>::sortInsts() 783{ 784 int insts_from_decode = fromDecode->size; 785 for (int i = 0; i < insts_from_decode; ++i) { 786 DynInstPtr inst = fromDecode->insts[i]; 787 insts[inst->threadNumber].push_back(inst); 788#if TRACING_ON 789 if (DTRACE(O3PipeView)) { 790 inst->renameTick = curTick() - inst->fetchTick; 791 } 792#endif 793 } 794} 795 796template<class Impl> 797bool 798DefaultRename<Impl>::skidsEmpty() 799{ 800 list<ThreadID>::iterator threads = activeThreads->begin(); 801 list<ThreadID>::iterator end = activeThreads->end(); 802 803 while (threads != end) { 804 ThreadID tid = *threads++; 805 806 if (!skidBuffer[tid].empty()) 807 return false; 808 } 809 810 return true; 811} 812 813template<class Impl> 814void 815DefaultRename<Impl>::updateStatus() 816{ 817 bool any_unblocking = false; 818 819 list<ThreadID>::iterator threads = activeThreads->begin(); 820 list<ThreadID>::iterator end = activeThreads->end(); 821 822 while (threads != end) { 823 ThreadID tid = *threads++; 824 825 if (renameStatus[tid] == Unblocking) { 826 any_unblocking = true; 827 break; 828 } 829 } 830 831 // Rename will have activity if it's unblocking. 832 if (any_unblocking) { 833 if (_status == Inactive) { 834 _status = Active; 835 836 DPRINTF(Activity, "Activating stage.\n"); 837 838 cpu->activateStage(O3CPU::RenameIdx); 839 } 840 } else { 841 // If it's not unblocking, then rename will not have any internal 842 // activity. Switch it to inactive. 843 if (_status == Active) { 844 _status = Inactive; 845 DPRINTF(Activity, "Deactivating stage.\n"); 846 847 cpu->deactivateStage(O3CPU::RenameIdx); 848 } 849 } 850} 851 852template <class Impl> 853bool 854DefaultRename<Impl>::block(ThreadID tid) 855{ 856 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 857 858 // Add the current inputs onto the skid buffer, so they can be 859 // reprocessed when this stage unblocks. 860 skidInsert(tid); 861 862 // Only signal backwards to block if the previous stages do not think 863 // rename is already blocked. 864 if (renameStatus[tid] != Blocked) { 865 // If resumeUnblocking is set, we unblocked during the squash, 866 // but now we're have unblocking status. We need to tell earlier 867 // stages to block. 868 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 869 toDecode->renameBlock[tid] = true; 870 toDecode->renameUnblock[tid] = false; 871 wroteToTimeBuffer = true; 872 } 873 874 // Rename can not go from SerializeStall to Blocked, otherwise 875 // it would not know to complete the serialize stall. 876 if (renameStatus[tid] != SerializeStall) { 877 // Set status to Blocked. 878 renameStatus[tid] = Blocked; 879 return true; 880 } 881 } 882 883 return false; 884} 885 886template <class Impl> 887bool 888DefaultRename<Impl>::unblock(ThreadID tid) 889{ 890 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 891 892 // Rename is done unblocking if the skid buffer is empty. 893 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 894 895 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 896 897 toDecode->renameUnblock[tid] = true; 898 wroteToTimeBuffer = true; 899 900 renameStatus[tid] = Running; 901 return true; 902 } 903 904 return false; 905} 906 907template <class Impl> 908void 909DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 910{ 911 typename std::list<RenameHistory>::iterator hb_it = 912 historyBuffer[tid].begin(); 913 914 // After a syscall squashes everything, the history buffer may be empty 915 // but the ROB may still be squashing instructions. 916 if (historyBuffer[tid].empty()) { 917 return; 918 } 919 920 // Go through the most recent instructions, undoing the mappings 921 // they did and freeing up the registers. 922 while (!historyBuffer[tid].empty() && 923 hb_it->instSeqNum > squashed_seq_num) { 924 assert(hb_it != historyBuffer[tid].end()); 925 926 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 927 "number %i.\n", tid, hb_it->instSeqNum); 928 929 // Undo the rename mapping only if it was really a change. 930 // Special regs that are not really renamed (like misc regs 931 // and the zero reg) can be recognized because the new mapping 932 // is the same as the old one. While it would be merely a 933 // waste of time to update the rename table, we definitely 934 // don't want to put these on the free list. 935 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 936 // Tell the rename map to set the architected register to the 937 // previous physical register that it was renamed to. 938 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 939 940 // Put the renamed physical register back on the free list. 941 freeList->addReg(hb_it->newPhysReg); 942 } 943 944 // Notify potential listeners that the register mapping needs to be 945 // removed because the instruction it was mapped to got squashed. Note 946 // that this is done before hb_it is incremented. 947 ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, 948 hb_it->newPhysReg)); 949 950 historyBuffer[tid].erase(hb_it++); 951 952 ++renameUndoneMaps; 953 } 954} 955 956template<class Impl> 957void 958DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 959{ 960 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 961 "history buffer %u (size=%i), until [sn:%lli].\n", 962 tid, tid, historyBuffer[tid].size(), inst_seq_num); 963 964 typename std::list<RenameHistory>::iterator hb_it = 965 historyBuffer[tid].end(); 966 967 --hb_it; 968 969 if (historyBuffer[tid].empty()) { 970 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 971 return; 972 } else if (hb_it->instSeqNum > inst_seq_num) { 973 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 974 "that a syscall happened recently.\n", tid); 975 return; 976 } 977 978 // Commit all the renames up until (and including) the committed sequence 979 // number. Some or even all of the committed instructions may not have 980 // rename histories if they did not have destination registers that were 981 // renamed. 982 while (!historyBuffer[tid].empty() && 983 hb_it != historyBuffer[tid].end() && 984 hb_it->instSeqNum <= inst_seq_num) { 985 986 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 987 "[sn:%lli].\n", 988 tid, hb_it->prevPhysReg, hb_it->instSeqNum); 989 990 // Don't free special phys regs like misc and zero regs, which 991 // can be recognized because the new mapping is the same as 992 // the old one. 993 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 994 freeList->addReg(hb_it->prevPhysReg); 995 } 996 997 ++renameCommittedMaps; 998 999 historyBuffer[tid].erase(hb_it--); 1000 } 1001} 1002 1003template <class Impl> 1004inline void 1005DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 1006{ 1007 ThreadContext *tc = inst->tcBase(); 1008 RenameMap *map = renameMap[tid]; 1009 unsigned num_src_regs = inst->numSrcRegs(); 1010 1011 // Get the architectual register numbers from the source and 1012 // operands, and redirect them to the right physical register. 1013 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 1014 RegId src_reg = inst->srcRegIdx(src_idx); 1015 RegIndex flat_src_reg; 1016 PhysRegIndex renamed_reg; 1017 1018 switch (src_reg.regClass) { 1019 case IntRegClass: 1020 flat_src_reg = tc->flattenIntIndex(src_reg.regIdx); 1021 renamed_reg = map->lookupInt(flat_src_reg); 1022 intRenameLookups++; 1023 break; 1024 1025 case FloatRegClass: 1026 flat_src_reg = tc->flattenFloatIndex(src_reg.regIdx); 1027 renamed_reg = map->lookupFloat(flat_src_reg); 1028 fpRenameLookups++; 1029 break; 1030 1031 case CCRegClass: 1032 flat_src_reg = tc->flattenCCIndex(src_reg.regIdx); 1033 renamed_reg = map->lookupCC(flat_src_reg); 1034 break; 1035 1036 case MiscRegClass: 1037 // misc regs don't get flattened 1038 flat_src_reg = src_reg.regIdx; 1039 renamed_reg = map->lookupMisc(flat_src_reg); 1040 break; 1041 1042 default: 1043 panic("Invalid register class: %d.", src_reg.regClass); 1044 } 1045 1046 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), " 1047 "got phys reg %i\n", tid, RegClassStrings[src_reg.regClass], 1048 (int)src_reg.regIdx, (int)flat_src_reg, (int)renamed_reg); 1049 1050 inst->renameSrcReg(src_idx, renamed_reg); 1051 1052 // See if the register is ready or not. 1053 if (scoreboard->getReg(renamed_reg)) { 1054 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 1055 tid, renamed_reg); 1056 1057 inst->markSrcRegReady(src_idx); 1058 } else { 1059 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 1060 tid, renamed_reg); 1061 } 1062 1063 ++renameRenameLookups; 1064 } 1065} 1066 1067template <class Impl> 1068inline void 1069DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1070{ 1071 ThreadContext *tc = inst->tcBase(); 1072 RenameMap *map = renameMap[tid]; 1073 unsigned num_dest_regs = inst->numDestRegs(); 1074 1075 // Rename the destination registers. 1076 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1077 RegId dest_reg = inst->destRegIdx(dest_idx); 1078 RegIndex flat_dest_reg; 1079 typename RenameMap::RenameInfo rename_result; 1080 1081 switch (dest_reg.regClass) { 1082 case IntRegClass: 1083 flat_dest_reg = tc->flattenIntIndex(dest_reg.regIdx); 1084 rename_result = map->renameInt(flat_dest_reg); 1085 break; 1086 1087 case FloatRegClass: 1088 flat_dest_reg = tc->flattenFloatIndex(dest_reg.regIdx); 1089 rename_result = map->renameFloat(flat_dest_reg); 1090 break; 1091 1092 case CCRegClass: 1093 flat_dest_reg = tc->flattenCCIndex(dest_reg.regIdx); 1094 rename_result = map->renameCC(flat_dest_reg); 1095 break; 1096 1097 case MiscRegClass: 1098 // misc regs don't get flattened 1099 flat_dest_reg = dest_reg.regIdx; 1100 rename_result = map->renameMisc(dest_reg.regIdx); 1101 break; 1102 1103 default: 1104 panic("Invalid register class: %d.", dest_reg.regClass); 1105 } 1106 1107 RegId flat_uni_dest_reg(dest_reg.regClass, flat_dest_reg); 1108 1109 inst->flattenDestReg(dest_idx, flat_uni_dest_reg); 1110 1111 // Mark Scoreboard entry as not ready 1112 scoreboard->unsetReg(rename_result.first); 1113 1114 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 1115 "reg %i.\n", tid, (int)flat_dest_reg, 1116 (int)rename_result.first); 1117 1118 // Record the rename information so that a history can be kept. 1119 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, 1120 rename_result.first, 1121 rename_result.second); 1122 1123 historyBuffer[tid].push_front(hb_entry); 1124 1125 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1126 "(size=%i), [sn:%lli].\n",tid, 1127 historyBuffer[tid].size(), 1128 (*historyBuffer[tid].begin()).instSeqNum); 1129 1130 // Tell the instruction to rename the appropriate destination 1131 // register (dest_idx) to the new physical register 1132 // (rename_result.first), and record the previous physical 1133 // register that the same logical register was renamed to 1134 // (rename_result.second). 1135 inst->renameDestReg(dest_idx, 1136 rename_result.first, 1137 rename_result.second); 1138 1139 ++renameRenamedOperands; 1140 } 1141} 1142 1143template <class Impl> 1144inline int 1145DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 1146{ 1147 int num_free = freeEntries[tid].robEntries - 1148 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1149 1150 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1151 1152 return num_free; 1153} 1154 1155template <class Impl> 1156inline int 1157DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 1158{ 1159 int num_free = freeEntries[tid].iqEntries - 1160 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1161 1162 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1163 1164 return num_free; 1165} 1166 1167template <class Impl> 1168inline int 1169DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 1170{ 1171 int num_free = freeEntries[tid].lqEntries - 1172 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 1173 DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 1174 "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 1175 loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 1176 return num_free; 1177} 1178 1179template <class Impl> 1180inline int 1181DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 1182{ 1183 int num_free = freeEntries[tid].sqEntries - 1184 (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 1185 DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 1186 "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 1187 storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 1188 return num_free; 1189} 1190 1191template <class Impl> 1192unsigned 1193DefaultRename<Impl>::validInsts() 1194{ 1195 unsigned inst_count = 0; 1196 1197 for (int i=0; i<fromDecode->size; i++) { 1198 if (!fromDecode->insts[i]->isSquashed()) 1199 inst_count++; 1200 } 1201 1202 return inst_count; 1203} 1204 1205template <class Impl> 1206void 1207DefaultRename<Impl>::readStallSignals(ThreadID tid) 1208{ 1209 if (fromIEW->iewBlock[tid]) { 1210 stalls[tid].iew = true; 1211 } 1212 1213 if (fromIEW->iewUnblock[tid]) { 1214 assert(stalls[tid].iew); 1215 stalls[tid].iew = false; 1216 } 1217} 1218 1219template <class Impl> 1220bool 1221DefaultRename<Impl>::checkStall(ThreadID tid) 1222{ 1223 bool ret_val = false; 1224 1225 if (stalls[tid].iew) { 1226 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1227 ret_val = true; 1228 } else if (calcFreeROBEntries(tid) <= 0) { 1229 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1230 ret_val = true; 1231 } else if (calcFreeIQEntries(tid) <= 0) { 1232 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1233 ret_val = true; 1234 } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 1235 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1236 ret_val = true; 1237 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1238 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1239 ret_val = true; 1240 } else if (renameStatus[tid] == SerializeStall && 1241 (!emptyROB[tid] || instsInProgress[tid])) { 1242 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1243 "empty.\n", 1244 tid); 1245 ret_val = true; 1246 } 1247 1248 return ret_val; 1249} 1250 1251template <class Impl> 1252void 1253DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1254{ 1255 if (fromIEW->iewInfo[tid].usedIQ) 1256 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 1257 1258 if (fromIEW->iewInfo[tid].usedLSQ) { 1259 freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 1260 freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 1261 } 1262 1263 if (fromCommit->commitInfo[tid].usedROB) { 1264 freeEntries[tid].robEntries = 1265 fromCommit->commitInfo[tid].freeROBEntries; 1266 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1267 } 1268 1269 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 1270 "Free LQ: %i, Free SQ: %i\n", 1271 tid, 1272 freeEntries[tid].iqEntries, 1273 freeEntries[tid].robEntries, 1274 freeEntries[tid].lqEntries, 1275 freeEntries[tid].sqEntries); 1276 1277 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1278 tid, instsInProgress[tid]); 1279} 1280 1281template <class Impl> 1282bool 1283DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 1284{ 1285 // Check if there's a squash signal, squash if there is 1286 // Check stall signals, block if necessary. 1287 // If status was blocked 1288 // check if stall conditions have passed 1289 // if so then go to unblocking 1290 // If status was Squashing 1291 // check if squashing is not high. Switch to running this cycle. 1292 // If status was serialize stall 1293 // check if ROB is empty and no insts are in flight to the ROB 1294 1295 readFreeEntries(tid); 1296 readStallSignals(tid); 1297 1298 if (fromCommit->commitInfo[tid].squash) { 1299 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1300 "commit.\n", tid); 1301 1302 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1303 1304 return true; 1305 } 1306 1307 if (checkStall(tid)) { 1308 return block(tid); 1309 } 1310 1311 if (renameStatus[tid] == Blocked) { 1312 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1313 tid); 1314 1315 renameStatus[tid] = Unblocking; 1316 1317 unblock(tid); 1318 1319 return true; 1320 } 1321 1322 if (renameStatus[tid] == Squashing) { 1323 // Switch status to running if rename isn't being told to block or 1324 // squash this cycle. 1325 if (resumeSerialize) { 1326 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1327 tid); 1328 1329 renameStatus[tid] = SerializeStall; 1330 return true; 1331 } else if (resumeUnblocking) { 1332 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1333 tid); 1334 renameStatus[tid] = Unblocking; 1335 return true; 1336 } else { 1337 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1338 tid); 1339 1340 renameStatus[tid] = Running; 1341 return false; 1342 } 1343 } 1344 1345 if (renameStatus[tid] == SerializeStall) { 1346 // Stall ends once the ROB is free. 1347 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1348 "unblocking.\n", tid); 1349 1350 DynInstPtr serial_inst = serializeInst[tid]; 1351 1352 renameStatus[tid] = Unblocking; 1353 1354 unblock(tid); 1355 1356 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1357 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 1358 1359 // Put instruction into queue here. 1360 serial_inst->clearSerializeBefore(); 1361 1362 if (!skidBuffer[tid].empty()) { 1363 skidBuffer[tid].push_front(serial_inst); 1364 } else { 1365 insts[tid].push_front(serial_inst); 1366 } 1367 1368 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1369 " Adding to front of list.\n", tid); 1370 1371 serializeInst[tid] = NULL; 1372 1373 return true; 1374 } 1375 1376 // If we've reached this point, we have not gotten any signals that 1377 // cause rename to change its status. Rename remains the same as before. 1378 return false; 1379} 1380 1381template<class Impl> 1382void 1383DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 1384{ 1385 if (inst_list.empty()) { 1386 // Mark a bit to say that I must serialize on the next instruction. 1387 serializeOnNextInst[tid] = true; 1388 return; 1389 } 1390 1391 // Set the next instruction as serializing. 1392 inst_list.front()->setSerializeBefore(); 1393} 1394 1395template <class Impl> 1396inline void 1397DefaultRename<Impl>::incrFullStat(const FullSource &source) 1398{ 1399 switch (source) { 1400 case ROB: 1401 ++renameROBFullEvents; 1402 break; 1403 case IQ: 1404 ++renameIQFullEvents; 1405 break; 1406 case LQ: 1407 ++renameLQFullEvents; 1408 break; 1409 case SQ: 1410 ++renameSQFullEvents; 1411 break; 1412 default: 1413 panic("Rename full stall stat should be incremented for a reason!"); 1414 break; 1415 } 1416} 1417 1418template <class Impl> 1419void 1420DefaultRename<Impl>::dumpHistory() 1421{ 1422 typename std::list<RenameHistory>::iterator buf_it; 1423 1424 for (ThreadID tid = 0; tid < numThreads; tid++) { 1425 1426 buf_it = historyBuffer[tid].begin(); 1427 1428 while (buf_it != historyBuffer[tid].end()) { 1429 cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg: %i Old phys " 1430 "reg: %i\n", (*buf_it).instSeqNum, 1431 RegClassStrings[(*buf_it).archReg.regClass], 1432 (*buf_it).archReg.regIdx, 1433 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1434 1435 buf_it++; 1436 } 1437 } 1438} 1439 1440#endif//__CPU_O3_RENAME_IMPL_HH__ 1441