mem_dep_unit.hh revision 10510:7e54a9a9f6b2
1/* 2 * Copyright (c) 2012, 2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_O3_MEM_DEP_UNIT_HH__ 44#define __CPU_O3_MEM_DEP_UNIT_HH__ 45 46#include <list> 47#include <memory> 48#include <set> 49 50#include "base/hashmap.hh" 51#include "base/statistics.hh" 52#include "cpu/inst_seq.hh" 53#include "debug/MemDepUnit.hh" 54 55struct SNHash { 56 size_t operator() (const InstSeqNum &seq_num) const { 57 unsigned a = (unsigned)seq_num; 58 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 59 60 return hash; 61 } 62}; 63 64struct DerivO3CPUParams; 65 66template <class Impl> 67class InstructionQueue; 68 69/** 70 * Memory dependency unit class. This holds the memory dependence predictor. 71 * As memory operations are issued to the IQ, they are also issued to this 72 * unit, which then looks up the prediction as to what they are dependent 73 * upon. This unit must be checked prior to a memory operation being able 74 * to issue. Although this is templated, it's somewhat hard to make a generic 75 * memory dependence unit. This one is mostly for store sets; it will be 76 * quite limited in what other memory dependence predictions it can also 77 * utilize. Thus this class should be most likely be rewritten for other 78 * dependence prediction schemes. 79 */ 80template <class MemDepPred, class Impl> 81class MemDepUnit 82{ 83 protected: 84 std::string _name; 85 86 public: 87 typedef typename Impl::DynInstPtr DynInstPtr; 88 89 /** Empty constructor. Must call init() prior to using in this case. */ 90 MemDepUnit(); 91 92 /** Constructs a MemDepUnit with given parameters. */ 93 MemDepUnit(DerivO3CPUParams *params); 94 95 /** Frees up any memory allocated. */ 96 ~MemDepUnit(); 97 98 /** Returns the name of the memory dependence unit. */ 99 std::string name() const { return _name; } 100 101 /** Initializes the unit with parameters and a thread id. */ 102 void init(DerivO3CPUParams *params, ThreadID tid); 103 104 /** Registers statistics. */ 105 void regStats(); 106 107 /** Determine if we are drained. */ 108 bool isDrained() const; 109 110 /** Perform sanity checks after a drain. */ 111 void drainSanityCheck() const; 112 113 /** Takes over from another CPU's thread. */ 114 void takeOverFrom(); 115 116 /** Sets the pointer to the IQ. */ 117 void setIQ(InstructionQueue<Impl> *iq_ptr); 118 119 /** Inserts a memory instruction. */ 120 void insert(DynInstPtr &inst); 121 122 /** Inserts a non-speculative memory instruction. */ 123 void insertNonSpec(DynInstPtr &inst); 124 125 /** Inserts a barrier instruction. */ 126 void insertBarrier(DynInstPtr &barr_inst); 127 128 /** Indicate that an instruction has its registers ready. */ 129 void regsReady(DynInstPtr &inst); 130 131 /** Indicate that a non-speculative instruction is ready. */ 132 void nonSpecInstReady(DynInstPtr &inst); 133 134 /** Reschedules an instruction to be re-executed. */ 135 void reschedule(DynInstPtr &inst); 136 137 /** Replays all instructions that have been rescheduled by moving them to 138 * the ready list. 139 */ 140 void replay(); 141 142 /** Completes a memory instruction. */ 143 void completed(DynInstPtr &inst); 144 145 /** Completes a barrier instruction. */ 146 void completeBarrier(DynInstPtr &inst); 147 148 /** Wakes any dependents of a memory instruction. */ 149 void wakeDependents(DynInstPtr &inst); 150 151 /** Squashes all instructions up until a given sequence number for a 152 * specific thread. 153 */ 154 void squash(const InstSeqNum &squashed_num, ThreadID tid); 155 156 /** Indicates an ordering violation between a store and a younger load. */ 157 void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 158 159 /** Issues the given instruction */ 160 void issue(DynInstPtr &inst); 161 162 /** Debugging function to dump the lists of instructions. */ 163 void dumpLists(); 164 165 private: 166 typedef typename std::list<DynInstPtr>::iterator ListIt; 167 168 class MemDepEntry; 169 170 typedef std::shared_ptr<MemDepEntry> MemDepEntryPtr; 171 172 /** Memory dependence entries that track memory operations, marking 173 * when the instruction is ready to execute and what instructions depend 174 * upon it. 175 */ 176 class MemDepEntry { 177 public: 178 /** Constructs a memory dependence entry. */ 179 MemDepEntry(DynInstPtr &new_inst) 180 : inst(new_inst), regsReady(false), memDepReady(false), 181 completed(false), squashed(false) 182 { 183#ifdef DEBUG 184 ++memdep_count; 185 186 DPRINTF(MemDepUnit, "Memory dependency entry created. " 187 "memdep_count=%i %s\n", memdep_count, inst->pcState()); 188#endif 189 } 190 191 /** Frees any pointers. */ 192 ~MemDepEntry() 193 { 194 for (int i = 0; i < dependInsts.size(); ++i) { 195 dependInsts[i] = NULL; 196 } 197#ifdef DEBUG 198 --memdep_count; 199 200 DPRINTF(MemDepUnit, "Memory dependency entry deleted. " 201 "memdep_count=%i %s\n", memdep_count, inst->pcState()); 202#endif 203 } 204 205 /** Returns the name of the memory dependence entry. */ 206 std::string name() const { return "memdepentry"; } 207 208 /** The instruction being tracked. */ 209 DynInstPtr inst; 210 211 /** The iterator to the instruction's location inside the list. */ 212 ListIt listIt; 213 214 /** A vector of any dependent instructions. */ 215 std::vector<MemDepEntryPtr> dependInsts; 216 217 /** If the registers are ready or not. */ 218 bool regsReady; 219 /** If all memory dependencies have been satisfied. */ 220 bool memDepReady; 221 /** If the instruction is completed. */ 222 bool completed; 223 /** If the instruction is squashed. */ 224 bool squashed; 225 226 /** For debugging. */ 227#ifdef DEBUG 228 static int memdep_count; 229 static int memdep_insert; 230 static int memdep_erase; 231#endif 232 }; 233 234 /** Finds the memory dependence entry in the hash map. */ 235 inline MemDepEntryPtr &findInHash(const DynInstPtr &inst); 236 237 /** Moves an entry to the ready list. */ 238 inline void moveToReady(MemDepEntryPtr &ready_inst_entry); 239 240 typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash; 241 242 typedef typename MemDepHash::iterator MemDepHashIt; 243 244 /** A hash map of all memory dependence entries. */ 245 MemDepHash memDepHash; 246 247 /** A list of all instructions in the memory dependence unit. */ 248 std::list<DynInstPtr> instList[Impl::MaxThreads]; 249 250 /** A list of all instructions that are going to be replayed. */ 251 std::list<DynInstPtr> instsToReplay; 252 253 /** The memory dependence predictor. It is accessed upon new 254 * instructions being added to the IQ, and responds by telling 255 * this unit what instruction the newly added instruction is dependent 256 * upon. 257 */ 258 MemDepPred depPred; 259 260 /** Is there an outstanding load barrier that loads must wait on. */ 261 bool loadBarrier; 262 /** The sequence number of the load barrier. */ 263 InstSeqNum loadBarrierSN; 264 /** Is there an outstanding store barrier that loads must wait on. */ 265 bool storeBarrier; 266 /** The sequence number of the store barrier. */ 267 InstSeqNum storeBarrierSN; 268 269 /** Pointer to the IQ. */ 270 InstructionQueue<Impl> *iqPtr; 271 272 /** The thread id of this memory dependence unit. */ 273 int id; 274 275 /** Stat for number of inserted loads. */ 276 Stats::Scalar insertedLoads; 277 /** Stat for number of inserted stores. */ 278 Stats::Scalar insertedStores; 279 /** Stat for number of conflicting loads that had to wait for a store. */ 280 Stats::Scalar conflictingLoads; 281 /** Stat for number of conflicting stores that had to wait for a store. */ 282 Stats::Scalar conflictingStores; 283}; 284 285#endif // __CPU_O3_MEM_DEP_UNIT_HH__ 286