lsq.hh revision 9444
12292SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 152292SN/A * All rights reserved. 162292SN/A * 172292SN/A * Redistribution and use in source and binary forms, with or without 182292SN/A * modification, are permitted provided that the following conditions are 192292SN/A * met: redistributions of source code must retain the above copyright 202292SN/A * notice, this list of conditions and the following disclaimer; 212292SN/A * redistributions in binary form must reproduce the above copyright 222292SN/A * notice, this list of conditions and the following disclaimer in the 232292SN/A * documentation and/or other materials provided with the distribution; 242292SN/A * neither the name of the copyright holders nor the names of its 252292SN/A * contributors may be used to endorse or promote products derived from 262292SN/A * this software without specific prior written permission. 272292SN/A * 282292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Korey Sewell 412292SN/A */ 422292SN/A 432292SN/A#ifndef __CPU_O3_LSQ_HH__ 442292SN/A#define __CPU_O3_LSQ_HH__ 452292SN/A 462292SN/A#include <map> 472292SN/A#include <queue> 482292SN/A 498229Snate@binkert.org#include "cpu/o3/lsq_unit.hh" 502292SN/A#include "cpu/inst_seq.hh" 512669Sktlim@umich.edu#include "mem/port.hh" 522292SN/A#include "sim/sim_object.hh" 532292SN/A 548737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 555529Snate@binkert.org 562292SN/Atemplate <class Impl> 572292SN/Aclass LSQ { 582292SN/A public: 592733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 602292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 612292SN/A typedef typename Impl::CPUPol::IEW IEW; 622292SN/A typedef typename Impl::CPUPol::LSQUnit LSQUnit; 632292SN/A 642348SN/A /** SMT policy. */ 652292SN/A enum LSQPolicy { 662292SN/A Dynamic, 672292SN/A Partitioned, 682292SN/A Threshold 692292SN/A }; 702292SN/A 712292SN/A /** Constructs an LSQ with the given parameters. */ 725529Snate@binkert.org LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 732292SN/A 742292SN/A /** Returns the name of the LSQ. */ 752292SN/A std::string name() const; 762292SN/A 772727Sktlim@umich.edu /** Registers statistics of each LSQ unit. */ 782727Sktlim@umich.edu void regStats(); 792727Sktlim@umich.edu 802292SN/A /** Sets the pointer to the list of active threads. */ 816221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 829444SAndreas.Sandberg@ARM.com 839444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 849444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 859444SAndreas.Sandberg@ARM.com /** Has the LSQ drained? */ 869444SAndreas.Sandberg@ARM.com bool isDrained() const; 872348SN/A /** Takes over execution from another CPU's thread. */ 882307SN/A void takeOverFrom(); 892307SN/A 902292SN/A /** Number of entries needed for the given amount of threads.*/ 916221Snate@binkert.org int entryAmount(ThreadID num_threads); 926221Snate@binkert.org void removeEntries(ThreadID tid); 932292SN/A /** Reset the max entries for each thread. */ 942292SN/A void resetEntries(); 952292SN/A /** Resize the max entries for a thread. */ 966221Snate@binkert.org void resizeEntries(unsigned size, ThreadID tid); 972292SN/A 982292SN/A /** Ticks the LSQ. */ 992292SN/A void tick(); 1002292SN/A /** Ticks a specific LSQ Unit. */ 1016221Snate@binkert.org void tick(ThreadID tid) 1022329SN/A { thread[tid].tick(); } 1032292SN/A 1042292SN/A /** Inserts a load into the LSQ. */ 1052292SN/A void insertLoad(DynInstPtr &load_inst); 1062292SN/A /** Inserts a store into the LSQ. */ 1072292SN/A void insertStore(DynInstPtr &store_inst); 1082292SN/A 1092292SN/A /** Executes a load. */ 1102292SN/A Fault executeLoad(DynInstPtr &inst); 1112292SN/A 1122292SN/A /** Executes a store. */ 1132292SN/A Fault executeStore(DynInstPtr &inst); 1142292SN/A 1152292SN/A /** 1162292SN/A * Commits loads up until the given sequence number for a specific thread. 1172292SN/A */ 1186221Snate@binkert.org void commitLoads(InstSeqNum &youngest_inst, ThreadID tid) 1192329SN/A { thread[tid].commitLoads(youngest_inst); } 1202329SN/A 1212292SN/A /** 1222292SN/A * Commits stores up until the given sequence number for a specific thread. 1232292SN/A */ 1246221Snate@binkert.org void commitStores(InstSeqNum &youngest_inst, ThreadID tid) 1252329SN/A { thread[tid].commitStores(youngest_inst); } 1262292SN/A 1272292SN/A /** 1282292SN/A * Attempts to write back stores until all cache ports are used or the 1292292SN/A * interface becomes blocked. 1302292SN/A */ 1312292SN/A void writebackStores(); 1322292SN/A /** Same as above, but only for one thread. */ 1336221Snate@binkert.org void writebackStores(ThreadID tid); 1342292SN/A 1352292SN/A /** 1362292SN/A * Squash instructions from a thread until the specified sequence number. 1372292SN/A */ 1386221Snate@binkert.org void squash(const InstSeqNum &squashed_num, ThreadID tid) 1392329SN/A { thread[tid].squash(squashed_num); } 1402292SN/A 1412292SN/A /** Returns whether or not there was a memory ordering violation. */ 1422292SN/A bool violation(); 1432292SN/A /** 1442292SN/A * Returns whether or not there was a memory ordering violation for a 1452292SN/A * specific thread. 1462292SN/A */ 1476221Snate@binkert.org bool violation(ThreadID tid) 1482329SN/A { return thread[tid].violation(); } 1492292SN/A 1502292SN/A /** Returns if a load is blocked due to the memory system for a specific 1512292SN/A * thread. 1522292SN/A */ 1536221Snate@binkert.org bool loadBlocked(ThreadID tid) 1542329SN/A { return thread[tid].loadBlocked(); } 1552292SN/A 1566221Snate@binkert.org bool isLoadBlockedHandled(ThreadID tid) 1572292SN/A { return thread[tid].isLoadBlockedHandled(); } 1582292SN/A 1596221Snate@binkert.org void setLoadBlockedHandled(ThreadID tid) 1602292SN/A { thread[tid].setLoadBlockedHandled(); } 1612292SN/A 1622292SN/A /** Gets the instruction that caused the memory ordering violation. */ 1636221Snate@binkert.org DynInstPtr getMemDepViolator(ThreadID tid) 1642329SN/A { return thread[tid].getMemDepViolator(); } 1652292SN/A 1662292SN/A /** Returns the head index of the load queue for a specific thread. */ 1676221Snate@binkert.org int getLoadHead(ThreadID tid) 1682329SN/A { return thread[tid].getLoadHead(); } 1692329SN/A 1702292SN/A /** Returns the sequence number of the head of the load queue. */ 1716221Snate@binkert.org InstSeqNum getLoadHeadSeqNum(ThreadID tid) 1722292SN/A { 1732292SN/A return thread[tid].getLoadHeadSeqNum(); 1742292SN/A } 1752292SN/A 1762292SN/A /** Returns the head index of the store queue. */ 1776221Snate@binkert.org int getStoreHead(ThreadID tid) 1782329SN/A { return thread[tid].getStoreHead(); } 1792329SN/A 1802292SN/A /** Returns the sequence number of the head of the store queue. */ 1816221Snate@binkert.org InstSeqNum getStoreHeadSeqNum(ThreadID tid) 1822292SN/A { 1832292SN/A return thread[tid].getStoreHeadSeqNum(); 1842292SN/A } 1852292SN/A 1862292SN/A /** Returns the number of instructions in all of the queues. */ 1872292SN/A int getCount(); 1882292SN/A /** Returns the number of instructions in the queues of one thread. */ 1896221Snate@binkert.org int getCount(ThreadID tid) 1902329SN/A { return thread[tid].getCount(); } 1912292SN/A 1922292SN/A /** Returns the total number of loads in the load queue. */ 1932292SN/A int numLoads(); 1942292SN/A /** Returns the total number of loads for a single thread. */ 1956221Snate@binkert.org int numLoads(ThreadID tid) 1962329SN/A { return thread[tid].numLoads(); } 1972292SN/A 1982292SN/A /** Returns the total number of stores in the store queue. */ 1992292SN/A int numStores(); 2002292SN/A /** Returns the total number of stores for a single thread. */ 2016221Snate@binkert.org int numStores(ThreadID tid) 2022329SN/A { return thread[tid].numStores(); } 2032292SN/A 2042292SN/A /** Returns the number of free entries. */ 2052292SN/A unsigned numFreeEntries(); 2062292SN/A /** Returns the number of free entries for a specific thread. */ 2076221Snate@binkert.org unsigned numFreeEntries(ThreadID tid); 2082292SN/A 2092292SN/A /** Returns if the LSQ is full (either LQ or SQ is full). */ 2102292SN/A bool isFull(); 2112292SN/A /** 2122292SN/A * Returns if the LSQ is full for a specific thread (either LQ or SQ is 2132292SN/A * full). 2142292SN/A */ 2156221Snate@binkert.org bool isFull(ThreadID tid); 2162292SN/A 2179444SAndreas.Sandberg@ARM.com /** Returns if the LSQ is empty (both LQ and SQ are empty). */ 2189444SAndreas.Sandberg@ARM.com bool isEmpty() const; 2199444SAndreas.Sandberg@ARM.com /** Returns if all of the LQs are empty. */ 2209444SAndreas.Sandberg@ARM.com bool lqEmpty() const; 2219444SAndreas.Sandberg@ARM.com /** Returns if all of the SQs are empty. */ 2229444SAndreas.Sandberg@ARM.com bool sqEmpty() const; 2239444SAndreas.Sandberg@ARM.com 2242292SN/A /** Returns if any of the LQs are full. */ 2252292SN/A bool lqFull(); 2262292SN/A /** Returns if the LQ of a given thread is full. */ 2276221Snate@binkert.org bool lqFull(ThreadID tid); 2282292SN/A 2292292SN/A /** Returns if any of the SQs are full. */ 2302292SN/A bool sqFull(); 2312292SN/A /** Returns if the SQ of a given thread is full. */ 2326221Snate@binkert.org bool sqFull(ThreadID tid); 2332292SN/A 2342292SN/A /** 2352292SN/A * Returns if the LSQ is stalled due to a memory operation that must be 2362292SN/A * replayed. 2372292SN/A */ 2382292SN/A bool isStalled(); 2392292SN/A /** 2402292SN/A * Returns if the LSQ of a specific thread is stalled due to a memory 2412292SN/A * operation that must be replayed. 2422292SN/A */ 2436221Snate@binkert.org bool isStalled(ThreadID tid); 2442292SN/A 2452292SN/A /** Returns whether or not there are any stores to write back to memory. */ 2462292SN/A bool hasStoresToWB(); 2472329SN/A 2482292SN/A /** Returns whether or not a specific thread has any stores to write back 2492292SN/A * to memory. 2502292SN/A */ 2516221Snate@binkert.org bool hasStoresToWB(ThreadID tid) 2522329SN/A { return thread[tid].hasStoresToWB(); } 2532329SN/A 2542292SN/A /** Returns the number of stores a specific thread has to write back. */ 2556221Snate@binkert.org int numStoresToWB(ThreadID tid) 2562329SN/A { return thread[tid].numStoresToWB(); } 2572292SN/A 2582292SN/A /** Returns if the LSQ will write back to memory this cycle. */ 2592292SN/A bool willWB(); 2602292SN/A /** Returns if the LSQ of a specific thread will write back to memory this 2612292SN/A * cycle. 2622292SN/A */ 2636221Snate@binkert.org bool willWB(ThreadID tid) 2642329SN/A { return thread[tid].willWB(); } 2652292SN/A 2662907Sktlim@umich.edu /** Returns if the cache is currently blocked. */ 2679444SAndreas.Sandberg@ARM.com bool cacheBlocked() const 2686221Snate@binkert.org { return retryTid != InvalidThreadID; } 2692907Sktlim@umich.edu 2702907Sktlim@umich.edu /** Sets the retry thread id, indicating that one of the LSQUnits 2712907Sktlim@umich.edu * tried to access the cache but the cache was blocked. */ 2726221Snate@binkert.org void setRetryTid(ThreadID tid) 2732907Sktlim@umich.edu { retryTid = tid; } 2742907Sktlim@umich.edu 2752292SN/A /** Debugging function to print out all instructions. */ 2769440SAndreas.Sandberg@ARM.com void dumpInsts() const; 2772292SN/A /** Debugging function to print out instructions from a specific thread. */ 2789440SAndreas.Sandberg@ARM.com void dumpInsts(ThreadID tid) const 2792329SN/A { thread[tid].dumpInsts(); } 2802292SN/A 2816974Stjones1@inf.ed.ac.uk /** Executes a read operation, using the load specified at the load 2826974Stjones1@inf.ed.ac.uk * index. 2836974Stjones1@inf.ed.ac.uk */ 2846974Stjones1@inf.ed.ac.uk Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 2857520Sgblack@eecs.umich.edu uint8_t *data, int load_idx); 2862292SN/A 2872292SN/A /** Executes a store operation, using the store specified at the store 2886974Stjones1@inf.ed.ac.uk * index. 2892292SN/A */ 2906974Stjones1@inf.ed.ac.uk Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 2917520Sgblack@eecs.umich.edu uint8_t *data, int store_idx); 2922292SN/A 2938707Sandreas.hansson@arm.com /** 2948707Sandreas.hansson@arm.com * Retry the previous send that failed. 2958707Sandreas.hansson@arm.com */ 2968707Sandreas.hansson@arm.com void recvRetry(); 2978707Sandreas.hansson@arm.com 2988707Sandreas.hansson@arm.com /** 2998707Sandreas.hansson@arm.com * Handles writing back and completing the load or store that has 3008707Sandreas.hansson@arm.com * returned from memory. 3018707Sandreas.hansson@arm.com * 3028707Sandreas.hansson@arm.com * @param pkt Response packet from the memory sub-system 3038707Sandreas.hansson@arm.com */ 3048975Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt); 3058707Sandreas.hansson@arm.com 3068975Sandreas.hansson@arm.com void recvTimingSnoopReq(PacketPtr pkt); 3078948Sandreas.hansson@arm.com 3084329Sktlim@umich.edu /** The CPU pointer. */ 3094329Sktlim@umich.edu O3CPU *cpu; 3104329Sktlim@umich.edu 3114329Sktlim@umich.edu /** The IEW stage pointer. */ 3124329Sktlim@umich.edu IEW *iewStage; 3134329Sktlim@umich.edu 3142907Sktlim@umich.edu protected: 3152292SN/A /** The LSQ policy for SMT mode. */ 3162292SN/A LSQPolicy lsqPolicy; 3172292SN/A 3182292SN/A /** The LSQ units for individual threads. */ 3192292SN/A LSQUnit thread[Impl::MaxThreads]; 3202292SN/A 3212292SN/A /** List of Active Threads in System. */ 3226221Snate@binkert.org std::list<ThreadID> *activeThreads; 3232292SN/A 3242292SN/A /** Total Size of LQ Entries. */ 3252292SN/A unsigned LQEntries; 3262292SN/A /** Total Size of SQ Entries. */ 3272292SN/A unsigned SQEntries; 3282292SN/A 3292292SN/A /** Max LQ Size - Used to Enforce Sharing Policies. */ 3302292SN/A unsigned maxLQEntries; 3312292SN/A 3322292SN/A /** Max SQ Size - Used to Enforce Sharing Policies. */ 3332292SN/A unsigned maxSQEntries; 3342292SN/A 3352292SN/A /** Number of Threads. */ 3366221Snate@binkert.org ThreadID numThreads; 3372907Sktlim@umich.edu 3382907Sktlim@umich.edu /** The thread id of the LSQ Unit that is currently waiting for a 3392907Sktlim@umich.edu * retry. */ 3406221Snate@binkert.org ThreadID retryTid; 3412292SN/A}; 3422292SN/A 3432292SN/Atemplate <class Impl> 3442292SN/AFault 3456974Stjones1@inf.ed.ac.ukLSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 3467520Sgblack@eecs.umich.edu uint8_t *data, int load_idx) 3472292SN/A{ 3486221Snate@binkert.org ThreadID tid = req->threadId(); 3492292SN/A 3506974Stjones1@inf.ed.ac.uk return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx); 3512292SN/A} 3522292SN/A 3532292SN/Atemplate <class Impl> 3542292SN/AFault 3556974Stjones1@inf.ed.ac.ukLSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 3567520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 3572292SN/A{ 3586221Snate@binkert.org ThreadID tid = req->threadId(); 3592292SN/A 3606974Stjones1@inf.ed.ac.uk return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx); 3612292SN/A} 3622292SN/A 3632292SN/A#endif // __CPU_O3_LSQ_HH__ 364