lsq.hh revision 9444
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Korey Sewell 41 */ 42 43#ifndef __CPU_O3_LSQ_HH__ 44#define __CPU_O3_LSQ_HH__ 45 46#include <map> 47#include <queue> 48 49#include "cpu/o3/lsq_unit.hh" 50#include "cpu/inst_seq.hh" 51#include "mem/port.hh" 52#include "sim/sim_object.hh" 53 54struct DerivO3CPUParams; 55 56template <class Impl> 57class LSQ { 58 public: 59 typedef typename Impl::O3CPU O3CPU; 60 typedef typename Impl::DynInstPtr DynInstPtr; 61 typedef typename Impl::CPUPol::IEW IEW; 62 typedef typename Impl::CPUPol::LSQUnit LSQUnit; 63 64 /** SMT policy. */ 65 enum LSQPolicy { 66 Dynamic, 67 Partitioned, 68 Threshold 69 }; 70 71 /** Constructs an LSQ with the given parameters. */ 72 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 73 74 /** Returns the name of the LSQ. */ 75 std::string name() const; 76 77 /** Registers statistics of each LSQ unit. */ 78 void regStats(); 79 80 /** Sets the pointer to the list of active threads. */ 81 void setActiveThreads(std::list<ThreadID> *at_ptr); 82 83 /** Perform sanity checks after a drain. */ 84 void drainSanityCheck() const; 85 /** Has the LSQ drained? */ 86 bool isDrained() const; 87 /** Takes over execution from another CPU's thread. */ 88 void takeOverFrom(); 89 90 /** Number of entries needed for the given amount of threads.*/ 91 int entryAmount(ThreadID num_threads); 92 void removeEntries(ThreadID tid); 93 /** Reset the max entries for each thread. */ 94 void resetEntries(); 95 /** Resize the max entries for a thread. */ 96 void resizeEntries(unsigned size, ThreadID tid); 97 98 /** Ticks the LSQ. */ 99 void tick(); 100 /** Ticks a specific LSQ Unit. */ 101 void tick(ThreadID tid) 102 { thread[tid].tick(); } 103 104 /** Inserts a load into the LSQ. */ 105 void insertLoad(DynInstPtr &load_inst); 106 /** Inserts a store into the LSQ. */ 107 void insertStore(DynInstPtr &store_inst); 108 109 /** Executes a load. */ 110 Fault executeLoad(DynInstPtr &inst); 111 112 /** Executes a store. */ 113 Fault executeStore(DynInstPtr &inst); 114 115 /** 116 * Commits loads up until the given sequence number for a specific thread. 117 */ 118 void commitLoads(InstSeqNum &youngest_inst, ThreadID tid) 119 { thread[tid].commitLoads(youngest_inst); } 120 121 /** 122 * Commits stores up until the given sequence number for a specific thread. 123 */ 124 void commitStores(InstSeqNum &youngest_inst, ThreadID tid) 125 { thread[tid].commitStores(youngest_inst); } 126 127 /** 128 * Attempts to write back stores until all cache ports are used or the 129 * interface becomes blocked. 130 */ 131 void writebackStores(); 132 /** Same as above, but only for one thread. */ 133 void writebackStores(ThreadID tid); 134 135 /** 136 * Squash instructions from a thread until the specified sequence number. 137 */ 138 void squash(const InstSeqNum &squashed_num, ThreadID tid) 139 { thread[tid].squash(squashed_num); } 140 141 /** Returns whether or not there was a memory ordering violation. */ 142 bool violation(); 143 /** 144 * Returns whether or not there was a memory ordering violation for a 145 * specific thread. 146 */ 147 bool violation(ThreadID tid) 148 { return thread[tid].violation(); } 149 150 /** Returns if a load is blocked due to the memory system for a specific 151 * thread. 152 */ 153 bool loadBlocked(ThreadID tid) 154 { return thread[tid].loadBlocked(); } 155 156 bool isLoadBlockedHandled(ThreadID tid) 157 { return thread[tid].isLoadBlockedHandled(); } 158 159 void setLoadBlockedHandled(ThreadID tid) 160 { thread[tid].setLoadBlockedHandled(); } 161 162 /** Gets the instruction that caused the memory ordering violation. */ 163 DynInstPtr getMemDepViolator(ThreadID tid) 164 { return thread[tid].getMemDepViolator(); } 165 166 /** Returns the head index of the load queue for a specific thread. */ 167 int getLoadHead(ThreadID tid) 168 { return thread[tid].getLoadHead(); } 169 170 /** Returns the sequence number of the head of the load queue. */ 171 InstSeqNum getLoadHeadSeqNum(ThreadID tid) 172 { 173 return thread[tid].getLoadHeadSeqNum(); 174 } 175 176 /** Returns the head index of the store queue. */ 177 int getStoreHead(ThreadID tid) 178 { return thread[tid].getStoreHead(); } 179 180 /** Returns the sequence number of the head of the store queue. */ 181 InstSeqNum getStoreHeadSeqNum(ThreadID tid) 182 { 183 return thread[tid].getStoreHeadSeqNum(); 184 } 185 186 /** Returns the number of instructions in all of the queues. */ 187 int getCount(); 188 /** Returns the number of instructions in the queues of one thread. */ 189 int getCount(ThreadID tid) 190 { return thread[tid].getCount(); } 191 192 /** Returns the total number of loads in the load queue. */ 193 int numLoads(); 194 /** Returns the total number of loads for a single thread. */ 195 int numLoads(ThreadID tid) 196 { return thread[tid].numLoads(); } 197 198 /** Returns the total number of stores in the store queue. */ 199 int numStores(); 200 /** Returns the total number of stores for a single thread. */ 201 int numStores(ThreadID tid) 202 { return thread[tid].numStores(); } 203 204 /** Returns the number of free entries. */ 205 unsigned numFreeEntries(); 206 /** Returns the number of free entries for a specific thread. */ 207 unsigned numFreeEntries(ThreadID tid); 208 209 /** Returns if the LSQ is full (either LQ or SQ is full). */ 210 bool isFull(); 211 /** 212 * Returns if the LSQ is full for a specific thread (either LQ or SQ is 213 * full). 214 */ 215 bool isFull(ThreadID tid); 216 217 /** Returns if the LSQ is empty (both LQ and SQ are empty). */ 218 bool isEmpty() const; 219 /** Returns if all of the LQs are empty. */ 220 bool lqEmpty() const; 221 /** Returns if all of the SQs are empty. */ 222 bool sqEmpty() const; 223 224 /** Returns if any of the LQs are full. */ 225 bool lqFull(); 226 /** Returns if the LQ of a given thread is full. */ 227 bool lqFull(ThreadID tid); 228 229 /** Returns if any of the SQs are full. */ 230 bool sqFull(); 231 /** Returns if the SQ of a given thread is full. */ 232 bool sqFull(ThreadID tid); 233 234 /** 235 * Returns if the LSQ is stalled due to a memory operation that must be 236 * replayed. 237 */ 238 bool isStalled(); 239 /** 240 * Returns if the LSQ of a specific thread is stalled due to a memory 241 * operation that must be replayed. 242 */ 243 bool isStalled(ThreadID tid); 244 245 /** Returns whether or not there are any stores to write back to memory. */ 246 bool hasStoresToWB(); 247 248 /** Returns whether or not a specific thread has any stores to write back 249 * to memory. 250 */ 251 bool hasStoresToWB(ThreadID tid) 252 { return thread[tid].hasStoresToWB(); } 253 254 /** Returns the number of stores a specific thread has to write back. */ 255 int numStoresToWB(ThreadID tid) 256 { return thread[tid].numStoresToWB(); } 257 258 /** Returns if the LSQ will write back to memory this cycle. */ 259 bool willWB(); 260 /** Returns if the LSQ of a specific thread will write back to memory this 261 * cycle. 262 */ 263 bool willWB(ThreadID tid) 264 { return thread[tid].willWB(); } 265 266 /** Returns if the cache is currently blocked. */ 267 bool cacheBlocked() const 268 { return retryTid != InvalidThreadID; } 269 270 /** Sets the retry thread id, indicating that one of the LSQUnits 271 * tried to access the cache but the cache was blocked. */ 272 void setRetryTid(ThreadID tid) 273 { retryTid = tid; } 274 275 /** Debugging function to print out all instructions. */ 276 void dumpInsts() const; 277 /** Debugging function to print out instructions from a specific thread. */ 278 void dumpInsts(ThreadID tid) const 279 { thread[tid].dumpInsts(); } 280 281 /** Executes a read operation, using the load specified at the load 282 * index. 283 */ 284 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 285 uint8_t *data, int load_idx); 286 287 /** Executes a store operation, using the store specified at the store 288 * index. 289 */ 290 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 291 uint8_t *data, int store_idx); 292 293 /** 294 * Retry the previous send that failed. 295 */ 296 void recvRetry(); 297 298 /** 299 * Handles writing back and completing the load or store that has 300 * returned from memory. 301 * 302 * @param pkt Response packet from the memory sub-system 303 */ 304 bool recvTimingResp(PacketPtr pkt); 305 306 void recvTimingSnoopReq(PacketPtr pkt); 307 308 /** The CPU pointer. */ 309 O3CPU *cpu; 310 311 /** The IEW stage pointer. */ 312 IEW *iewStage; 313 314 protected: 315 /** The LSQ policy for SMT mode. */ 316 LSQPolicy lsqPolicy; 317 318 /** The LSQ units for individual threads. */ 319 LSQUnit thread[Impl::MaxThreads]; 320 321 /** List of Active Threads in System. */ 322 std::list<ThreadID> *activeThreads; 323 324 /** Total Size of LQ Entries. */ 325 unsigned LQEntries; 326 /** Total Size of SQ Entries. */ 327 unsigned SQEntries; 328 329 /** Max LQ Size - Used to Enforce Sharing Policies. */ 330 unsigned maxLQEntries; 331 332 /** Max SQ Size - Used to Enforce Sharing Policies. */ 333 unsigned maxSQEntries; 334 335 /** Number of Threads. */ 336 ThreadID numThreads; 337 338 /** The thread id of the LSQ Unit that is currently waiting for a 339 * retry. */ 340 ThreadID retryTid; 341}; 342 343template <class Impl> 344Fault 345LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 346 uint8_t *data, int load_idx) 347{ 348 ThreadID tid = req->threadId(); 349 350 return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx); 351} 352 353template <class Impl> 354Fault 355LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 356 uint8_t *data, int store_idx) 357{ 358 ThreadID tid = req->threadId(); 359 360 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx); 361} 362 363#endif // __CPU_O3_LSQ_HH__ 364