lsq.hh revision 2689
12292SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Korey Sewell 292292SN/A */ 302292SN/A 312292SN/A#ifndef __CPU_O3_LSQ_HH__ 322292SN/A#define __CPU_O3_LSQ_HH__ 332292SN/A 342292SN/A#include <map> 352292SN/A#include <queue> 362292SN/A 372292SN/A#include "config/full_system.hh" 382292SN/A#include "cpu/inst_seq.hh" 392329SN/A//#include "cpu/o3/cpu_policy.hh" 402292SN/A#include "cpu/o3/lsq_unit.hh" 412669Sktlim@umich.edu#include "mem/port.hh" 422292SN/A//#include "mem/page_table.hh" 432292SN/A#include "sim/sim_object.hh" 442292SN/A 452292SN/Atemplate <class Impl> 462292SN/Aclass LSQ { 472292SN/A public: 482292SN/A typedef typename Impl::Params Params; 492292SN/A typedef typename Impl::FullCPU FullCPU; 502292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 512292SN/A typedef typename Impl::CPUPol::IEW IEW; 522292SN/A typedef typename Impl::CPUPol::LSQUnit LSQUnit; 532292SN/A 542348SN/A /** SMT policy. */ 552292SN/A enum LSQPolicy { 562292SN/A Dynamic, 572292SN/A Partitioned, 582292SN/A Threshold 592292SN/A }; 602292SN/A 612292SN/A /** Constructs an LSQ with the given parameters. */ 622292SN/A LSQ(Params *params); 632292SN/A 642292SN/A /** Returns the name of the LSQ. */ 652292SN/A std::string name() const; 662292SN/A 672292SN/A /** Sets the pointer to the list of active threads. */ 682292SN/A void setActiveThreads(std::list<unsigned> *at_ptr); 692292SN/A /** Sets the CPU pointer. */ 702292SN/A void setCPU(FullCPU *cpu_ptr); 712292SN/A /** Sets the IEW stage pointer. */ 722292SN/A void setIEW(IEW *iew_ptr); 732292SN/A /** Sets the page table pointer. */ 742292SN/A// void setPageTable(PageTable *pt_ptr); 752348SN/A /** Switches out the LSQ. */ 762307SN/A void switchOut(); 772348SN/A /** Takes over execution from another CPU's thread. */ 782307SN/A void takeOverFrom(); 792307SN/A 802292SN/A /** Number of entries needed for the given amount of threads.*/ 812292SN/A int entryAmount(int num_threads); 822292SN/A void removeEntries(unsigned tid); 832292SN/A /** Reset the max entries for each thread. */ 842292SN/A void resetEntries(); 852292SN/A /** Resize the max entries for a thread. */ 862292SN/A void resizeEntries(unsigned size, unsigned tid); 872292SN/A 882292SN/A /** Ticks the LSQ. */ 892292SN/A void tick(); 902292SN/A /** Ticks a specific LSQ Unit. */ 912329SN/A void tick(unsigned tid) 922329SN/A { thread[tid].tick(); } 932292SN/A 942292SN/A /** Inserts a load into the LSQ. */ 952292SN/A void insertLoad(DynInstPtr &load_inst); 962292SN/A /** Inserts a store into the LSQ. */ 972292SN/A void insertStore(DynInstPtr &store_inst); 982292SN/A 992292SN/A /** Executes a load. */ 1002292SN/A Fault executeLoad(DynInstPtr &inst); 1012292SN/A 1022292SN/A /** Executes a store. */ 1032292SN/A Fault executeStore(DynInstPtr &inst); 1042292SN/A 1052292SN/A /** 1062292SN/A * Commits loads up until the given sequence number for a specific thread. 1072292SN/A */ 1082329SN/A void commitLoads(InstSeqNum &youngest_inst, unsigned tid) 1092329SN/A { thread[tid].commitLoads(youngest_inst); } 1102329SN/A 1112292SN/A /** 1122292SN/A * Commits stores up until the given sequence number for a specific thread. 1132292SN/A */ 1142329SN/A void commitStores(InstSeqNum &youngest_inst, unsigned tid) 1152329SN/A { thread[tid].commitStores(youngest_inst); } 1162292SN/A 1172292SN/A /** 1182292SN/A * Attempts to write back stores until all cache ports are used or the 1192292SN/A * interface becomes blocked. 1202292SN/A */ 1212292SN/A void writebackStores(); 1222292SN/A /** Same as above, but only for one thread. */ 1232292SN/A void writebackStores(unsigned tid); 1242292SN/A 1252292SN/A /** 1262292SN/A * Squash instructions from a thread until the specified sequence number. 1272292SN/A */ 1282329SN/A void squash(const InstSeqNum &squashed_num, unsigned tid) 1292329SN/A { thread[tid].squash(squashed_num); } 1302292SN/A 1312292SN/A /** Returns whether or not there was a memory ordering violation. */ 1322292SN/A bool violation(); 1332292SN/A /** 1342292SN/A * Returns whether or not there was a memory ordering violation for a 1352292SN/A * specific thread. 1362292SN/A */ 1372329SN/A bool violation(unsigned tid) 1382329SN/A { return thread[tid].violation(); } 1392292SN/A 1402292SN/A /** Returns if a load is blocked due to the memory system for a specific 1412292SN/A * thread. 1422292SN/A */ 1432329SN/A bool loadBlocked(unsigned tid) 1442329SN/A { return thread[tid].loadBlocked(); } 1452292SN/A 1462292SN/A bool isLoadBlockedHandled(unsigned tid) 1472292SN/A { return thread[tid].isLoadBlockedHandled(); } 1482292SN/A 1492292SN/A void setLoadBlockedHandled(unsigned tid) 1502292SN/A { thread[tid].setLoadBlockedHandled(); } 1512292SN/A 1522292SN/A /** Gets the instruction that caused the memory ordering violation. */ 1532329SN/A DynInstPtr getMemDepViolator(unsigned tid) 1542329SN/A { return thread[tid].getMemDepViolator(); } 1552292SN/A 1562292SN/A /** Returns the head index of the load queue for a specific thread. */ 1572329SN/A int getLoadHead(unsigned tid) 1582329SN/A { return thread[tid].getLoadHead(); } 1592329SN/A 1602292SN/A /** Returns the sequence number of the head of the load queue. */ 1612292SN/A InstSeqNum getLoadHeadSeqNum(unsigned tid) 1622292SN/A { 1632292SN/A return thread[tid].getLoadHeadSeqNum(); 1642292SN/A } 1652292SN/A 1662292SN/A /** Returns the head index of the store queue. */ 1672329SN/A int getStoreHead(unsigned tid) 1682329SN/A { return thread[tid].getStoreHead(); } 1692329SN/A 1702292SN/A /** Returns the sequence number of the head of the store queue. */ 1712292SN/A InstSeqNum getStoreHeadSeqNum(unsigned tid) 1722292SN/A { 1732292SN/A return thread[tid].getStoreHeadSeqNum(); 1742292SN/A } 1752292SN/A 1762292SN/A /** Returns the number of instructions in all of the queues. */ 1772292SN/A int getCount(); 1782292SN/A /** Returns the number of instructions in the queues of one thread. */ 1792329SN/A int getCount(unsigned tid) 1802329SN/A { return thread[tid].getCount(); } 1812292SN/A 1822292SN/A /** Returns the total number of loads in the load queue. */ 1832292SN/A int numLoads(); 1842292SN/A /** Returns the total number of loads for a single thread. */ 1852329SN/A int numLoads(unsigned tid) 1862329SN/A { return thread[tid].numLoads(); } 1872292SN/A 1882292SN/A /** Returns the total number of stores in the store queue. */ 1892292SN/A int numStores(); 1902292SN/A /** Returns the total number of stores for a single thread. */ 1912329SN/A int numStores(unsigned tid) 1922329SN/A { return thread[tid].numStores(); } 1932292SN/A 1942292SN/A /** Returns the total number of loads that are ready. */ 1952292SN/A int numLoadsReady(); 1962292SN/A /** Returns the number of loads that are ready for a single thread. */ 1972329SN/A int numLoadsReady(unsigned tid) 1982329SN/A { return thread[tid].numLoadsReady(); } 1992292SN/A 2002292SN/A /** Returns the number of free entries. */ 2012292SN/A unsigned numFreeEntries(); 2022292SN/A /** Returns the number of free entries for a specific thread. */ 2032292SN/A unsigned numFreeEntries(unsigned tid); 2042292SN/A 2052292SN/A /** Returns if the LSQ is full (either LQ or SQ is full). */ 2062292SN/A bool isFull(); 2072292SN/A /** 2082292SN/A * Returns if the LSQ is full for a specific thread (either LQ or SQ is 2092292SN/A * full). 2102292SN/A */ 2112292SN/A bool isFull(unsigned tid); 2122292SN/A 2132292SN/A /** Returns if any of the LQs are full. */ 2142292SN/A bool lqFull(); 2152292SN/A /** Returns if the LQ of a given thread is full. */ 2162292SN/A bool lqFull(unsigned tid); 2172292SN/A 2182292SN/A /** Returns if any of the SQs are full. */ 2192292SN/A bool sqFull(); 2202292SN/A /** Returns if the SQ of a given thread is full. */ 2212292SN/A bool sqFull(unsigned tid); 2222292SN/A 2232292SN/A /** 2242292SN/A * Returns if the LSQ is stalled due to a memory operation that must be 2252292SN/A * replayed. 2262292SN/A */ 2272292SN/A bool isStalled(); 2282292SN/A /** 2292292SN/A * Returns if the LSQ of a specific thread is stalled due to a memory 2302292SN/A * operation that must be replayed. 2312292SN/A */ 2322292SN/A bool isStalled(unsigned tid); 2332292SN/A 2342292SN/A /** Returns whether or not there are any stores to write back to memory. */ 2352292SN/A bool hasStoresToWB(); 2362329SN/A 2372292SN/A /** Returns whether or not a specific thread has any stores to write back 2382292SN/A * to memory. 2392292SN/A */ 2402329SN/A bool hasStoresToWB(unsigned tid) 2412329SN/A { return thread[tid].hasStoresToWB(); } 2422329SN/A 2432292SN/A /** Returns the number of stores a specific thread has to write back. */ 2442329SN/A int numStoresToWB(unsigned tid) 2452329SN/A { return thread[tid].numStoresToWB(); } 2462292SN/A 2472292SN/A /** Returns if the LSQ will write back to memory this cycle. */ 2482292SN/A bool willWB(); 2492292SN/A /** Returns if the LSQ of a specific thread will write back to memory this 2502292SN/A * cycle. 2512292SN/A */ 2522329SN/A bool willWB(unsigned tid) 2532329SN/A { return thread[tid].willWB(); } 2542292SN/A 2552292SN/A /** Debugging function to print out all instructions. */ 2562292SN/A void dumpInsts(); 2572292SN/A /** Debugging function to print out instructions from a specific thread. */ 2582329SN/A void dumpInsts(unsigned tid) 2592329SN/A { thread[tid].dumpInsts(); } 2602292SN/A 2612292SN/A /** Executes a read operation, using the load specified at the load index. */ 2622292SN/A template <class T> 2632669Sktlim@umich.edu Fault read(RequestPtr req, T &data, int load_idx); 2642292SN/A 2652292SN/A /** Executes a store operation, using the store specified at the store 2662292SN/A * index. 2672292SN/A */ 2682292SN/A template <class T> 2692669Sktlim@umich.edu Fault write(RequestPtr req, T &data, int store_idx); 2702292SN/A 2712292SN/A private: 2722292SN/A /** The LSQ policy for SMT mode. */ 2732292SN/A LSQPolicy lsqPolicy; 2742292SN/A 2752292SN/A /** The LSQ units for individual threads. */ 2762292SN/A LSQUnit thread[Impl::MaxThreads]; 2772292SN/A 2782292SN/A /** The CPU pointer. */ 2792292SN/A FullCPU *cpu; 2802292SN/A 2812292SN/A /** The IEW stage pointer. */ 2822292SN/A IEW *iewStage; 2832292SN/A 2842292SN/A /** The pointer to the page table. */ 2852292SN/A// PageTable *pTable; 2862292SN/A 2872292SN/A /** List of Active Threads in System. */ 2882292SN/A std::list<unsigned> *activeThreads; 2892292SN/A 2902292SN/A /** Total Size of LQ Entries. */ 2912292SN/A unsigned LQEntries; 2922292SN/A /** Total Size of SQ Entries. */ 2932292SN/A unsigned SQEntries; 2942292SN/A 2952292SN/A /** Max LQ Size - Used to Enforce Sharing Policies. */ 2962292SN/A unsigned maxLQEntries; 2972292SN/A 2982292SN/A /** Max SQ Size - Used to Enforce Sharing Policies. */ 2992292SN/A unsigned maxSQEntries; 3002292SN/A 3012292SN/A /** Number of Threads. */ 3022292SN/A unsigned numThreads; 3032292SN/A}; 3042292SN/A 3052292SN/Atemplate <class Impl> 3062292SN/Atemplate <class T> 3072292SN/AFault 3082669Sktlim@umich.eduLSQ<Impl>::read(RequestPtr req, T &data, int load_idx) 3092292SN/A{ 3102669Sktlim@umich.edu unsigned tid = req->getThreadNum(); 3112292SN/A 3122292SN/A return thread[tid].read(req, data, load_idx); 3132292SN/A} 3142292SN/A 3152292SN/Atemplate <class Impl> 3162292SN/Atemplate <class T> 3172292SN/AFault 3182669Sktlim@umich.eduLSQ<Impl>::write(RequestPtr req, T &data, int store_idx) 3192292SN/A{ 3202669Sktlim@umich.edu unsigned tid = req->getThreadNum(); 3212292SN/A 3222292SN/A return thread[tid].write(req, data, store_idx); 3232292SN/A} 3242292SN/A 3252292SN/A#endif // __CPU_O3_LSQ_HH__ 326