lsq.hh revision 2689 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#ifndef __CPU_O3_LSQ_HH__
32#define __CPU_O3_LSQ_HH__
33
34#include <map>
35#include <queue>
36
37#include "config/full_system.hh"
38#include "cpu/inst_seq.hh"
39//#include "cpu/o3/cpu_policy.hh"
40#include "cpu/o3/lsq_unit.hh"
41#include "mem/port.hh"
42//#include "mem/page_table.hh"
43#include "sim/sim_object.hh"
44
45template <class Impl>
46class LSQ {
47  public:
48    typedef typename Impl::Params Params;
49    typedef typename Impl::FullCPU FullCPU;
50    typedef typename Impl::DynInstPtr DynInstPtr;
51    typedef typename Impl::CPUPol::IEW IEW;
52    typedef typename Impl::CPUPol::LSQUnit LSQUnit;
53
54    /** SMT policy. */
55    enum LSQPolicy {
56        Dynamic,
57        Partitioned,
58        Threshold
59    };
60
61    /** Constructs an LSQ with the given parameters. */
62    LSQ(Params *params);
63
64    /** Returns the name of the LSQ. */
65    std::string name() const;
66
67    /** Sets the pointer to the list of active threads. */
68    void setActiveThreads(std::list<unsigned> *at_ptr);
69    /** Sets the CPU pointer. */
70    void setCPU(FullCPU *cpu_ptr);
71    /** Sets the IEW stage pointer. */
72    void setIEW(IEW *iew_ptr);
73    /** Sets the page table pointer. */
74//    void setPageTable(PageTable *pt_ptr);
75    /** Switches out the LSQ. */
76    void switchOut();
77    /** Takes over execution from another CPU's thread. */
78    void takeOverFrom();
79
80    /** Number of entries needed for the given amount of threads.*/
81    int entryAmount(int num_threads);
82    void removeEntries(unsigned tid);
83    /** Reset the max entries for each thread. */
84    void resetEntries();
85    /** Resize the max entries for a thread. */
86    void resizeEntries(unsigned size, unsigned tid);
87
88    /** Ticks the LSQ. */
89    void tick();
90    /** Ticks a specific LSQ Unit. */
91    void tick(unsigned tid)
92    { thread[tid].tick(); }
93
94    /** Inserts a load into the LSQ. */
95    void insertLoad(DynInstPtr &load_inst);
96    /** Inserts a store into the LSQ. */
97    void insertStore(DynInstPtr &store_inst);
98
99    /** Executes a load. */
100    Fault executeLoad(DynInstPtr &inst);
101
102    /** Executes a store. */
103    Fault executeStore(DynInstPtr &inst);
104
105    /**
106     * Commits loads up until the given sequence number for a specific thread.
107     */
108    void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
109    { thread[tid].commitLoads(youngest_inst); }
110
111    /**
112     * Commits stores up until the given sequence number for a specific thread.
113     */
114    void commitStores(InstSeqNum &youngest_inst, unsigned tid)
115    { thread[tid].commitStores(youngest_inst); }
116
117    /**
118     * Attempts to write back stores until all cache ports are used or the
119     * interface becomes blocked.
120     */
121    void writebackStores();
122    /** Same as above, but only for one thread. */
123    void writebackStores(unsigned tid);
124
125    /**
126     * Squash instructions from a thread until the specified sequence number.
127     */
128    void squash(const InstSeqNum &squashed_num, unsigned tid)
129    { thread[tid].squash(squashed_num); }
130
131    /** Returns whether or not there was a memory ordering violation. */
132    bool violation();
133    /**
134     * Returns whether or not there was a memory ordering violation for a
135     * specific thread.
136     */
137    bool violation(unsigned tid)
138    { return thread[tid].violation(); }
139
140    /** Returns if a load is blocked due to the memory system for a specific
141     *  thread.
142     */
143    bool loadBlocked(unsigned tid)
144    { return thread[tid].loadBlocked(); }
145
146    bool isLoadBlockedHandled(unsigned tid)
147    { return thread[tid].isLoadBlockedHandled(); }
148
149    void setLoadBlockedHandled(unsigned tid)
150    { thread[tid].setLoadBlockedHandled(); }
151
152    /** Gets the instruction that caused the memory ordering violation. */
153    DynInstPtr getMemDepViolator(unsigned tid)
154    { return thread[tid].getMemDepViolator(); }
155
156    /** Returns the head index of the load queue for a specific thread. */
157    int getLoadHead(unsigned tid)
158    { return thread[tid].getLoadHead(); }
159
160    /** Returns the sequence number of the head of the load queue. */
161    InstSeqNum getLoadHeadSeqNum(unsigned tid)
162    {
163        return thread[tid].getLoadHeadSeqNum();
164    }
165
166    /** Returns the head index of the store queue. */
167    int getStoreHead(unsigned tid)
168    { return thread[tid].getStoreHead(); }
169
170    /** Returns the sequence number of the head of the store queue. */
171    InstSeqNum getStoreHeadSeqNum(unsigned tid)
172    {
173        return thread[tid].getStoreHeadSeqNum();
174    }
175
176    /** Returns the number of instructions in all of the queues. */
177    int getCount();
178    /** Returns the number of instructions in the queues of one thread. */
179    int getCount(unsigned tid)
180    { return thread[tid].getCount(); }
181
182    /** Returns the total number of loads in the load queue. */
183    int numLoads();
184    /** Returns the total number of loads for a single thread. */
185    int numLoads(unsigned tid)
186    { return thread[tid].numLoads(); }
187
188    /** Returns the total number of stores in the store queue. */
189    int numStores();
190    /** Returns the total number of stores for a single thread. */
191    int numStores(unsigned tid)
192    { return thread[tid].numStores(); }
193
194    /** Returns the total number of loads that are ready. */
195    int numLoadsReady();
196    /** Returns the number of loads that are ready for a single thread. */
197    int numLoadsReady(unsigned tid)
198    { return thread[tid].numLoadsReady(); }
199
200    /** Returns the number of free entries. */
201    unsigned numFreeEntries();
202    /** Returns the number of free entries for a specific thread. */
203    unsigned numFreeEntries(unsigned tid);
204
205    /** Returns if the LSQ is full (either LQ or SQ is full). */
206    bool isFull();
207    /**
208     * Returns if the LSQ is full for a specific thread (either LQ or SQ is
209     * full).
210     */
211    bool isFull(unsigned tid);
212
213    /** Returns if any of the LQs are full. */
214    bool lqFull();
215    /** Returns if the LQ of a given thread is full. */
216    bool lqFull(unsigned tid);
217
218    /** Returns if any of the SQs are full. */
219    bool sqFull();
220    /** Returns if the SQ of a given thread is full. */
221    bool sqFull(unsigned tid);
222
223    /**
224     * Returns if the LSQ is stalled due to a memory operation that must be
225     * replayed.
226     */
227    bool isStalled();
228    /**
229     * Returns if the LSQ of a specific thread is stalled due to a memory
230     * operation that must be replayed.
231     */
232    bool isStalled(unsigned tid);
233
234    /** Returns whether or not there are any stores to write back to memory. */
235    bool hasStoresToWB();
236
237    /** Returns whether or not a specific thread has any stores to write back
238     * to memory.
239     */
240    bool hasStoresToWB(unsigned tid)
241    { return thread[tid].hasStoresToWB(); }
242
243    /** Returns the number of stores a specific thread has to write back. */
244    int  numStoresToWB(unsigned tid)
245    { return thread[tid].numStoresToWB(); }
246
247    /** Returns if the LSQ will write back to memory this cycle. */
248    bool willWB();
249    /** Returns if the LSQ of a specific thread will write back to memory this
250     * cycle.
251     */
252    bool willWB(unsigned tid)
253    { return thread[tid].willWB(); }
254
255    /** Debugging function to print out all instructions. */
256    void dumpInsts();
257    /** Debugging function to print out instructions from a specific thread. */
258    void dumpInsts(unsigned tid)
259    { thread[tid].dumpInsts(); }
260
261    /** Executes a read operation, using the load specified at the load index. */
262    template <class T>
263    Fault read(RequestPtr req, T &data, int load_idx);
264
265    /** Executes a store operation, using the store specified at the store
266     *   index.
267     */
268    template <class T>
269    Fault write(RequestPtr req, T &data, int store_idx);
270
271  private:
272    /** The LSQ policy for SMT mode. */
273    LSQPolicy lsqPolicy;
274
275    /** The LSQ units for individual threads. */
276    LSQUnit thread[Impl::MaxThreads];
277
278    /** The CPU pointer. */
279    FullCPU *cpu;
280
281    /** The IEW stage pointer. */
282    IEW *iewStage;
283
284    /** The pointer to the page table. */
285//    PageTable *pTable;
286
287    /** List of Active Threads in System. */
288    std::list<unsigned> *activeThreads;
289
290    /** Total Size of LQ Entries. */
291    unsigned LQEntries;
292    /** Total Size of SQ Entries. */
293    unsigned SQEntries;
294
295    /** Max LQ Size - Used to Enforce Sharing Policies. */
296    unsigned maxLQEntries;
297
298    /** Max SQ Size - Used to Enforce Sharing Policies. */
299    unsigned maxSQEntries;
300
301    /** Number of Threads. */
302    unsigned numThreads;
303};
304
305template <class Impl>
306template <class T>
307Fault
308LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
309{
310    unsigned tid = req->getThreadNum();
311
312    return thread[tid].read(req, data, load_idx);
313}
314
315template <class Impl>
316template <class T>
317Fault
318LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
319{
320    unsigned tid = req->getThreadNum();
321
322    return thread[tid].write(req, data, store_idx);
323}
324
325#endif // __CPU_O3_LSQ_HH__
326