inst_queue_impl.hh revision 9444
11689SN/A/* 210333Smitch.hayenga@arm.com * Copyright (c) 2011-2012 ARM Limited 39920Syasuko.eckert@amd.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137944SGiacomo.Gabrielli@arm.com * 147944SGiacomo.Gabrielli@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 152326SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 391689SN/A * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412665Ssaidi@eecs.umich.edu * Korey Sewell 422831Sksewell@umich.edu */ 431689SN/A 441689SN/A#include <limits> 459944Smatt.horsnell@ARM.com#include <vector> 469944Smatt.horsnell@ARM.com 479944Smatt.horsnell@ARM.com#include "cpu/o3/fu_pool.hh" 482064SN/A#include "cpu/o3/inst_queue.hh" 491060SN/A#include "debug/IQ.hh" 501060SN/A#include "enums/OpClass.hh" 5113449Sgabeblack@google.com#include "params/DerivO3CPU.hh" 522292SN/A#include "sim/core.hh" 531717SN/A 548232Snate@binkert.org// clang complains about std::set being overloaded with Packet::set if 554762Snate@binkert.org// we open up the entire namespace std 566221Snate@binkert.orgusing std::list; 574762Snate@binkert.org 581060SN/Atemplate <class Impl> 598737Skoansin.tan@gmail.comInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 608737Skoansin.tan@gmail.com int fu_idx, InstructionQueue<Impl> *iq_ptr) 618737Skoansin.tan@gmail.com : Event(Stat_Event_Pri, AutoDelete), 625529Snate@binkert.org inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 631061SN/A{ 6413429Srekai.gonzalezalberquilla@arm.com} 655606Snate@binkert.org 668581Ssteve.reinhardt@amd.comtemplate <class Impl> 678581Ssteve.reinhardt@amd.comvoid 681060SN/AInstructionQueue<Impl>::FUCompletion::process() 692292SN/A{ 702292SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 712292SN/A inst = NULL; 722292SN/A} 732292SN/A 742292SN/A 752326SN/Atemplate <class Impl> 762292SN/Aconst char * 772292SN/AInstructionQueue<Impl>::FUCompletion::description() const 782292SN/A{ 792292SN/A return "Functional unit completion"; 802292SN/A} 812292SN/A 825336Shines@cs.fsu.edutemplate <class Impl> 832292SN/AInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 844873Sstever@eecs.umich.edu DerivO3CPUParams *params) 852292SN/A : cpu(cpu_ptr), 862292SN/A iewStage(iew_ptr), 872292SN/A fuPool(params->fuPool), 884329Sktlim@umich.edu numEntries(params->numIQEntries), 895529Snate@binkert.org totalWidth(params->issueWidth), 904329Sktlim@umich.edu numPhysIntRegs(params->numPhysIntRegs), 914329Sktlim@umich.edu numPhysFloatRegs(params->numPhysFloatRegs), 924329Sktlim@umich.edu commitToIEWDelay(params->commitToIEWDelay) 932292SN/A{ 942292SN/A assert(fuPool); 952292SN/A 962292SN/A numThreads = params->numThreads; 972292SN/A 982292SN/A // Set the number of physical registers as the number of int + float 995529Snate@binkert.org numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 1001060SN/A 1019920Syasuko.eckert@amd.com //Create an entry for each physical register within the 10212109SRekai.GonzalezAlberquilla@arm.com //dependency graph. 1039920Syasuko.eckert@amd.com dependGraph.resize(numPhysRegs); 10412109SRekai.GonzalezAlberquilla@arm.com 10512109SRekai.GonzalezAlberquilla@arm.com // Resize the register scoreboard. 10612109SRekai.GonzalezAlberquilla@arm.com regScoreboard.resize(numPhysRegs); 1071060SN/A 1081060SN/A //Initialize Mem Dependence Units 1091060SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1102326SN/A memDepUnit[tid].init(params, tid); 1111060SN/A memDepUnit[tid].setIQ(this); 1121060SN/A } 1131060SN/A 1141060SN/A resetState(); 1152292SN/A 1166221Snate@binkert.org std::string policy = params->smtIQPolicy; 1176221Snate@binkert.org 1186221Snate@binkert.org //Convert string to lowercase 1191060SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1201060SN/A (int(*)(int)) tolower); 1212307SN/A 1222292SN/A //Figure out resource sharing policy 1232980Sgblack@eecs.umich.edu if (policy == "dynamic") { 1242292SN/A iqPolicy = Dynamic; 1252292SN/A 1262292SN/A //Set Max Entries to Total ROB Capacity 1272292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1282292SN/A maxEntries[tid] = numEntries; 1292292SN/A } 1302292SN/A 1312292SN/A } else if (policy == "partitioned") { 1322292SN/A iqPolicy = Partitioned; 1332292SN/A 1346221Snate@binkert.org //@todo:make work if part_amt doesnt divide evenly. 1356221Snate@binkert.org int part_amt = numEntries / numThreads; 1362292SN/A 1372292SN/A //Divide ROB up evenly 1382292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1392292SN/A maxEntries[tid] = part_amt; 1402292SN/A } 1412292SN/A 1422292SN/A DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1432292SN/A "%i entries per thread.\n",part_amt); 1442292SN/A } else if (policy == "threshold") { 1456221Snate@binkert.org iqPolicy = Threshold; 1466221Snate@binkert.org 1472292SN/A double threshold = (double)params->smtIQThreshold / 100; 1482292SN/A 1492831Sksewell@umich.edu int thresholdIQ = (int)((double)threshold * numEntries); 1502292SN/A 1512292SN/A //Divide up by threshold amount 1522292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1532292SN/A maxEntries[tid] = thresholdIQ; 1542292SN/A } 1552292SN/A 1562292SN/A DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1572292SN/A "%i entries per thread.\n",thresholdIQ); 1582292SN/A } else { 1596221Snate@binkert.org assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1606221Snate@binkert.org "Partitioned, Threshold}"); 1612292SN/A } 1622292SN/A} 1632831Sksewell@umich.edu 1642292SN/Atemplate <class Impl> 1652292SN/AInstructionQueue<Impl>::~InstructionQueue() 16613449Sgabeblack@google.com{ 16713449Sgabeblack@google.com dependGraph.reset(); 1682292SN/A#ifdef DEBUG 1692292SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1702292SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1712292SN/A#endif 1722292SN/A} 1732292SN/A 1742326SN/Atemplate <class Impl> 1752348SN/Astd::string 1762326SN/AInstructionQueue<Impl>::name() const 1772326SN/A{ 1782348SN/A return cpu->name() + ".iq"; 1792292SN/A} 1802292SN/A 1812292SN/Atemplate <class Impl> 1822292SN/Avoid 1832292SN/AInstructionQueue<Impl>::regStats() 1842292SN/A{ 1852292SN/A using namespace Stats; 1861060SN/A iqInstsAdded 1871060SN/A .name(name() + ".iqInstsAdded") 1881061SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1891060SN/A .prereq(iqInstsAdded); 1901062SN/A 1911062SN/A iqNonSpecInstsAdded 1922301SN/A .name(name() + ".iqNonSpecInstsAdded") 1931062SN/A .desc("Number of non-speculative instructions added to the IQ") 1941062SN/A .prereq(iqNonSpecInstsAdded); 1951062SN/A 1961062SN/A iqInstsIssued 1971062SN/A .name(name() + ".iqInstsIssued") 1981062SN/A .desc("Number of instructions issued") 1991062SN/A .prereq(iqInstsIssued); 2001062SN/A 2011062SN/A iqIntInstsIssued 2021062SN/A .name(name() + ".iqIntInstsIssued") 2032301SN/A .desc("Number of integer instructions issued") 2042301SN/A .prereq(iqIntInstsIssued); 2052301SN/A 2062301SN/A iqFloatInstsIssued 2071062SN/A .name(name() + ".iqFloatInstsIssued") 2081062SN/A .desc("Number of float instructions issued") 2091062SN/A .prereq(iqFloatInstsIssued); 2101062SN/A 2111062SN/A iqBranchInstsIssued 2121062SN/A .name(name() + ".iqBranchInstsIssued") 2131062SN/A .desc("Number of branch instructions issued") 2141062SN/A .prereq(iqBranchInstsIssued); 2151062SN/A 2161062SN/A iqMemInstsIssued 2171062SN/A .name(name() + ".iqMemInstsIssued") 2181062SN/A .desc("Number of memory instructions issued") 2191062SN/A .prereq(iqMemInstsIssued); 2201062SN/A 2211062SN/A iqMiscInstsIssued 2221062SN/A .name(name() + ".iqMiscInstsIssued") 2231062SN/A .desc("Number of miscellaneous instructions issued") 2241062SN/A .prereq(iqMiscInstsIssued); 2251062SN/A 2261062SN/A iqSquashedInstsIssued 2271062SN/A .name(name() + ".iqSquashedInstsIssued") 2281062SN/A .desc("Number of squashed instructions issued") 2291062SN/A .prereq(iqSquashedInstsIssued); 2301062SN/A 2311062SN/A iqSquashedInstsExamined 2321062SN/A .name(name() + ".iqSquashedInstsExamined") 2331062SN/A .desc("Number of squashed instructions iterated over during squash;" 2341062SN/A " mainly for profiling") 2351062SN/A .prereq(iqSquashedInstsExamined); 2361062SN/A 2371062SN/A iqSquashedOperandsExamined 2381062SN/A .name(name() + ".iqSquashedOperandsExamined") 2391062SN/A .desc("Number of squashed operands that are examined and possibly " 2401062SN/A "removed from graph") 2411062SN/A .prereq(iqSquashedOperandsExamined); 2421062SN/A 2431062SN/A iqSquashedNonSpecRemoved 2441062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2451062SN/A .desc("Number of squashed non-spec instructions that were removed") 2461062SN/A .prereq(iqSquashedNonSpecRemoved); 2471062SN/A/* 2481062SN/A queueResDist 2491062SN/A .init(Num_OpClasses, 0, 99, 2) 2501062SN/A .name(name() + ".IQ:residence:") 2511062SN/A .desc("cycles from dispatch to issue") 2521062SN/A .flags(total | pdf | cdf ) 2531062SN/A ; 2542361SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2552326SN/A queueResDist.subname(i, opClassStrings[i]); 2562301SN/A } 2572301SN/A*/ 2582301SN/A numIssuedDist 2592301SN/A .init(0,totalWidth,1) 2602301SN/A .name(name() + ".issued_per_cycle") 2612301SN/A .desc("Number of insts issued each cycle") 2622326SN/A .flags(pdf) 2632301SN/A ; 2642361SN/A/* 2652326SN/A dist_unissued 2662307SN/A .init(Num_OpClasses+2) 2678240Snate@binkert.org .name(name() + ".unissued_cause") 2682301SN/A .desc("Reason ready instruction not issued") 2692307SN/A .flags(pdf | dist) 2702301SN/A ; 2712301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2722301SN/A dist_unissued.subname(i, unissued_names[i]); 2732301SN/A } 2748240Snate@binkert.org*/ 2752301SN/A statIssuedInstType 2762301SN/A .init(numThreads,Enums::Num_OpClass) 2772301SN/A .name(name() + ".FU_type") 2782301SN/A .desc("Type of FU issued") 2792301SN/A .flags(total | pdf | dist) 2802301SN/A ; 2812301SN/A statIssuedInstType.ysubnames(Enums::OpClassStrings); 2822326SN/A 2834762Snate@binkert.org // 2848240Snate@binkert.org // How long did instructions for a particular FU type wait prior to issue 2852301SN/A // 2862301SN/A/* 2872301SN/A issueDelayDist 2884762Snate@binkert.org .init(Num_OpClasses,0,99,2) 2892301SN/A .name(name() + ".") 2902301SN/A .desc("cycles from operands ready to issue") 2912301SN/A .flags(pdf | cdf) 2922301SN/A ; 2932361SN/A 2942326SN/A for (int i=0; i<Num_OpClasses; ++i) { 2952301SN/A std::stringstream subname; 2968240Snate@binkert.org subname << opClassStrings[i] << "_delay"; 2972301SN/A issueDelayDist.subname(i, subname.str()); 2982301SN/A } 2992301SN/A*/ 3002301SN/A issueRate 3012301SN/A .name(name() + ".rate") 3022980Sgblack@eecs.umich.edu .desc("Inst issue rate") 3032301SN/A .flags(total) 3042326SN/A ; 3052301SN/A issueRate = iqInstsIssued / cpu->numCycles; 3062361SN/A 3072326SN/A statFuBusy 3088240Snate@binkert.org .init(Num_OpClasses) 3092301SN/A .name(name() + ".fu_full") 3102301SN/A .desc("attempts to use FU when none available") 3112301SN/A .flags(pdf | dist) 3122326SN/A ; 3132727Sktlim@umich.edu for (int i=0; i < Num_OpClasses; ++i) { 3142326SN/A statFuBusy.subname(i, Enums::OpClassStrings[i]); 3152301SN/A } 3168240Snate@binkert.org 3172301SN/A fuBusy 3182301SN/A .init(numThreads) 3192301SN/A .name(name() + ".fu_busy_cnt") 3202301SN/A .desc("FU busy when requested") 3214762Snate@binkert.org .flags(total) 3222301SN/A ; 3232301SN/A 3242326SN/A fuBusyRate 3252301SN/A .name(name() + ".fu_busy_rate") 3268240Snate@binkert.org .desc("FU busy rate (busy events/executed inst)") 3272301SN/A .flags(total) 3282301SN/A ; 3292301SN/A fuBusyRate = fuBusy / iqInstsIssued; 3302301SN/A 3312326SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3328240Snate@binkert.org // Tell mem dependence unit to reg stats as well. 3332301SN/A memDepUnit[tid].regStats(); 3342301SN/A } 3352301SN/A 3362326SN/A intInstQueueReads 3372301SN/A .name(name() + ".int_inst_queue_reads") 3386221Snate@binkert.org .desc("Number of integer instruction queue reads") 3392292SN/A .flags(total); 3406221Snate@binkert.org 3412292SN/A intInstQueueWrites 3427897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3437897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3447897Shestness@cs.utexas.edu .flags(total); 3457897Shestness@cs.utexas.edu 3467897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3477897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3487897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3497897Shestness@cs.utexas.edu .flags(total); 3507897Shestness@cs.utexas.edu 3517897Shestness@cs.utexas.edu fpInstQueueReads 3527897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3537897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3547897Shestness@cs.utexas.edu .flags(total); 3557897Shestness@cs.utexas.edu 3567897Shestness@cs.utexas.edu fpInstQueueWrites 3577897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3587897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3597897Shestness@cs.utexas.edu .flags(total); 3607897Shestness@cs.utexas.edu 3617897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses 3627897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3637897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3647897Shestness@cs.utexas.edu .flags(total); 3657897Shestness@cs.utexas.edu 3667897Shestness@cs.utexas.edu intAluAccesses 3677897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 36812110SRekai.GonzalezAlberquilla@arm.com .desc("Number of integer alu accesses") 3697897Shestness@cs.utexas.edu .flags(total); 3707897Shestness@cs.utexas.edu 3717897Shestness@cs.utexas.edu fpAluAccesses 3727897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 37312319Sandreas.sandberg@arm.com .desc("Number of floating point alu accesses") 37412319Sandreas.sandberg@arm.com .flags(total); 37512319Sandreas.sandberg@arm.com 37612319Sandreas.sandberg@arm.com} 37712319Sandreas.sandberg@arm.com 37812319Sandreas.sandberg@arm.comtemplate <class Impl> 37912319Sandreas.sandberg@arm.comvoid 38012319Sandreas.sandberg@arm.comInstructionQueue<Impl>::resetState() 38112319Sandreas.sandberg@arm.com{ 38212319Sandreas.sandberg@arm.com //Initialize thread IQ counts 38312319Sandreas.sandberg@arm.com for (ThreadID tid = 0; tid <numThreads; tid++) { 38412319Sandreas.sandberg@arm.com count[tid] = 0; 38512319Sandreas.sandberg@arm.com instList[tid].clear(); 38612319Sandreas.sandberg@arm.com } 38712319Sandreas.sandberg@arm.com 3887897Shestness@cs.utexas.edu // Initialize the number of free IQ entries. 3897897Shestness@cs.utexas.edu freeEntries = numEntries; 3907897Shestness@cs.utexas.edu 3917897Shestness@cs.utexas.edu // Note that in actuality, the registers corresponding to the logical 3927897Shestness@cs.utexas.edu // registers start off as ready. However this doesn't matter for the 3937897Shestness@cs.utexas.edu // IQ as the instruction should have been correctly told if those 3947897Shestness@cs.utexas.edu // registers are ready in rename. Thus it can all be initialized as 3957897Shestness@cs.utexas.edu // unready. 3967897Shestness@cs.utexas.edu for (int i = 0; i < numPhysRegs; ++i) { 3977897Shestness@cs.utexas.edu regScoreboard[i] = false; 39812319Sandreas.sandberg@arm.com } 39912319Sandreas.sandberg@arm.com 40012319Sandreas.sandberg@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 40112319Sandreas.sandberg@arm.com squashedSeqNum[tid] = 0; 40212319Sandreas.sandberg@arm.com } 4031062SN/A 4041062SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4051062SN/A while (!readyInsts[i].empty()) 4061062SN/A readyInsts[i].pop(); 4072307SN/A queueOnList[i] = false; 4081060SN/A readyIt[i] = listOrder.end(); 4092307SN/A } 4106221Snate@binkert.org nonSpecInsts.clear(); 4116221Snate@binkert.org listOrder.clear(); 4126221Snate@binkert.org deferredMemInsts.clear(); 4132307SN/A} 4141060SN/A 4152307SN/Atemplate <class Impl> 4162307SN/Avoid 4172307SN/AInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4182307SN/A{ 4192307SN/A activeThreads = at_ptr; 4202307SN/A} 4212307SN/A 4222307SN/Atemplate <class Impl> 4232307SN/Avoid 4242307SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4252307SN/A{ 4262307SN/A issueToExecuteQueue = i2e_ptr; 4276221Snate@binkert.org} 4286221Snate@binkert.org 4292307SN/Atemplate <class Impl> 4302307SN/Avoid 4312307SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4322307SN/A{ 4332307SN/A timeBuffer = tb_ptr; 4342307SN/A 4352307SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4362307SN/A} 4372307SN/A 4382307SN/Atemplate <class Impl> 4397944SGiacomo.Gabrielli@arm.comvoid 44010333Smitch.hayenga@arm.comInstructionQueue<Impl>::drainSanityCheck() const 44110333Smitch.hayenga@arm.com{ 44210511Smitch.hayenga@arm.com assert(dependGraph.empty()); 4431060SN/A assert(instsToExecute.empty()); 4441060SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) 4451061SN/A memDepUnit[tid].drainSanityCheck(); 4461060SN/A} 4476221Snate@binkert.org 4481060SN/Atemplate <class Impl> 4492292SN/Avoid 4502064SN/AInstructionQueue<Impl>::takeOverFrom() 4512064SN/A{ 4522064SN/A resetState(); 4532064SN/A} 4542292SN/A 4552064SN/Atemplate <class Impl> 4564318Sktlim@umich.eduint 4571060SN/AInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4581060SN/A{ 4591061SN/A if (iqPolicy == Partitioned) { 4601060SN/A return numEntries / num_threads; 4611060SN/A } else { 4621060SN/A return 0; 4631060SN/A } 4641060SN/A} 4651060SN/A 4661060SN/A 4671060SN/Atemplate <class Impl> 4681684SN/Avoid 46910510Smitch.hayenga@arm.comInstructionQueue<Impl>::resetEntries() 47010510Smitch.hayenga@arm.com{ 47110510Smitch.hayenga@arm.com if (iqPolicy != Dynamic || numThreads > 1) { 47210511Smitch.hayenga@arm.com int active_threads = activeThreads->size(); 47310511Smitch.hayenga@arm.com 47410511Smitch.hayenga@arm.com list<ThreadID>::iterator threads = activeThreads->begin(); 47510510Smitch.hayenga@arm.com list<ThreadID>::iterator end = activeThreads->end(); 47610510Smitch.hayenga@arm.com 47710510Smitch.hayenga@arm.com while (threads != end) { 47810510Smitch.hayenga@arm.com ThreadID tid = *threads++; 47910510Smitch.hayenga@arm.com 48010510Smitch.hayenga@arm.com if (iqPolicy == Partitioned) { 48110510Smitch.hayenga@arm.com maxEntries[tid] = numEntries / active_threads; 4822307SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4839444SAndreas.Sandberg@ARM.com maxEntries[tid] = numEntries; 4842307SN/A } 4859444SAndreas.Sandberg@ARM.com } 4869444SAndreas.Sandberg@ARM.com } 4879444SAndreas.Sandberg@ARM.com} 4889444SAndreas.Sandberg@ARM.com 4892307SN/Atemplate <class Impl> 4902307SN/Aunsigned 4912307SN/AInstructionQueue<Impl>::numFreeEntries() 4922307SN/A{ 4932307SN/A return freeEntries; 4942307SN/A} 4959444SAndreas.Sandberg@ARM.com 4962307SN/Atemplate <class Impl> 4972307SN/Aunsigned 4982307SN/AInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 4992292SN/A{ 5006221Snate@binkert.org return maxEntries[tid] - count[tid]; 5012292SN/A} 5022292SN/A 5032292SN/A// Might want to do something more complex if it knows how many instructions 5042292SN/A// will be issued this cycle. 5052292SN/Atemplate <class Impl> 5062292SN/Abool 5072292SN/AInstructionQueue<Impl>::isFull() 5082292SN/A{ 5092292SN/A if (freeEntries == 0) { 5102292SN/A return(true); 5112292SN/A } else { 5122292SN/A return(false); 5132292SN/A } 5142292SN/A} 5153867Sbinkertn@umich.edu 5162292SN/Atemplate <class Impl> 5176221Snate@binkert.orgbool 5186221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid) 5192292SN/A{ 5203867Sbinkertn@umich.edu if (numFreeEntries(tid) == 0) { 5216221Snate@binkert.org return(true); 5223867Sbinkertn@umich.edu } else { 5232292SN/A return(false); 5243867Sbinkertn@umich.edu } 52511321Ssteve.reinhardt@amd.com} 5263867Sbinkertn@umich.edu 5272292SN/Atemplate <class Impl> 5282292SN/Abool 5292292SN/AInstructionQueue<Impl>::hasReadyInsts() 5302292SN/A{ 5312292SN/A if (!listOrder.empty()) { 5322292SN/A return true; 5331684SN/A } 5341684SN/A 5351684SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5361684SN/A if (!readyInsts[i].empty()) { 5371684SN/A return true; 5381684SN/A } 5392292SN/A } 5402292SN/A 5416221Snate@binkert.org return false; 5422292SN/A} 5432292SN/A 5442292SN/Atemplate <class Impl> 5452292SN/Avoid 5461060SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5471060SN/A{ 5481061SN/A new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5491060SN/A // Make sure the instruction is valid 5501060SN/A assert(new_inst); 5511060SN/A 5521060SN/A DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5531060SN/A new_inst->seqNum, new_inst->pcState()); 5541060SN/A 5551060SN/A assert(freeEntries != 0); 5561060SN/A 5571060SN/A instList[new_inst->threadNumber].push_back(new_inst); 5581060SN/A 5591061SN/A --freeEntries; 5602292SN/A 5616221Snate@binkert.org new_inst->setInIQ(); 5622292SN/A 5632292SN/A // Look through its source registers (physical regs), and mark any 5642292SN/A // dependencies. 5652292SN/A addToDependents(new_inst); 5662292SN/A 5672292SN/A // Have this instruction set itself as the producer of its destination 5682292SN/A // register(s). 5692292SN/A addToProducers(new_inst); 5702292SN/A 5712292SN/A if (new_inst->isMemRef()) { 5722292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5732292SN/A } else { 5742292SN/A addIfReady(new_inst); 5752292SN/A } 5762292SN/A 5772292SN/A ++iqInstsAdded; 5782292SN/A 5792292SN/A count[new_inst->threadNumber]++; 5802292SN/A 5812292SN/A assert(freeEntries == (numEntries - countInsts())); 5822292SN/A} 5832292SN/A 5842292SN/Atemplate <class Impl> 5852292SN/Avoid 5862292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5872292SN/A{ 5881060SN/A // @todo: Clean up this code; can do it by setting inst as unable 58913429Srekai.gonzalezalberquilla@arm.com // to issue, then calling normal insert on the inst. 5901060SN/A new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 59112110SRekai.GonzalezAlberquilla@arm.com 59212110SRekai.GonzalezAlberquilla@arm.com assert(new_inst); 59312110SRekai.GonzalezAlberquilla@arm.com 59412110SRekai.GonzalezAlberquilla@arm.com nonSpecInsts[new_inst->seqNum] = new_inst; 59512110SRekai.GonzalezAlberquilla@arm.com 59612110SRekai.GonzalezAlberquilla@arm.com DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 59712110SRekai.GonzalezAlberquilla@arm.com "to the IQ.\n", 5981060SN/A new_inst->seqNum, new_inst->pcState()); 5991060SN/A 6001060SN/A assert(freeEntries != 0); 6017720Sgblack@eecs.umich.edu 6027720Sgblack@eecs.umich.edu instList[new_inst->threadNumber].push_back(new_inst); 6031060SN/A 6041060SN/A --freeEntries; 6051060SN/A 6062292SN/A new_inst->setInIQ(); 6071060SN/A 6082064SN/A // Have this instruction set itself as the producer of its destination 6091060SN/A // register(s). 6102292SN/A addToProducers(new_inst); 6111060SN/A 6121060SN/A // If it's a memory instruction, add it to the memory dependency 6131060SN/A // unit. 6141060SN/A if (new_inst->isMemRef()) { 6151060SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6161060SN/A } 6171060SN/A 6182326SN/A ++iqNonSpecInstsAdded; 6191060SN/A 6201061SN/A count[new_inst->threadNumber]++; 6212292SN/A 6221062SN/A assert(freeEntries == (numEntries - countInsts())); 6231062SN/A} 6241061SN/A 6251061SN/Atemplate <class Impl> 6261062SN/Avoid 6271060SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 6282292SN/A{ 6292292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6301060SN/A 6311060SN/A insertNonSpec(barr_inst); 6321060SN/A} 6331061SN/A 6341061SN/Atemplate <class Impl> 63513429Srekai.gonzalezalberquilla@arm.comtypename Impl::DynInstPtr 6361061SN/AInstructionQueue<Impl>::getInstToExecute() 6371061SN/A{ 6381061SN/A assert(!instsToExecute.empty()); 63912110SRekai.GonzalezAlberquilla@arm.com DynInstPtr inst = instsToExecute.front(); 64012110SRekai.GonzalezAlberquilla@arm.com instsToExecute.pop_front(); 64112110SRekai.GonzalezAlberquilla@arm.com if (inst->isFloating()){ 64212110SRekai.GonzalezAlberquilla@arm.com fpInstQueueReads++; 64312110SRekai.GonzalezAlberquilla@arm.com } else { 64412110SRekai.GonzalezAlberquilla@arm.com intInstQueueReads++; 64512110SRekai.GonzalezAlberquilla@arm.com } 6461061SN/A return inst; 6472292SN/A} 6481061SN/A 6492292SN/Atemplate <class Impl> 6501061SN/Avoid 6517720Sgblack@eecs.umich.eduInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6522326SN/A{ 6537720Sgblack@eecs.umich.edu assert(!readyInsts[op_class].empty()); 6542064SN/A 6551061SN/A ListOrderEntry queue_entry; 6561061SN/A 6572292SN/A queue_entry.queueType = op_class; 6581061SN/A 6592064SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6601061SN/A 6612292SN/A ListOrderIt list_it = listOrder.begin(); 6621061SN/A ListOrderIt list_end_it = listOrder.end(); 6631061SN/A 6641061SN/A while (list_it != list_end_it) { 6652326SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6661061SN/A break; 6671061SN/A } 6681061SN/A 6692292SN/A list_it++; 6702292SN/A } 6711061SN/A 6721062SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6731062SN/A queueOnList[op_class] = true; 6742292SN/A} 6752292SN/A 6762292SN/Atemplate <class Impl> 6772292SN/Avoid 6781061SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6791061SN/A{ 6801061SN/A // Get iterator of next item on the list 6811060SN/A // Delete the original iterator 68213429Srekai.gonzalezalberquilla@arm.com // Determine if the next item is either the end of the list or younger 6831060SN/A // than the new instruction. If so, then add in a new iterator right here. 6842292SN/A // If not, then move along. 6851060SN/A ListOrderEntry queue_entry; 6862292SN/A OpClass op_class = (*list_order_it).queueType; 6872292SN/A ListOrderIt next_it = list_order_it; 6881060SN/A 6892064SN/A ++next_it; 6902333SN/A 6912333SN/A queue_entry.queueType = op_class; 6922333SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6932333SN/A 69413429Srekai.gonzalezalberquilla@arm.com while (next_it != listOrder.end() && 6952333SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 69612110SRekai.GonzalezAlberquilla@arm.com ++next_it; 6977897Shestness@cs.utexas.edu } 69812110SRekai.GonzalezAlberquilla@arm.com 69912110SRekai.GonzalezAlberquilla@arm.com readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7007897Shestness@cs.utexas.edu} 7017897Shestness@cs.utexas.edu 7027897Shestness@cs.utexas.edutemplate <class Impl> 7032333SN/Avoid 7042333SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 7051060SN/A{ 7062333SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7072064SN/A assert(!cpu->switchedOut()); 7082292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7092292SN/A // long latency op). Wake it if it was. This may be overkill. 7102292SN/A iewStage->wakeCPU(); 7112292SN/A 7122292SN/A if (fu_idx > -1) 7132292SN/A fuPool->freeUnitNextCycle(fu_idx); 7142292SN/A 7152292SN/A // @todo: Ensure that these FU Completions happen at the beginning 7162292SN/A // of a cycle, otherwise they could add too many instructions to 7172292SN/A // the queue. 7182292SN/A issueToExecuteQueue->access(-1)->size++; 7192292SN/A instsToExecute.push_back(inst); 7202292SN/A} 7212292SN/A 7222292SN/A// @todo: Figure out a better way to remove the squashed items from the 7232292SN/A// lists. Checking the top item of each list to see if it's squashed 7242292SN/A// wastes time and forces jumps. 7252292SN/Atemplate <class Impl> 7262292SN/Avoid 7271060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7281060SN/A{ 7292292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7302292SN/A "the IQ.\n"); 7312292SN/A 7321060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7332292SN/A 7342292SN/A DynInstPtr deferred_mem_inst; 7352292SN/A int total_deferred_mem_issued = 0; 7362292SN/A while (total_deferred_mem_issued < totalWidth && 7372292SN/A (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { 7382292SN/A issueToExecuteQueue->access(0)->size++; 7392292SN/A instsToExecute.push_back(deferred_mem_inst); 7402292SN/A total_deferred_mem_issued++; 7412292SN/A } 7422292SN/A 7432292SN/A // Have iterator to head of the list 7442292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7452292SN/A // Try to get a FU that can do what this op needs. 7462292SN/A // If successful, change the oldestInst to the new top of the list, put 7472292SN/A // the queue in the proper place in the list. 7482292SN/A // Increment the iterator. 7492292SN/A // This will avoid trying to schedule a certain op class if there are no 7502292SN/A // FUs that handle it. 7512292SN/A ListOrderIt order_it = listOrder.begin(); 7522292SN/A ListOrderIt order_end_it = listOrder.end(); 7532292SN/A int total_issued = 0; 7541060SN/A 7551060SN/A while (total_issued < (totalWidth - total_deferred_mem_issued) && 7562292SN/A iewStage->canIssue() && 7571060SN/A order_it != order_end_it) { 7581060SN/A OpClass op_class = (*order_it).queueType; 7592292SN/A 7602292SN/A assert(!readyInsts[op_class].empty()); 76113429Srekai.gonzalezalberquilla@arm.com 7622292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7632367SN/A 7649444SAndreas.Sandberg@ARM.com issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 7652292SN/A 7662292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 76710511Smitch.hayenga@arm.com 7682292SN/A if (issuing_inst->isSquashed()) { 7692292SN/A readyInsts[op_class].pop(); 7702326SN/A 7712326SN/A if (!readyInsts[op_class].empty()) { 7722292SN/A moveToYoungerInst(order_it); 7732326SN/A } else { 7742326SN/A readyIt[op_class] = listOrder.end(); 7752326SN/A queueOnList[op_class] = false; 7765327Smengke97@hotmail.com } 7772333SN/A 7782292SN/A listOrder.erase(order_it++); 7792292SN/A 7801061SN/A ++iqSquashedInstsIssued; 7811061SN/A 7821061SN/A continue; 7831061SN/A } 7841060SN/A 7851060SN/A int idx = -2; 7861060SN/A Cycles op_latency = Cycles(1); 7872292SN/A ThreadID tid = issuing_inst->threadNumber; 7882292SN/A 7891060SN/A if (op_class != No_OpClass) { 7901060SN/A idx = fuPool->getUnit(op_class); 7911060SN/A issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 79210333Smitch.hayenga@arm.com if (idx > -1) { 79313429Srekai.gonzalezalberquilla@arm.com op_latency = fuPool->getOpLatency(op_class); 79410333Smitch.hayenga@arm.com } 79510333Smitch.hayenga@arm.com } 79610333Smitch.hayenga@arm.com 79710333Smitch.hayenga@arm.com // If we have an instruction that doesn't require a FU, or a 79813429Srekai.gonzalezalberquilla@arm.com // valid FU, then schedule for execution. 79910333Smitch.hayenga@arm.com if (idx == -2 || idx != -1) { 8007944SGiacomo.Gabrielli@arm.com if (op_latency == Cycles(1)) { 8017944SGiacomo.Gabrielli@arm.com i2e_info->size++; 8022292SN/A instsToExecute.push_back(issuing_inst); 8032292SN/A 8042292SN/A // Add the FU onto the list of FU's to be freed next 8052292SN/A // cycle if we used one. 8062292SN/A if (idx >= 0) 8072292SN/A fuPool->freeUnitNextCycle(idx); 8082292SN/A } else { 8092292SN/A Cycles issue_latency = fuPool->getIssueLatency(op_class); 81010333Smitch.hayenga@arm.com // Generate completion event for the FU 8112292SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8122292SN/A idx, this); 8131060SN/A 81410333Smitch.hayenga@arm.com cpu->schedule(execution, 8152292SN/A cpu->clockEdge(Cycles(op_latency - 1))); 8161060SN/A 8172292SN/A // @todo: Enforce that issue_latency == 1 or op_latency 8181060SN/A if (issue_latency > Cycles(1)) { 8192292SN/A // If FU isn't pipelined, then it must be freed 8201060SN/A // upon the execution completing. 82112110SRekai.GonzalezAlberquilla@arm.com execution->setFreeFU(); 82212110SRekai.GonzalezAlberquilla@arm.com } else { 82312110SRekai.GonzalezAlberquilla@arm.com // Add the FU onto the list of FU's to be freed next cycle. 82412110SRekai.GonzalezAlberquilla@arm.com fuPool->freeUnitNextCycle(idx); 82512110SRekai.GonzalezAlberquilla@arm.com } 82612110SRekai.GonzalezAlberquilla@arm.com } 82712110SRekai.GonzalezAlberquilla@arm.com 8287897Shestness@cs.utexas.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8292292SN/A "[sn:%lli]\n", 8301060SN/A tid, issuing_inst->pcState(), 8312292SN/A issuing_inst->seqNum); 8322292SN/A 8331060SN/A readyInsts[op_class].pop(); 8342292SN/A 8352292SN/A if (!readyInsts[op_class].empty()) { 8362292SN/A moveToYoungerInst(order_it); 8372292SN/A } else { 8382292SN/A readyIt[op_class] = listOrder.end(); 8391060SN/A queueOnList[op_class] = false; 8401060SN/A } 8412292SN/A 8421060SN/A issuing_inst->setIssued(); 8432292SN/A ++total_issued; 8442292SN/A 8452292SN/A#if TRACING_ON 8461060SN/A issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 8471060SN/A#endif 84811365SRekai.GonzalezAlberquilla@arm.com 8499184Sandreas.hansson@arm.com if (!issuing_inst->isMemRef()) { 8506221Snate@binkert.org // Memory instructions can not be freed from the IQ until they 8511060SN/A // complete. 8522326SN/A ++freeEntries; 8532326SN/A count[tid]--; 85412110SRekai.GonzalezAlberquilla@arm.com issuing_inst->clearInIQ(); 85512110SRekai.GonzalezAlberquilla@arm.com } else { 85612110SRekai.GonzalezAlberquilla@arm.com memDepUnit[tid].issue(issuing_inst); 85712110SRekai.GonzalezAlberquilla@arm.com } 85812110SRekai.GonzalezAlberquilla@arm.com 85912110SRekai.GonzalezAlberquilla@arm.com listOrder.erase(order_it++); 86012110SRekai.GonzalezAlberquilla@arm.com statIssuedInstType[tid][op_class]++; 86111365SRekai.GonzalezAlberquilla@arm.com iewStage->incrWb(issuing_inst->seqNum); 8622326SN/A } else { 8631060SN/A statFuBusy[op_class]++; 8641060SN/A fuBusy[tid]++; 8651060SN/A ++order_it; 8662348SN/A } 8672348SN/A } 86811365SRekai.GonzalezAlberquilla@arm.com 8699184Sandreas.hansson@arm.com numIssuedDist.sample(total_issued); 8702292SN/A iqInstsIssued+= total_issued; 8712333SN/A 8721060SN/A // If we issued any instructions, tell the CPU we had activity. 8732326SN/A // @todo If the way deferred memory instructions are handeled due to 8742326SN/A // translation changes then the deferredMemInsts condition should be removed 8752326SN/A // from the code below. 8762326SN/A if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) { 8772292SN/A cpu->activityThisCycle(); 87810807Snilay@cs.wisc.edu } else { 8792326SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 88010511Smitch.hayenga@arm.com } 8812326SN/A} 8822326SN/A 8831060SN/Atemplate <class Impl> 8849180Sandreas.hansson@arm.comvoid 8859180Sandreas.hansson@arm.comInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 8861060SN/A{ 88710807Snilay@cs.wisc.edu DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 8882348SN/A "to execute.\n", inst); 8892348SN/A 8902326SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 8912292SN/A 8922292SN/A assert(inst_it != nonSpecInsts.end()); 8932326SN/A 8942292SN/A ThreadID tid = (*inst_it).second->threadNumber; 8951060SN/A 8961060SN/A (*inst_it).second->setAtCommit(); 8977720Sgblack@eecs.umich.edu 8982292SN/A (*inst_it).second->setCanIssue(); 8997720Sgblack@eecs.umich.edu 9002292SN/A if (!(*inst_it).second->isMemRef()) { 9011060SN/A addIfReady((*inst_it).second); 9022292SN/A } else { 9031061SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9042292SN/A } 9052292SN/A 9062292SN/A (*inst_it).second = NULL; 9072292SN/A 9082292SN/A nonSpecInsts.erase(inst_it); 9091060SN/A} 9101060SN/A 9112064SN/Atemplate <class Impl> 9122292SN/Avoid 9132064SN/AInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9148471SGiacomo.Gabrielli@arm.com{ 9159046SAli.Saidi@ARM.com DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9168471SGiacomo.Gabrielli@arm.com tid,inst); 9178471SGiacomo.Gabrielli@arm.com 9182292SN/A ListIt iq_it = instList[tid].begin(); 9192292SN/A 9202292SN/A while (iq_it != instList[tid].end() && 9212292SN/A (*iq_it)->seqNum <= inst) { 9222301SN/A ++iq_it; 9232731Sktlim@umich.edu instList[tid].pop_front(); 9242292SN/A } 9252301SN/A 9262292SN/A assert(freeEntries == (numEntries - countInsts())); 9272292SN/A} 9282292SN/A 9292326SN/Atemplate <class Impl> 9302292SN/Aint 9312326SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 9322326SN/A{ 9332292SN/A int dependents = 0; 9341060SN/A 9351060SN/A // The instruction queue here takes care of both floating and int ops 9361062SN/A if (completed_inst->isFloating()) { 9372326SN/A fpInstQueueWakeupQccesses++; 9382326SN/A } else { 9392307SN/A intInstQueueWakeupAccesses++; 9402348SN/A } 9418071SAli.Saidi@ARM.com 9428071SAli.Saidi@ARM.com DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 9438071SAli.Saidi@ARM.com 94410333Smitch.hayenga@arm.com assert(!completed_inst->isSquashed()); 9452292SN/A 9462292SN/A // Tell the memory dependence unit to wake any dependents on this 9472292SN/A // instruction if it is a memory instruction. Also complete the memory 9482292SN/A // instruction at this point since we know it executed without issues. 9491060SN/A // @todo: Might want to rename "completeMemInst" to something that 9501060SN/A // indicates that it won't need to be replayed, and call this 9511061SN/A // earlier. Might not be a big deal. 9521060SN/A if (completed_inst->isMemRef()) { 9531061SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 9541060SN/A completeMemInst(completed_inst); 9552292SN/A } else if (completed_inst->isMemBarrier() || 9562292SN/A completed_inst->isWriteBarrier()) { 9571062SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 9582292SN/A } 9591060SN/A 9601061SN/A for (int dest_reg_idx = 0; 9611060SN/A dest_reg_idx < completed_inst->numDestRegs(); 9626221Snate@binkert.org dest_reg_idx++) 9632292SN/A { 9644033Sktlim@umich.edu PhysRegIndex dest_reg = 9654033Sktlim@umich.edu completed_inst->renamedDestRegIdx(dest_reg_idx); 9661061SN/A 9671060SN/A // Special case of uniq or control registers. They are not 9681062SN/A // handled by the IQ and thus have no dependency graph entry. 9691062SN/A // @todo Figure out a cleaner way to handle this. 9701062SN/A if (dest_reg >= numPhysRegs) { 9712292SN/A DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 9721062SN/A numPhysRegs); 9731060SN/A continue; 9742292SN/A } 9752292SN/A 9761061SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 9771060SN/A (int) dest_reg); 9781060SN/A 9791061SN/A //Go through the dependency chain, marking the registers as 9801061SN/A //ready within the waiting instructions. 9816221Snate@binkert.org DynInstPtr dep_inst = dependGraph.pop(dest_reg); 9822292SN/A 9832292SN/A while (dep_inst) { 9842292SN/A DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 9852292SN/A "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 9862292SN/A 9872292SN/A // Might want to give more information to the instruction 9882292SN/A // so that it knows which of its source registers is 9892292SN/A // ready. However that would mean that the dependency 9902292SN/A // graph entries would need to hold the src_reg_idx. 9912292SN/A dep_inst->markSrcRegReady(); 9922292SN/A 9932292SN/A addIfReady(dep_inst); 9942292SN/A 9952292SN/A dep_inst = dependGraph.pop(dest_reg); 9962292SN/A 9972292SN/A ++dependents; 9982301SN/A } 99913429Srekai.gonzalezalberquilla@arm.com 10001684SN/A // Reset the head node now that all of its dependents have 10012301SN/A // been woken up. 10022301SN/A assert(dependGraph.empty(dest_reg)); 10037897Shestness@cs.utexas.edu dependGraph.clearInst(dest_reg); 10047897Shestness@cs.utexas.edu 100512110SRekai.GonzalezAlberquilla@arm.com // Mark the scoreboard as having that register ready. 100612110SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg] = true; 100712110SRekai.GonzalezAlberquilla@arm.com } 10087897Shestness@cs.utexas.edu return dependents; 10097897Shestness@cs.utexas.edu} 10107897Shestness@cs.utexas.edu 10117897Shestness@cs.utexas.edutemplate <class Impl> 10122292SN/Avoid 10132292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 10142292SN/A{ 10151684SN/A OpClass op_class = ready_inst->opClass(); 10161684SN/A 10172292SN/A readyInsts[op_class].push(ready_inst); 10182326SN/A 10192326SN/A // Will need to reorder the list if either a queue is not on the list, 10202326SN/A // or it has an older instruction than last time. 10212326SN/A if (!queueOnList[op_class]) { 10221684SN/A addToOrderList(op_class); 10232292SN/A } else if (readyInsts[op_class].top()->seqNum < 10242292SN/A (*readyIt[op_class]).oldestInst) { 10252292SN/A listOrder.erase(readyIt[op_class]); 10262292SN/A addToOrderList(op_class); 10272292SN/A } 10281684SN/A 10291684SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10301684SN/A "the ready list, PC %s opclass:%i [sn:%lli].\n", 10311684SN/A ready_inst->pcState(), op_class, ready_inst->seqNum); 10321684SN/A} 10331684SN/A 103412105Snathanael.premillieu@arm.comtemplate <class Impl> 10351684SN/Avoid 10361684SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 10371684SN/A{ 10381684SN/A DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 103912105Snathanael.premillieu@arm.com 104012105Snathanael.premillieu@arm.com // Reset DTB translation state 104112106SRekai.GonzalezAlberquilla@arm.com resched_inst->translationStarted(false); 10421684SN/A resched_inst->translationCompleted(false); 10431684SN/A 10441684SN/A resched_inst->clearCanIssue(); 104512105Snathanael.premillieu@arm.com memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 104612106SRekai.GonzalezAlberquilla@arm.com} 104712106SRekai.GonzalezAlberquilla@arm.com 10481684SN/Atemplate <class Impl> 10492326SN/Avoid 10502326SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 105112106SRekai.GonzalezAlberquilla@arm.com{ 10521684SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 10532326SN/A} 10547599Sminkyu.jeong@arm.com 10557720Sgblack@eecs.umich.edutemplate <class Impl> 10561684SN/Avoid 10571684SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 10582326SN/A{ 10592326SN/A ThreadID tid = completed_inst->threadNumber; 10602326SN/A 10612326SN/A DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 10621684SN/A completed_inst->pcState(), completed_inst->seqNum); 10632326SN/A 10641684SN/A ++freeEntries; 106512106SRekai.GonzalezAlberquilla@arm.com 10661684SN/A completed_inst->memOpDone(true); 10672301SN/A 10681684SN/A memDepUnit[tid].completed(completed_inst); 10691684SN/A count[tid]--; 10702326SN/A} 10712326SN/A 107212106SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 107312106SRekai.GonzalezAlberquilla@arm.comvoid 10741684SN/AInstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 10751684SN/A{ 107612106SRekai.GonzalezAlberquilla@arm.com deferredMemInsts.push_back(deferred_inst); 10771684SN/A} 10782301SN/A 10792064SN/Atemplate <class Impl> 10802064SN/Atypename Impl::DynInstPtr 10812064SN/AInstructionQueue<Impl>::getDeferredMemInstToExecute() 10822064SN/A{ 108313429Srekai.gonzalezalberquilla@arm.com for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 10842064SN/A ++it) { 10852292SN/A if ((*it)->translationCompleted() || (*it)->isSquashed()) { 10862292SN/A DynInstPtr ret = *it; 10872292SN/A deferredMemInsts.erase(it); 10882292SN/A return ret; 10892326SN/A } 10902326SN/A } 10912326SN/A return NULL; 10922326SN/A} 10932326SN/A 10942326SN/Atemplate <class Impl> 10952326SN/Avoid 10962326SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 10972326SN/A DynInstPtr &faulting_load) 10982326SN/A{ 10992292SN/A intInstQueueWrites++; 11007720Sgblack@eecs.umich.edu memDepUnit[store->threadNumber].violation(store, faulting_load); 11017720Sgblack@eecs.umich.edu} 11022064SN/A 11032064SN/Atemplate <class Impl> 11042064SN/Avoid 11052064SN/AInstructionQueue<Impl>::squash(ThreadID tid) 110613429Srekai.gonzalezalberquilla@arm.com{ 11072064SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 11084033Sktlim@umich.edu "the IQ.\n", tid); 11097944SGiacomo.Gabrielli@arm.com 11107944SGiacomo.Gabrielli@arm.com // Read instruction sequence number of last instruction out of the 11119046SAli.Saidi@ARM.com // time buffer. 11129046SAli.Saidi@ARM.com squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 11137944SGiacomo.Gabrielli@arm.com 11144033Sktlim@umich.edu // Call doSquash if there are insts in the IQ 11152292SN/A if (count[tid] > 0) { 11162064SN/A doSquash(tid); 11172064SN/A } 11182064SN/A 11192064SN/A // Also tell the memory dependence unit to squash. 112013429Srekai.gonzalezalberquilla@arm.com memDepUnit[tid].squash(squashedSeqNum[tid], tid); 11212064SN/A} 112210333Smitch.hayenga@arm.com 11232292SN/Atemplate <class Impl> 11242292SN/Avoid 11252292SN/AInstructionQueue<Impl>::doSquash(ThreadID tid) 11262292SN/A{ 112713429Srekai.gonzalezalberquilla@arm.com // Start at the tail. 11282292SN/A ListIt squash_it = instList[tid].end(); 11296221Snate@binkert.org --squash_it; 11302292SN/A 11317720Sgblack@eecs.umich.edu DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 11327720Sgblack@eecs.umich.edu tid, squashedSeqNum[tid]); 11332292SN/A 11342292SN/A // Squash any instructions younger than the squashed sequence number 11352292SN/A // given. 11369046SAli.Saidi@ARM.com while (squash_it != instList[tid].end() && 11372292SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 11382292SN/A 11392292SN/A DynInstPtr squashed_inst = (*squash_it); 11401684SN/A squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 11411684SN/A 11421684SN/A // Only handle the instruction if it actually is in the IQ and 11431684SN/A // hasn't already been squashed in the IQ. 114413429Srekai.gonzalezalberquilla@arm.com if (squashed_inst->threadNumber != tid || 11457944SGiacomo.Gabrielli@arm.com squashed_inst->isSquashedInIQ()) { 11467944SGiacomo.Gabrielli@arm.com --squash_it; 11477944SGiacomo.Gabrielli@arm.com continue; 11487944SGiacomo.Gabrielli@arm.com } 11497944SGiacomo.Gabrielli@arm.com 115010333Smitch.hayenga@arm.com if (!squashed_inst->isIssued() || 115113429Srekai.gonzalezalberquilla@arm.com (squashed_inst->isMemRef() && 115210333Smitch.hayenga@arm.com !squashed_inst->memOpDone())) { 115310333Smitch.hayenga@arm.com 115410333Smitch.hayenga@arm.com DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 115510333Smitch.hayenga@arm.com tid, squashed_inst->seqNum, squashed_inst->pcState()); 115610333Smitch.hayenga@arm.com 115710333Smitch.hayenga@arm.com // Remove the instruction from the dependency list. 115810333Smitch.hayenga@arm.com if (!squashed_inst->isNonSpeculative() && 115910333Smitch.hayenga@arm.com !squashed_inst->isStoreConditional() && 116010333Smitch.hayenga@arm.com !squashed_inst->isMemBarrier() && 116110333Smitch.hayenga@arm.com !squashed_inst->isWriteBarrier()) { 116210333Smitch.hayenga@arm.com 116310333Smitch.hayenga@arm.com for (int src_reg_idx = 0; 116410333Smitch.hayenga@arm.com src_reg_idx < squashed_inst->numSrcRegs(); 116510333Smitch.hayenga@arm.com src_reg_idx++) 116610333Smitch.hayenga@arm.com { 116710333Smitch.hayenga@arm.com PhysRegIndex src_reg = 116810333Smitch.hayenga@arm.com squashed_inst->renamedSrcRegIdx(src_reg_idx); 116910333Smitch.hayenga@arm.com 117010333Smitch.hayenga@arm.com // Only remove it from the dependency graph if it 11717944SGiacomo.Gabrielli@arm.com // was placed there in the first place. 11727944SGiacomo.Gabrielli@arm.com 11737944SGiacomo.Gabrielli@arm.com // Instead of doing a linked list traversal, we 11747944SGiacomo.Gabrielli@arm.com // can just remove these squashed instructions 11757944SGiacomo.Gabrielli@arm.com // either at issue time, or when the register is 11769046SAli.Saidi@ARM.com // overwritten. The only downside to this is it 117713429Srekai.gonzalezalberquilla@arm.com // leaves more room for error. 11787944SGiacomo.Gabrielli@arm.com 117910333Smitch.hayenga@arm.com if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 11807944SGiacomo.Gabrielli@arm.com src_reg < numPhysRegs) { 11817944SGiacomo.Gabrielli@arm.com dependGraph.remove(src_reg, squashed_inst); 118210333Smitch.hayenga@arm.com } 118310333Smitch.hayenga@arm.com 118410333Smitch.hayenga@arm.com 118510333Smitch.hayenga@arm.com ++iqSquashedOperandsExamined; 118610333Smitch.hayenga@arm.com } 118710333Smitch.hayenga@arm.com } else if (!squashed_inst->isStoreConditional() || 118810333Smitch.hayenga@arm.com !squashed_inst->isCompleted()) { 118910333Smitch.hayenga@arm.com NonSpecMapIt ns_inst_it = 119010333Smitch.hayenga@arm.com nonSpecInsts.find(squashed_inst->seqNum); 119110333Smitch.hayenga@arm.com 119213429Srekai.gonzalezalberquilla@arm.com if (ns_inst_it == nonSpecInsts.end()) { 119310333Smitch.hayenga@arm.com assert(squashed_inst->getFault() != NoFault); 119410333Smitch.hayenga@arm.com } else { 119510333Smitch.hayenga@arm.com 11967944SGiacomo.Gabrielli@arm.com (*ns_inst_it).second = NULL; 11977944SGiacomo.Gabrielli@arm.com 11987944SGiacomo.Gabrielli@arm.com nonSpecInsts.erase(ns_inst_it); 11997944SGiacomo.Gabrielli@arm.com 120013429Srekai.gonzalezalberquilla@arm.com ++iqSquashedNonSpecRemoved; 120113429Srekai.gonzalezalberquilla@arm.com } 12021061SN/A } 12037897Shestness@cs.utexas.edu 12042292SN/A // Might want to also clear out the head of the dependency graph. 12051061SN/A 12061061SN/A // Mark it as squashed within the IQ. 12071061SN/A squashed_inst->setSquashedInIQ(); 12081060SN/A 12096221Snate@binkert.org // @todo: Remove this hack where several statuses are set so the 12101060SN/A // inst will flow through the rest of the pipeline. 12112292SN/A squashed_inst->setIssued(); 12122292SN/A squashed_inst->setCanCommit(); 12131060SN/A squashed_inst->clearInIQ(); 12141060SN/A 12151060SN/A //Update Thread IQ Count 12162292SN/A count[squashed_inst->threadNumber]--; 12171060SN/A 121810797Sbrandon.potter@amd.com ++freeEntries; 12191061SN/A } 12201061SN/A 12212292SN/A instList[tid].erase(squash_it--); 12221060SN/A ++iqSquashedInstsExamined; 12231060SN/A } 12241061SN/A} 12251061SN/A 12266221Snate@binkert.orgtemplate <class Impl> 12271061SN/Abool 12282326SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 12292326SN/A{ 12302326SN/A // Loop through the instruction's source registers, adding 12311061SN/A // them to the dependency list if they are not ready. 12322292SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 12332292SN/A bool return_val = false; 12341061SN/A 12351061SN/A for (int src_reg_idx = 0; 12361061SN/A src_reg_idx < total_src_regs; 12372326SN/A src_reg_idx++) 12382326SN/A { 12392292SN/A // Only add it to the dependency graph if it's not ready. 12402326SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 124112110SRekai.GonzalezAlberquilla@arm.com PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 124212110SRekai.GonzalezAlberquilla@arm.com 124312110SRekai.GonzalezAlberquilla@arm.com // Check the IQ's scoreboard to make sure the register 124412110SRekai.GonzalezAlberquilla@arm.com // hasn't become ready while the instruction was in flight 124512110SRekai.GonzalezAlberquilla@arm.com // between stages. Only if it really isn't ready should 124612110SRekai.GonzalezAlberquilla@arm.com // it be added to the dependency graph. 124712110SRekai.GonzalezAlberquilla@arm.com if (src_reg >= numPhysRegs) { 12481061SN/A continue; 12491061SN/A } else if (regScoreboard[src_reg] == false) { 12501061SN/A DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12512292SN/A "is being added to the dependency chain.\n", 12522292SN/A new_inst->pcState(), src_reg); 12532326SN/A 12542292SN/A dependGraph.insert(src_reg, new_inst); 12552292SN/A 12562292SN/A // Change the return value to indicate that something 12572292SN/A // was added to the dependency graph. 12582292SN/A return_val = true; 12599046SAli.Saidi@ARM.com } else { 12601062SN/A DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12617720Sgblack@eecs.umich.edu "became ready before it reached the IQ.\n", 12627720Sgblack@eecs.umich.edu new_inst->pcState(), src_reg); 12632367SN/A // Mark a register ready within the instruction. 126410032SGiacomo.Gabrielli@arm.com new_inst->markSrcRegReady(src_reg_idx); 126510032SGiacomo.Gabrielli@arm.com } 126610032SGiacomo.Gabrielli@arm.com } 126710032SGiacomo.Gabrielli@arm.com } 126810032SGiacomo.Gabrielli@arm.com 12691061SN/A return return_val; 127010032SGiacomo.Gabrielli@arm.com} 127110032SGiacomo.Gabrielli@arm.com 127210032SGiacomo.Gabrielli@arm.comtemplate <class Impl> 127310032SGiacomo.Gabrielli@arm.comvoid 127410032SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 12751061SN/A{ 12761061SN/A // Nothing really needs to be marked when an instruction becomes 12771681SN/A // the producer of a register's value, but for convenience a ptr 12781061SN/A // to the producing instruction will be placed in the head node of 12791061SN/A // the dependency links. 128012105Snathanael.premillieu@arm.com int8_t total_dest_regs = new_inst->numDestRegs(); 12811061SN/A 12821061SN/A for (int dest_reg_idx = 0; 12832326SN/A dest_reg_idx < total_dest_regs; 12842326SN/A dest_reg_idx++) 12852326SN/A { 12862326SN/A PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 12872326SN/A 12882326SN/A // Instructions that use the misc regs will have a reg number 12892326SN/A // higher than the normal physical registers. In this case these 12902326SN/A // registers are not renamed, and there is no need to track 12912292SN/A // dependencies as these instructions must be executed at commit. 12921061SN/A if (dest_reg >= numPhysRegs) { 129312105Snathanael.premillieu@arm.com continue; 129412106SRekai.GonzalezAlberquilla@arm.com } 129512106SRekai.GonzalezAlberquilla@arm.com 12961061SN/A if (!dependGraph.empty(dest_reg)) { 12971062SN/A dependGraph.dump(); 12982292SN/A panic("Dependency graph %i not empty!", dest_reg); 12991062SN/A } 13001061SN/A 13014033Sktlim@umich.edu dependGraph.setInst(dest_reg, new_inst); 13024033Sktlim@umich.edu 13032292SN/A // Mark the scoreboard to say it's not yet ready. 13042292SN/A regScoreboard[dest_reg] = false; 13058275SAli.Saidi@ARM.com } 130610017Sandreas.hansson@arm.com} 130710017Sandreas.hansson@arm.com 130810017Sandreas.hansson@arm.comtemplate <class Impl> 13094033Sktlim@umich.eduvoid 131010017Sandreas.hansson@arm.comInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 131110017Sandreas.hansson@arm.com{ 131210017Sandreas.hansson@arm.com // If the instruction now has all of its source registers 131310017Sandreas.hansson@arm.com // available, then add it to the list of ready instructions. 131410017Sandreas.hansson@arm.com if (inst->readyToIssue()) { 13154033Sktlim@umich.edu 13161062SN/A //Add the instruction to the proper ready list. 13174033Sktlim@umich.edu if (inst->isMemRef()) { 13181681SN/A 13194033Sktlim@umich.edu DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 13201062SN/A 13214033Sktlim@umich.edu // Message to the mem dependence unit that this instruction has 13224033Sktlim@umich.edu // its registers ready. 13231061SN/A memDepUnit[inst->threadNumber].regsReady(inst); 13241061SN/A 13251061SN/A return; 13261061SN/A } 13271061SN/A 13281061SN/A OpClass op_class = inst->opClass(); 13291061SN/A 13302292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 13312292SN/A "the ready list, PC %s opclass:%i [sn:%lli].\n", 13321681SN/A inst->pcState(), op_class, inst->seqNum); 13331681SN/A 13342731Sktlim@umich.edu readyInsts[op_class].push(inst); 13352292SN/A 13362292SN/A // Will need to reorder the list if either a queue is not on the list, 13372292SN/A // or it has an older instruction than last time. 13381681SN/A if (!queueOnList[op_class]) { 13391681SN/A addToOrderList(op_class); 13401061SN/A } else if (readyInsts[op_class].top()->seqNum < 13411061SN/A (*readyIt[op_class]).oldestInst) { 134212833Sjang.hanhwi@gmail.com listOrder.erase(readyIt[op_class]); 134312833Sjang.hanhwi@gmail.com addToOrderList(op_class); 134412833Sjang.hanhwi@gmail.com } 134512833Sjang.hanhwi@gmail.com } 134612833Sjang.hanhwi@gmail.com} 134712833Sjang.hanhwi@gmail.com 134812833Sjang.hanhwi@gmail.comtemplate <class Impl> 134912833Sjang.hanhwi@gmail.comint 135012833Sjang.hanhwi@gmail.comInstructionQueue<Impl>::countInsts() 135112833Sjang.hanhwi@gmail.com{ 135212833Sjang.hanhwi@gmail.com#if 0 135312833Sjang.hanhwi@gmail.com //ksewell:This works but definitely could use a cleaner write 135412833Sjang.hanhwi@gmail.com //with a more intuitive way of counting. Right now it's 135512833Sjang.hanhwi@gmail.com //just brute force .... 135612833Sjang.hanhwi@gmail.com // Change the #if if you want to use this method. 135712833Sjang.hanhwi@gmail.com int total_insts = 0; 135812833Sjang.hanhwi@gmail.com 135912833Sjang.hanhwi@gmail.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 136012833Sjang.hanhwi@gmail.com ListIt count_it = instList[tid].begin(); 13612326SN/A 13621062SN/A while (count_it != instList[tid].end()) { 13631061SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 13641060SN/A if (!(*count_it)->isIssued()) { 13651060SN/A ++total_insts; 13661061SN/A } else if ((*count_it)->isMemRef() && 13671060SN/A !(*count_it)->memOpDone) { 136813429Srekai.gonzalezalberquilla@arm.com // Loads that have not been marked as executed still count 13691060SN/A // towards the total instructions. 13701060SN/A ++total_insts; 13711060SN/A } 13721060SN/A } 13731060SN/A 13741060SN/A ++count_it; 13751060SN/A } 13761060SN/A } 13771060SN/A 13781060SN/A return total_insts; 13791060SN/A#else 13801060SN/A return numEntries - freeEntries; 138112105Snathanael.premillieu@arm.com#endif 13821060SN/A} 13831060SN/A 13841060SN/Atemplate <class Impl> 13851060SN/Avoid 13861060SN/AInstructionQueue<Impl>::dumpLists() 138712105Snathanael.premillieu@arm.com{ 13881061SN/A for (int i = 0; i < Num_OpClasses; ++i) { 138912106SRekai.GonzalezAlberquilla@arm.com cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 139012105Snathanael.premillieu@arm.com 13911060SN/A cprintf("\n"); 139212106SRekai.GonzalezAlberquilla@arm.com } 139312106SRekai.GonzalezAlberquilla@arm.com 13941060SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 139512106SRekai.GonzalezAlberquilla@arm.com 13961060SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 13971060SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 13981060SN/A 13991060SN/A cprintf("Non speculative list: "); 14001060SN/A 140112105Snathanael.premillieu@arm.com while (non_spec_it != non_spec_end_it) { 14021060SN/A cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 140312106SRekai.GonzalezAlberquilla@arm.com (*non_spec_it).second->seqNum); 140412106SRekai.GonzalezAlberquilla@arm.com ++non_spec_it; 14051060SN/A } 14062326SN/A 14071060SN/A cprintf("\n"); 14081060SN/A 14091060SN/A ListOrderIt list_order_it = listOrder.begin(); 14101060SN/A ListOrderIt list_order_end_it = listOrder.end(); 14111060SN/A int i = 1; 14121060SN/A 14131060SN/A cprintf("List order: "); 14141061SN/A 14151060SN/A while (list_order_it != list_order_end_it) { 141613429Srekai.gonzalezalberquilla@arm.com cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 14171060SN/A (*list_order_it).oldestInst); 14182326SN/A 14192326SN/A ++list_order_it; 14202326SN/A ++i; 14212326SN/A } 14221060SN/A 14231060SN/A cprintf("\n"); 14241060SN/A} 14251060SN/A 14261060SN/A 14271060SN/Atemplate <class Impl> 142812105Snathanael.premillieu@arm.comvoid 14291061SN/AInstructionQueue<Impl>::dumpInsts() 143012105Snathanael.premillieu@arm.com{ 14311061SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 143212105Snathanael.premillieu@arm.com int num = 0; 14331061SN/A int valid_num = 0; 14341060SN/A ListIt inst_list_it = instList[tid].begin(); 14351060SN/A 143612106SRekai.GonzalezAlberquilla@arm.com while (inst_list_it != instList[tid].end()) { 14372326SN/A cprintf("Instruction:%i\n", num); 143812105Snathanael.premillieu@arm.com if (!(*inst_list_it)->isSquashed()) { 143912106SRekai.GonzalezAlberquilla@arm.com if (!(*inst_list_it)->isIssued()) { 144012106SRekai.GonzalezAlberquilla@arm.com ++valid_num; 14412064SN/A cprintf("Count:%i\n", valid_num); 14421062SN/A } else if ((*inst_list_it)->isMemRef() && 144312106SRekai.GonzalezAlberquilla@arm.com !(*inst_list_it)->memOpDone()) { 14441062SN/A // Loads that have not been marked as executed 14451060SN/A // still count towards the total instructions. 144612106SRekai.GonzalezAlberquilla@arm.com ++valid_num; 14471060SN/A cprintf("Count:%i\n", valid_num); 14481060SN/A } 14491060SN/A } 14501061SN/A 14511060SN/A cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 145213429Srekai.gonzalezalberquilla@arm.com "Issued:%i\nSquashed:%i\n", 14531060SN/A (*inst_list_it)->pcState(), 14542326SN/A (*inst_list_it)->seqNum, 14551060SN/A (*inst_list_it)->threadNumber, 14561060SN/A (*inst_list_it)->isIssued(), 14571061SN/A (*inst_list_it)->isSquashed()); 14581060SN/A 14592292SN/A if ((*inst_list_it)->isMemRef()) { 14601061SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 14612292SN/A } 14621061SN/A 14631062SN/A cprintf("\n"); 14641062SN/A 14652292SN/A inst_list_it++; 14661062SN/A ++num; 14672292SN/A } 14682292SN/A } 14691062SN/A 14702292SN/A cprintf("Insts to Execute list:\n"); 14711061SN/A 14722292SN/A int num = 0; 14737720Sgblack@eecs.umich.edu int valid_num = 0; 14747720Sgblack@eecs.umich.edu ListIt inst_list_it = instsToExecute.begin(); 14751061SN/A 14762292SN/A while (inst_list_it != instsToExecute.end()) 14771061SN/A { 14782326SN/A cprintf("Instruction:%i\n", 14792326SN/A num); 14802326SN/A if (!(*inst_list_it)->isSquashed()) { 14812326SN/A if (!(*inst_list_it)->isIssued()) { 14822326SN/A ++valid_num; 14832326SN/A cprintf("Count:%i\n", valid_num); 14842326SN/A } else if ((*inst_list_it)->isMemRef() && 14852326SN/A !(*inst_list_it)->memOpDone()) { 14861060SN/A // Loads that have not been marked as executed 14871060SN/A // still count towards the total instructions. 14881060SN/A ++valid_num; 14891060SN/A cprintf("Count:%i\n", valid_num); 14901061SN/A } 14911061SN/A } 14921061SN/A 14931061SN/A cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 14942698Sktlim@umich.edu "Issued:%i\nSquashed:%i\n", 14952292SN/A (*inst_list_it)->pcState(), 14962292SN/A (*inst_list_it)->seqNum, 14972292SN/A (*inst_list_it)->threadNumber, 14982698Sktlim@umich.edu (*inst_list_it)->isIssued(), 14991061SN/A (*inst_list_it)->isSquashed()); 15001061SN/A 15016221Snate@binkert.org if ((*inst_list_it)->isMemRef()) { 15026221Snate@binkert.org cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 15031681SN/A } 15046221Snate@binkert.org 15052292SN/A cprintf("\n"); 15062292SN/A 15072292SN/A inst_list_it++; 15082292SN/A ++num; 15092292SN/A } 15102292SN/A} 15112292SN/A