inst_queue_impl.hh revision 9444
13536Sgblack@eecs.umich.edu/* 23536Sgblack@eecs.umich.edu * Copyright (c) 2011-2012 ARM Limited 33536Sgblack@eecs.umich.edu * All rights reserved. 43536Sgblack@eecs.umich.edu * 53536Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 63536Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 73536Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 83536Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 93536Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 103536Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 113536Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 123536Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 133536Sgblack@eecs.umich.edu * 143536Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 153536Sgblack@eecs.umich.edu * All rights reserved. 163536Sgblack@eecs.umich.edu * 173536Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 183536Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 193536Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 203536Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 213536Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 223536Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 233536Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 243536Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 253536Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 263536Sgblack@eecs.umich.edu * this software without specific prior written permission. 273536Sgblack@eecs.umich.edu * 283536Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293536Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303536Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313536Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323536Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 335543Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343536Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353536Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363536Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373536Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383536Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393536Sgblack@eecs.umich.edu * 403536Sgblack@eecs.umich.edu * Authors: Kevin Lim 415543Ssaidi@eecs.umich.edu * Korey Sewell 425543Ssaidi@eecs.umich.edu */ 433536Sgblack@eecs.umich.edu 443536Sgblack@eecs.umich.edu#include <limits> 453536Sgblack@eecs.umich.edu#include <vector> 463536Sgblack@eecs.umich.edu 473536Sgblack@eecs.umich.edu#include "cpu/o3/fu_pool.hh" 483536Sgblack@eecs.umich.edu#include "cpu/o3/inst_queue.hh" 493536Sgblack@eecs.umich.edu#include "debug/IQ.hh" 503536Sgblack@eecs.umich.edu#include "enums/OpClass.hh" 513536Sgblack@eecs.umich.edu#include "params/DerivO3CPU.hh" 523536Sgblack@eecs.umich.edu#include "sim/core.hh" 533536Sgblack@eecs.umich.edu 545543Ssaidi@eecs.umich.edu// clang complains about std::set being overloaded with Packet::set if 555543Ssaidi@eecs.umich.edu// we open up the entire namespace std 563536Sgblack@eecs.umich.eduusing std::list; 573536Sgblack@eecs.umich.edu 583536Sgblack@eecs.umich.edutemplate <class Impl> 593536Sgblack@eecs.umich.eduInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 603536Sgblack@eecs.umich.edu int fu_idx, InstructionQueue<Impl> *iq_ptr) 613536Sgblack@eecs.umich.edu : Event(Stat_Event_Pri, AutoDelete), 623536Sgblack@eecs.umich.edu inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 633536Sgblack@eecs.umich.edu{ 643536Sgblack@eecs.umich.edu} 653536Sgblack@eecs.umich.edu 663536Sgblack@eecs.umich.edutemplate <class Impl> 673536Sgblack@eecs.umich.eduvoid 683536Sgblack@eecs.umich.eduInstructionQueue<Impl>::FUCompletion::process() 693536Sgblack@eecs.umich.edu{ 703536Sgblack@eecs.umich.edu iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 713536Sgblack@eecs.umich.edu inst = NULL; 725543Ssaidi@eecs.umich.edu} 733536Sgblack@eecs.umich.edu 743536Sgblack@eecs.umich.edu 753536Sgblack@eecs.umich.edutemplate <class Impl> 763536Sgblack@eecs.umich.educonst char * 773536Sgblack@eecs.umich.eduInstructionQueue<Impl>::FUCompletion::description() const 783536Sgblack@eecs.umich.edu{ 793536Sgblack@eecs.umich.edu return "Functional unit completion"; 803536Sgblack@eecs.umich.edu} 813536Sgblack@eecs.umich.edu 823536Sgblack@eecs.umich.edutemplate <class Impl> 833536Sgblack@eecs.umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 843536Sgblack@eecs.umich.edu DerivO3CPUParams *params) 853536Sgblack@eecs.umich.edu : cpu(cpu_ptr), 863536Sgblack@eecs.umich.edu iewStage(iew_ptr), 873536Sgblack@eecs.umich.edu fuPool(params->fuPool), 883536Sgblack@eecs.umich.edu numEntries(params->numIQEntries), 893536Sgblack@eecs.umich.edu totalWidth(params->issueWidth), 903536Sgblack@eecs.umich.edu numPhysIntRegs(params->numPhysIntRegs), 913536Sgblack@eecs.umich.edu numPhysFloatRegs(params->numPhysFloatRegs), 925543Ssaidi@eecs.umich.edu commitToIEWDelay(params->commitToIEWDelay) 935543Ssaidi@eecs.umich.edu{ 943536Sgblack@eecs.umich.edu assert(fuPool); 953536Sgblack@eecs.umich.edu 963536Sgblack@eecs.umich.edu numThreads = params->numThreads; 973536Sgblack@eecs.umich.edu 983536Sgblack@eecs.umich.edu // Set the number of physical registers as the number of int + float 993536Sgblack@eecs.umich.edu numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 1003536Sgblack@eecs.umich.edu 1013536Sgblack@eecs.umich.edu //Create an entry for each physical register within the 1023536Sgblack@eecs.umich.edu //dependency graph. 1033536Sgblack@eecs.umich.edu dependGraph.resize(numPhysRegs); 1043536Sgblack@eecs.umich.edu 1053536Sgblack@eecs.umich.edu // Resize the register scoreboard. 1063536Sgblack@eecs.umich.edu regScoreboard.resize(numPhysRegs); 1073536Sgblack@eecs.umich.edu 1083536Sgblack@eecs.umich.edu //Initialize Mem Dependence Units 1093536Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 1103536Sgblack@eecs.umich.edu memDepUnit[tid].init(params, tid); 1113536Sgblack@eecs.umich.edu memDepUnit[tid].setIQ(this); 1123536Sgblack@eecs.umich.edu } 1133536Sgblack@eecs.umich.edu 1143536Sgblack@eecs.umich.edu resetState(); 1153536Sgblack@eecs.umich.edu 1163536Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1173536Sgblack@eecs.umich.edu 1183536Sgblack@eecs.umich.edu //Convert string to lowercase 1193536Sgblack@eecs.umich.edu std::transform(policy.begin(), policy.end(), policy.begin(), 1205569Snate@binkert.org (int(*)(int)) tolower); 1213536Sgblack@eecs.umich.edu 1223536Sgblack@eecs.umich.edu //Figure out resource sharing policy 1233536Sgblack@eecs.umich.edu if (policy == "dynamic") { 1243961Sgblack@eecs.umich.edu iqPolicy = Dynamic; 1253961Sgblack@eecs.umich.edu 1263961Sgblack@eecs.umich.edu //Set Max Entries to Total ROB Capacity 1273961Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 1283961Sgblack@eecs.umich.edu maxEntries[tid] = numEntries; 1293550Sgblack@eecs.umich.edu } 1303961Sgblack@eecs.umich.edu 1316327Sgblack@eecs.umich.edu } else if (policy == "partitioned") { 1323550Sgblack@eecs.umich.edu iqPolicy = Partitioned; 1333536Sgblack@eecs.umich.edu 1343536Sgblack@eecs.umich.edu //@todo:make work if part_amt doesnt divide evenly. 1353536Sgblack@eecs.umich.edu int part_amt = numEntries / numThreads; 1363536Sgblack@eecs.umich.edu 1373536Sgblack@eecs.umich.edu //Divide ROB up evenly 1383536Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 1393536Sgblack@eecs.umich.edu maxEntries[tid] = part_amt; 1403536Sgblack@eecs.umich.edu } 1413536Sgblack@eecs.umich.edu 1423536Sgblack@eecs.umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1433536Sgblack@eecs.umich.edu "%i entries per thread.\n",part_amt); 1445567Snate@binkert.org } else if (policy == "threshold") { 1453536Sgblack@eecs.umich.edu iqPolicy = Threshold; 1465569Snate@binkert.org 1475569Snate@binkert.org double threshold = (double)params->smtIQThreshold / 100; 1483536Sgblack@eecs.umich.edu 1493579Sgblack@eecs.umich.edu int thresholdIQ = (int)((double)threshold * numEntries); 1503536Sgblack@eecs.umich.edu 1513536Sgblack@eecs.umich.edu //Divide up by threshold amount 1525569Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1535569Snate@binkert.org maxEntries[tid] = thresholdIQ; 1545569Snate@binkert.org } 1553536Sgblack@eecs.umich.edu 1563536Sgblack@eecs.umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1573536Sgblack@eecs.umich.edu "%i entries per thread.\n",thresholdIQ); 1583961Sgblack@eecs.umich.edu } else { 1593961Sgblack@eecs.umich.edu assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1603961Sgblack@eecs.umich.edu "Partitioned, Threshold}"); 1613536Sgblack@eecs.umich.edu } 1623536Sgblack@eecs.umich.edu} 1635568Snate@binkert.org 1645568Snate@binkert.orgtemplate <class Impl> 1653536Sgblack@eecs.umich.eduInstructionQueue<Impl>::~InstructionQueue() 1663536Sgblack@eecs.umich.edu{ 1675568Snate@binkert.org dependGraph.reset(); 1685568Snate@binkert.org#ifdef DEBUG 1693536Sgblack@eecs.umich.edu cprintf("Nodes traversed: %i, removed: %i\n", 1703536Sgblack@eecs.umich.edu dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1713536Sgblack@eecs.umich.edu#endif 1723536Sgblack@eecs.umich.edu} 1733536Sgblack@eecs.umich.edu 1743536Sgblack@eecs.umich.edutemplate <class Impl> 1753536Sgblack@eecs.umich.edustd::string 1763536Sgblack@eecs.umich.eduInstructionQueue<Impl>::name() const 1773536Sgblack@eecs.umich.edu{ 1783536Sgblack@eecs.umich.edu return cpu->name() + ".iq"; 1795569Snate@binkert.org} 1805569Snate@binkert.org 1815569Snate@binkert.orgtemplate <class Impl> 1825569Snate@binkert.orgvoid 1835569Snate@binkert.orgInstructionQueue<Impl>::regStats() 1845569Snate@binkert.org{ 1855569Snate@binkert.org using namespace Stats; 1863536Sgblack@eecs.umich.edu iqInstsAdded 1875568Snate@binkert.org .name(name() + ".iqInstsAdded") 1883536Sgblack@eecs.umich.edu .desc("Number of instructions added to the IQ (excludes non-spec)") 1893536Sgblack@eecs.umich.edu .prereq(iqInstsAdded); 1905568Snate@binkert.org 1915569Snate@binkert.org iqNonSpecInstsAdded 1925569Snate@binkert.org .name(name() + ".iqNonSpecInstsAdded") 1933536Sgblack@eecs.umich.edu .desc("Number of non-speculative instructions added to the IQ") 1943536Sgblack@eecs.umich.edu .prereq(iqNonSpecInstsAdded); 1953536Sgblack@eecs.umich.edu 1963536Sgblack@eecs.umich.edu iqInstsIssued 1975568Snate@binkert.org .name(name() + ".iqInstsIssued") 1983536Sgblack@eecs.umich.edu .desc("Number of instructions issued") 1993536Sgblack@eecs.umich.edu .prereq(iqInstsIssued); 2003536Sgblack@eecs.umich.edu 2013536Sgblack@eecs.umich.edu iqIntInstsIssued 2023961Sgblack@eecs.umich.edu .name(name() + ".iqIntInstsIssued") 2033536Sgblack@eecs.umich.edu .desc("Number of integer instructions issued") 2043536Sgblack@eecs.umich.edu .prereq(iqIntInstsIssued); 2055569Snate@binkert.org 2065569Snate@binkert.org iqFloatInstsIssued 2075569Snate@binkert.org .name(name() + ".iqFloatInstsIssued") 2085569Snate@binkert.org .desc("Number of float instructions issued") 2093536Sgblack@eecs.umich.edu .prereq(iqFloatInstsIssued); 2103536Sgblack@eecs.umich.edu 2113536Sgblack@eecs.umich.edu iqBranchInstsIssued 2123579Sgblack@eecs.umich.edu .name(name() + ".iqBranchInstsIssued") 2133536Sgblack@eecs.umich.edu .desc("Number of branch instructions issued") 2147720Sgblack@eecs.umich.edu .prereq(iqBranchInstsIssued); 2153536Sgblack@eecs.umich.edu 2163536Sgblack@eecs.umich.edu iqMemInstsIssued 2175568Snate@binkert.org .name(name() + ".iqMemInstsIssued") 2185568Snate@binkert.org .desc("Number of memory instructions issued") 2195568Snate@binkert.org .prereq(iqMemInstsIssued); 2203536Sgblack@eecs.umich.edu 2213536Sgblack@eecs.umich.edu iqMiscInstsIssued 2225568Snate@binkert.org .name(name() + ".iqMiscInstsIssued") 2233536Sgblack@eecs.umich.edu .desc("Number of miscellaneous instructions issued") 2243536Sgblack@eecs.umich.edu .prereq(iqMiscInstsIssued); 2253536Sgblack@eecs.umich.edu 2263536Sgblack@eecs.umich.edu iqSquashedInstsIssued 2273536Sgblack@eecs.umich.edu .name(name() + ".iqSquashedInstsIssued") 2285568Snate@binkert.org .desc("Number of squashed instructions issued") 2293536Sgblack@eecs.umich.edu .prereq(iqSquashedInstsIssued); 2303536Sgblack@eecs.umich.edu 2313536Sgblack@eecs.umich.edu iqSquashedInstsExamined 2323536Sgblack@eecs.umich.edu .name(name() + ".iqSquashedInstsExamined") 2333536Sgblack@eecs.umich.edu .desc("Number of squashed instructions iterated over during squash;" 2345569Snate@binkert.org " mainly for profiling") 2355569Snate@binkert.org .prereq(iqSquashedInstsExamined); 2365569Snate@binkert.org 2375569Snate@binkert.org iqSquashedOperandsExamined 2383536Sgblack@eecs.umich.edu .name(name() + ".iqSquashedOperandsExamined") 2393536Sgblack@eecs.umich.edu .desc("Number of squashed operands that are examined and possibly " 2403536Sgblack@eecs.umich.edu "removed from graph") 2413536Sgblack@eecs.umich.edu .prereq(iqSquashedOperandsExamined); 2425568Snate@binkert.org 2435568Snate@binkert.org iqSquashedNonSpecRemoved 2445568Snate@binkert.org .name(name() + ".iqSquashedNonSpecRemoved") 2453536Sgblack@eecs.umich.edu .desc("Number of squashed non-spec instructions that were removed") 2463536Sgblack@eecs.umich.edu .prereq(iqSquashedNonSpecRemoved); 2475568Snate@binkert.org/* 2483536Sgblack@eecs.umich.edu queueResDist 2493536Sgblack@eecs.umich.edu .init(Num_OpClasses, 0, 99, 2) 2503536Sgblack@eecs.umich.edu .name(name() + ".IQ:residence:") 2513536Sgblack@eecs.umich.edu .desc("cycles from dispatch to issue") 2523536Sgblack@eecs.umich.edu .flags(total | pdf | cdf ) 2535568Snate@binkert.org ; 2543536Sgblack@eecs.umich.edu for (int i = 0; i < Num_OpClasses; ++i) { 2553536Sgblack@eecs.umich.edu queueResDist.subname(i, opClassStrings[i]); 2563536Sgblack@eecs.umich.edu } 2577720Sgblack@eecs.umich.edu*/ 2583536Sgblack@eecs.umich.edu numIssuedDist 2593536Sgblack@eecs.umich.edu .init(0,totalWidth,1) 2603536Sgblack@eecs.umich.edu .name(name() + ".issued_per_cycle") 2613536Sgblack@eecs.umich.edu .desc("Number of insts issued each cycle") 2623536Sgblack@eecs.umich.edu .flags(pdf) 2633536Sgblack@eecs.umich.edu ; 2643550Sgblack@eecs.umich.edu/* 2653536Sgblack@eecs.umich.edu dist_unissued 2663550Sgblack@eecs.umich.edu .init(Num_OpClasses+2) 2673536Sgblack@eecs.umich.edu .name(name() + ".unissued_cause") 2683536Sgblack@eecs.umich.edu .desc("Reason ready instruction not issued") 2693550Sgblack@eecs.umich.edu .flags(pdf | dist) 2703536Sgblack@eecs.umich.edu ; 2713536Sgblack@eecs.umich.edu for (int i=0; i < (Num_OpClasses + 2); ++i) { 2723536Sgblack@eecs.umich.edu dist_unissued.subname(i, unissued_names[i]); 2733536Sgblack@eecs.umich.edu } 2743536Sgblack@eecs.umich.edu*/ 2753536Sgblack@eecs.umich.edu statIssuedInstType 2767720Sgblack@eecs.umich.edu .init(numThreads,Enums::Num_OpClass) 2777720Sgblack@eecs.umich.edu .name(name() + ".FU_type") 2783536Sgblack@eecs.umich.edu .desc("Type of FU issued") 2793536Sgblack@eecs.umich.edu .flags(total | pdf | dist) 2803536Sgblack@eecs.umich.edu ; 2813536Sgblack@eecs.umich.edu statIssuedInstType.ysubnames(Enums::OpClassStrings); 2827720Sgblack@eecs.umich.edu 2837720Sgblack@eecs.umich.edu // 2843536Sgblack@eecs.umich.edu // How long did instructions for a particular FU type wait prior to issue 2853536Sgblack@eecs.umich.edu // 2863536Sgblack@eecs.umich.edu/* 2877720Sgblack@eecs.umich.edu issueDelayDist 2883536Sgblack@eecs.umich.edu .init(Num_OpClasses,0,99,2) 2893536Sgblack@eecs.umich.edu .name(name() + ".") 2903536Sgblack@eecs.umich.edu .desc("cycles from operands ready to issue") 2913536Sgblack@eecs.umich.edu .flags(pdf | cdf) 2923550Sgblack@eecs.umich.edu ; 2933536Sgblack@eecs.umich.edu 2947720Sgblack@eecs.umich.edu for (int i=0; i<Num_OpClasses; ++i) { 2953536Sgblack@eecs.umich.edu std::stringstream subname; 2963536Sgblack@eecs.umich.edu subname << opClassStrings[i] << "_delay"; 2977720Sgblack@eecs.umich.edu issueDelayDist.subname(i, subname.str()); 2983536Sgblack@eecs.umich.edu } 2993536Sgblack@eecs.umich.edu*/ 3003536Sgblack@eecs.umich.edu issueRate 3013536Sgblack@eecs.umich.edu .name(name() + ".rate") 3023536Sgblack@eecs.umich.edu .desc("Inst issue rate") 3033536Sgblack@eecs.umich.edu .flags(total) 3043536Sgblack@eecs.umich.edu ; 3053536Sgblack@eecs.umich.edu issueRate = iqInstsIssued / cpu->numCycles; 3063536Sgblack@eecs.umich.edu 3073536Sgblack@eecs.umich.edu statFuBusy 3083536Sgblack@eecs.umich.edu .init(Num_OpClasses) 3093536Sgblack@eecs.umich.edu .name(name() + ".fu_full") 3103536Sgblack@eecs.umich.edu .desc("attempts to use FU when none available") 3113536Sgblack@eecs.umich.edu .flags(pdf | dist) 3123536Sgblack@eecs.umich.edu ; 3133536Sgblack@eecs.umich.edu for (int i=0; i < Num_OpClasses; ++i) { 314 statFuBusy.subname(i, Enums::OpClassStrings[i]); 315 } 316 317 fuBusy 318 .init(numThreads) 319 .name(name() + ".fu_busy_cnt") 320 .desc("FU busy when requested") 321 .flags(total) 322 ; 323 324 fuBusyRate 325 .name(name() + ".fu_busy_rate") 326 .desc("FU busy rate (busy events/executed inst)") 327 .flags(total) 328 ; 329 fuBusyRate = fuBusy / iqInstsIssued; 330 331 for (ThreadID tid = 0; tid < numThreads; tid++) { 332 // Tell mem dependence unit to reg stats as well. 333 memDepUnit[tid].regStats(); 334 } 335 336 intInstQueueReads 337 .name(name() + ".int_inst_queue_reads") 338 .desc("Number of integer instruction queue reads") 339 .flags(total); 340 341 intInstQueueWrites 342 .name(name() + ".int_inst_queue_writes") 343 .desc("Number of integer instruction queue writes") 344 .flags(total); 345 346 intInstQueueWakeupAccesses 347 .name(name() + ".int_inst_queue_wakeup_accesses") 348 .desc("Number of integer instruction queue wakeup accesses") 349 .flags(total); 350 351 fpInstQueueReads 352 .name(name() + ".fp_inst_queue_reads") 353 .desc("Number of floating instruction queue reads") 354 .flags(total); 355 356 fpInstQueueWrites 357 .name(name() + ".fp_inst_queue_writes") 358 .desc("Number of floating instruction queue writes") 359 .flags(total); 360 361 fpInstQueueWakeupQccesses 362 .name(name() + ".fp_inst_queue_wakeup_accesses") 363 .desc("Number of floating instruction queue wakeup accesses") 364 .flags(total); 365 366 intAluAccesses 367 .name(name() + ".int_alu_accesses") 368 .desc("Number of integer alu accesses") 369 .flags(total); 370 371 fpAluAccesses 372 .name(name() + ".fp_alu_accesses") 373 .desc("Number of floating point alu accesses") 374 .flags(total); 375 376} 377 378template <class Impl> 379void 380InstructionQueue<Impl>::resetState() 381{ 382 //Initialize thread IQ counts 383 for (ThreadID tid = 0; tid <numThreads; tid++) { 384 count[tid] = 0; 385 instList[tid].clear(); 386 } 387 388 // Initialize the number of free IQ entries. 389 freeEntries = numEntries; 390 391 // Note that in actuality, the registers corresponding to the logical 392 // registers start off as ready. However this doesn't matter for the 393 // IQ as the instruction should have been correctly told if those 394 // registers are ready in rename. Thus it can all be initialized as 395 // unready. 396 for (int i = 0; i < numPhysRegs; ++i) { 397 regScoreboard[i] = false; 398 } 399 400 for (ThreadID tid = 0; tid < numThreads; ++tid) { 401 squashedSeqNum[tid] = 0; 402 } 403 404 for (int i = 0; i < Num_OpClasses; ++i) { 405 while (!readyInsts[i].empty()) 406 readyInsts[i].pop(); 407 queueOnList[i] = false; 408 readyIt[i] = listOrder.end(); 409 } 410 nonSpecInsts.clear(); 411 listOrder.clear(); 412 deferredMemInsts.clear(); 413} 414 415template <class Impl> 416void 417InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 418{ 419 activeThreads = at_ptr; 420} 421 422template <class Impl> 423void 424InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 425{ 426 issueToExecuteQueue = i2e_ptr; 427} 428 429template <class Impl> 430void 431InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 432{ 433 timeBuffer = tb_ptr; 434 435 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 436} 437 438template <class Impl> 439void 440InstructionQueue<Impl>::drainSanityCheck() const 441{ 442 assert(dependGraph.empty()); 443 assert(instsToExecute.empty()); 444 for (ThreadID tid = 0; tid < numThreads; ++tid) 445 memDepUnit[tid].drainSanityCheck(); 446} 447 448template <class Impl> 449void 450InstructionQueue<Impl>::takeOverFrom() 451{ 452 resetState(); 453} 454 455template <class Impl> 456int 457InstructionQueue<Impl>::entryAmount(ThreadID num_threads) 458{ 459 if (iqPolicy == Partitioned) { 460 return numEntries / num_threads; 461 } else { 462 return 0; 463 } 464} 465 466 467template <class Impl> 468void 469InstructionQueue<Impl>::resetEntries() 470{ 471 if (iqPolicy != Dynamic || numThreads > 1) { 472 int active_threads = activeThreads->size(); 473 474 list<ThreadID>::iterator threads = activeThreads->begin(); 475 list<ThreadID>::iterator end = activeThreads->end(); 476 477 while (threads != end) { 478 ThreadID tid = *threads++; 479 480 if (iqPolicy == Partitioned) { 481 maxEntries[tid] = numEntries / active_threads; 482 } else if(iqPolicy == Threshold && active_threads == 1) { 483 maxEntries[tid] = numEntries; 484 } 485 } 486 } 487} 488 489template <class Impl> 490unsigned 491InstructionQueue<Impl>::numFreeEntries() 492{ 493 return freeEntries; 494} 495 496template <class Impl> 497unsigned 498InstructionQueue<Impl>::numFreeEntries(ThreadID tid) 499{ 500 return maxEntries[tid] - count[tid]; 501} 502 503// Might want to do something more complex if it knows how many instructions 504// will be issued this cycle. 505template <class Impl> 506bool 507InstructionQueue<Impl>::isFull() 508{ 509 if (freeEntries == 0) { 510 return(true); 511 } else { 512 return(false); 513 } 514} 515 516template <class Impl> 517bool 518InstructionQueue<Impl>::isFull(ThreadID tid) 519{ 520 if (numFreeEntries(tid) == 0) { 521 return(true); 522 } else { 523 return(false); 524 } 525} 526 527template <class Impl> 528bool 529InstructionQueue<Impl>::hasReadyInsts() 530{ 531 if (!listOrder.empty()) { 532 return true; 533 } 534 535 for (int i = 0; i < Num_OpClasses; ++i) { 536 if (!readyInsts[i].empty()) { 537 return true; 538 } 539 } 540 541 return false; 542} 543 544template <class Impl> 545void 546InstructionQueue<Impl>::insert(DynInstPtr &new_inst) 547{ 548 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 549 // Make sure the instruction is valid 550 assert(new_inst); 551 552 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 553 new_inst->seqNum, new_inst->pcState()); 554 555 assert(freeEntries != 0); 556 557 instList[new_inst->threadNumber].push_back(new_inst); 558 559 --freeEntries; 560 561 new_inst->setInIQ(); 562 563 // Look through its source registers (physical regs), and mark any 564 // dependencies. 565 addToDependents(new_inst); 566 567 // Have this instruction set itself as the producer of its destination 568 // register(s). 569 addToProducers(new_inst); 570 571 if (new_inst->isMemRef()) { 572 memDepUnit[new_inst->threadNumber].insert(new_inst); 573 } else { 574 addIfReady(new_inst); 575 } 576 577 ++iqInstsAdded; 578 579 count[new_inst->threadNumber]++; 580 581 assert(freeEntries == (numEntries - countInsts())); 582} 583 584template <class Impl> 585void 586InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 587{ 588 // @todo: Clean up this code; can do it by setting inst as unable 589 // to issue, then calling normal insert on the inst. 590 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 591 592 assert(new_inst); 593 594 nonSpecInsts[new_inst->seqNum] = new_inst; 595 596 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 597 "to the IQ.\n", 598 new_inst->seqNum, new_inst->pcState()); 599 600 assert(freeEntries != 0); 601 602 instList[new_inst->threadNumber].push_back(new_inst); 603 604 --freeEntries; 605 606 new_inst->setInIQ(); 607 608 // Have this instruction set itself as the producer of its destination 609 // register(s). 610 addToProducers(new_inst); 611 612 // If it's a memory instruction, add it to the memory dependency 613 // unit. 614 if (new_inst->isMemRef()) { 615 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 616 } 617 618 ++iqNonSpecInstsAdded; 619 620 count[new_inst->threadNumber]++; 621 622 assert(freeEntries == (numEntries - countInsts())); 623} 624 625template <class Impl> 626void 627InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 628{ 629 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 630 631 insertNonSpec(barr_inst); 632} 633 634template <class Impl> 635typename Impl::DynInstPtr 636InstructionQueue<Impl>::getInstToExecute() 637{ 638 assert(!instsToExecute.empty()); 639 DynInstPtr inst = instsToExecute.front(); 640 instsToExecute.pop_front(); 641 if (inst->isFloating()){ 642 fpInstQueueReads++; 643 } else { 644 intInstQueueReads++; 645 } 646 return inst; 647} 648 649template <class Impl> 650void 651InstructionQueue<Impl>::addToOrderList(OpClass op_class) 652{ 653 assert(!readyInsts[op_class].empty()); 654 655 ListOrderEntry queue_entry; 656 657 queue_entry.queueType = op_class; 658 659 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 660 661 ListOrderIt list_it = listOrder.begin(); 662 ListOrderIt list_end_it = listOrder.end(); 663 664 while (list_it != list_end_it) { 665 if ((*list_it).oldestInst > queue_entry.oldestInst) { 666 break; 667 } 668 669 list_it++; 670 } 671 672 readyIt[op_class] = listOrder.insert(list_it, queue_entry); 673 queueOnList[op_class] = true; 674} 675 676template <class Impl> 677void 678InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 679{ 680 // Get iterator of next item on the list 681 // Delete the original iterator 682 // Determine if the next item is either the end of the list or younger 683 // than the new instruction. If so, then add in a new iterator right here. 684 // If not, then move along. 685 ListOrderEntry queue_entry; 686 OpClass op_class = (*list_order_it).queueType; 687 ListOrderIt next_it = list_order_it; 688 689 ++next_it; 690 691 queue_entry.queueType = op_class; 692 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 693 694 while (next_it != listOrder.end() && 695 (*next_it).oldestInst < queue_entry.oldestInst) { 696 ++next_it; 697 } 698 699 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 700} 701 702template <class Impl> 703void 704InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 705{ 706 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 707 assert(!cpu->switchedOut()); 708 // The CPU could have been sleeping until this op completed (*extremely* 709 // long latency op). Wake it if it was. This may be overkill. 710 iewStage->wakeCPU(); 711 712 if (fu_idx > -1) 713 fuPool->freeUnitNextCycle(fu_idx); 714 715 // @todo: Ensure that these FU Completions happen at the beginning 716 // of a cycle, otherwise they could add too many instructions to 717 // the queue. 718 issueToExecuteQueue->access(-1)->size++; 719 instsToExecute.push_back(inst); 720} 721 722// @todo: Figure out a better way to remove the squashed items from the 723// lists. Checking the top item of each list to see if it's squashed 724// wastes time and forces jumps. 725template <class Impl> 726void 727InstructionQueue<Impl>::scheduleReadyInsts() 728{ 729 DPRINTF(IQ, "Attempting to schedule ready instructions from " 730 "the IQ.\n"); 731 732 IssueStruct *i2e_info = issueToExecuteQueue->access(0); 733 734 DynInstPtr deferred_mem_inst; 735 int total_deferred_mem_issued = 0; 736 while (total_deferred_mem_issued < totalWidth && 737 (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { 738 issueToExecuteQueue->access(0)->size++; 739 instsToExecute.push_back(deferred_mem_inst); 740 total_deferred_mem_issued++; 741 } 742 743 // Have iterator to head of the list 744 // While I haven't exceeded bandwidth or reached the end of the list, 745 // Try to get a FU that can do what this op needs. 746 // If successful, change the oldestInst to the new top of the list, put 747 // the queue in the proper place in the list. 748 // Increment the iterator. 749 // This will avoid trying to schedule a certain op class if there are no 750 // FUs that handle it. 751 ListOrderIt order_it = listOrder.begin(); 752 ListOrderIt order_end_it = listOrder.end(); 753 int total_issued = 0; 754 755 while (total_issued < (totalWidth - total_deferred_mem_issued) && 756 iewStage->canIssue() && 757 order_it != order_end_it) { 758 OpClass op_class = (*order_it).queueType; 759 760 assert(!readyInsts[op_class].empty()); 761 762 DynInstPtr issuing_inst = readyInsts[op_class].top(); 763 764 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 765 766 assert(issuing_inst->seqNum == (*order_it).oldestInst); 767 768 if (issuing_inst->isSquashed()) { 769 readyInsts[op_class].pop(); 770 771 if (!readyInsts[op_class].empty()) { 772 moveToYoungerInst(order_it); 773 } else { 774 readyIt[op_class] = listOrder.end(); 775 queueOnList[op_class] = false; 776 } 777 778 listOrder.erase(order_it++); 779 780 ++iqSquashedInstsIssued; 781 782 continue; 783 } 784 785 int idx = -2; 786 Cycles op_latency = Cycles(1); 787 ThreadID tid = issuing_inst->threadNumber; 788 789 if (op_class != No_OpClass) { 790 idx = fuPool->getUnit(op_class); 791 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 792 if (idx > -1) { 793 op_latency = fuPool->getOpLatency(op_class); 794 } 795 } 796 797 // If we have an instruction that doesn't require a FU, or a 798 // valid FU, then schedule for execution. 799 if (idx == -2 || idx != -1) { 800 if (op_latency == Cycles(1)) { 801 i2e_info->size++; 802 instsToExecute.push_back(issuing_inst); 803 804 // Add the FU onto the list of FU's to be freed next 805 // cycle if we used one. 806 if (idx >= 0) 807 fuPool->freeUnitNextCycle(idx); 808 } else { 809 Cycles issue_latency = fuPool->getIssueLatency(op_class); 810 // Generate completion event for the FU 811 FUCompletion *execution = new FUCompletion(issuing_inst, 812 idx, this); 813 814 cpu->schedule(execution, 815 cpu->clockEdge(Cycles(op_latency - 1))); 816 817 // @todo: Enforce that issue_latency == 1 or op_latency 818 if (issue_latency > Cycles(1)) { 819 // If FU isn't pipelined, then it must be freed 820 // upon the execution completing. 821 execution->setFreeFU(); 822 } else { 823 // Add the FU onto the list of FU's to be freed next cycle. 824 fuPool->freeUnitNextCycle(idx); 825 } 826 } 827 828 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 829 "[sn:%lli]\n", 830 tid, issuing_inst->pcState(), 831 issuing_inst->seqNum); 832 833 readyInsts[op_class].pop(); 834 835 if (!readyInsts[op_class].empty()) { 836 moveToYoungerInst(order_it); 837 } else { 838 readyIt[op_class] = listOrder.end(); 839 queueOnList[op_class] = false; 840 } 841 842 issuing_inst->setIssued(); 843 ++total_issued; 844 845#if TRACING_ON 846 issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 847#endif 848 849 if (!issuing_inst->isMemRef()) { 850 // Memory instructions can not be freed from the IQ until they 851 // complete. 852 ++freeEntries; 853 count[tid]--; 854 issuing_inst->clearInIQ(); 855 } else { 856 memDepUnit[tid].issue(issuing_inst); 857 } 858 859 listOrder.erase(order_it++); 860 statIssuedInstType[tid][op_class]++; 861 iewStage->incrWb(issuing_inst->seqNum); 862 } else { 863 statFuBusy[op_class]++; 864 fuBusy[tid]++; 865 ++order_it; 866 } 867 } 868 869 numIssuedDist.sample(total_issued); 870 iqInstsIssued+= total_issued; 871 872 // If we issued any instructions, tell the CPU we had activity. 873 // @todo If the way deferred memory instructions are handeled due to 874 // translation changes then the deferredMemInsts condition should be removed 875 // from the code below. 876 if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) { 877 cpu->activityThisCycle(); 878 } else { 879 DPRINTF(IQ, "Not able to schedule any instructions.\n"); 880 } 881} 882 883template <class Impl> 884void 885InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 886{ 887 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 888 "to execute.\n", inst); 889 890 NonSpecMapIt inst_it = nonSpecInsts.find(inst); 891 892 assert(inst_it != nonSpecInsts.end()); 893 894 ThreadID tid = (*inst_it).second->threadNumber; 895 896 (*inst_it).second->setAtCommit(); 897 898 (*inst_it).second->setCanIssue(); 899 900 if (!(*inst_it).second->isMemRef()) { 901 addIfReady((*inst_it).second); 902 } else { 903 memDepUnit[tid].nonSpecInstReady((*inst_it).second); 904 } 905 906 (*inst_it).second = NULL; 907 908 nonSpecInsts.erase(inst_it); 909} 910 911template <class Impl> 912void 913InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 914{ 915 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 916 tid,inst); 917 918 ListIt iq_it = instList[tid].begin(); 919 920 while (iq_it != instList[tid].end() && 921 (*iq_it)->seqNum <= inst) { 922 ++iq_it; 923 instList[tid].pop_front(); 924 } 925 926 assert(freeEntries == (numEntries - countInsts())); 927} 928 929template <class Impl> 930int 931InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 932{ 933 int dependents = 0; 934 935 // The instruction queue here takes care of both floating and int ops 936 if (completed_inst->isFloating()) { 937 fpInstQueueWakeupQccesses++; 938 } else { 939 intInstQueueWakeupAccesses++; 940 } 941 942 DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 943 944 assert(!completed_inst->isSquashed()); 945 946 // Tell the memory dependence unit to wake any dependents on this 947 // instruction if it is a memory instruction. Also complete the memory 948 // instruction at this point since we know it executed without issues. 949 // @todo: Might want to rename "completeMemInst" to something that 950 // indicates that it won't need to be replayed, and call this 951 // earlier. Might not be a big deal. 952 if (completed_inst->isMemRef()) { 953 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 954 completeMemInst(completed_inst); 955 } else if (completed_inst->isMemBarrier() || 956 completed_inst->isWriteBarrier()) { 957 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 958 } 959 960 for (int dest_reg_idx = 0; 961 dest_reg_idx < completed_inst->numDestRegs(); 962 dest_reg_idx++) 963 { 964 PhysRegIndex dest_reg = 965 completed_inst->renamedDestRegIdx(dest_reg_idx); 966 967 // Special case of uniq or control registers. They are not 968 // handled by the IQ and thus have no dependency graph entry. 969 // @todo Figure out a cleaner way to handle this. 970 if (dest_reg >= numPhysRegs) { 971 DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 972 numPhysRegs); 973 continue; 974 } 975 976 DPRINTF(IQ, "Waking any dependents on register %i.\n", 977 (int) dest_reg); 978 979 //Go through the dependency chain, marking the registers as 980 //ready within the waiting instructions. 981 DynInstPtr dep_inst = dependGraph.pop(dest_reg); 982 983 while (dep_inst) { 984 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 985 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 986 987 // Might want to give more information to the instruction 988 // so that it knows which of its source registers is 989 // ready. However that would mean that the dependency 990 // graph entries would need to hold the src_reg_idx. 991 dep_inst->markSrcRegReady(); 992 993 addIfReady(dep_inst); 994 995 dep_inst = dependGraph.pop(dest_reg); 996 997 ++dependents; 998 } 999 1000 // Reset the head node now that all of its dependents have 1001 // been woken up. 1002 assert(dependGraph.empty(dest_reg)); 1003 dependGraph.clearInst(dest_reg); 1004 1005 // Mark the scoreboard as having that register ready. 1006 regScoreboard[dest_reg] = true; 1007 } 1008 return dependents; 1009} 1010 1011template <class Impl> 1012void 1013InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 1014{ 1015 OpClass op_class = ready_inst->opClass(); 1016 1017 readyInsts[op_class].push(ready_inst); 1018 1019 // Will need to reorder the list if either a queue is not on the list, 1020 // or it has an older instruction than last time. 1021 if (!queueOnList[op_class]) { 1022 addToOrderList(op_class); 1023 } else if (readyInsts[op_class].top()->seqNum < 1024 (*readyIt[op_class]).oldestInst) { 1025 listOrder.erase(readyIt[op_class]); 1026 addToOrderList(op_class); 1027 } 1028 1029 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1030 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1031 ready_inst->pcState(), op_class, ready_inst->seqNum); 1032} 1033 1034template <class Impl> 1035void 1036InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 1037{ 1038 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 1039 1040 // Reset DTB translation state 1041 resched_inst->translationStarted(false); 1042 resched_inst->translationCompleted(false); 1043 1044 resched_inst->clearCanIssue(); 1045 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 1046} 1047 1048template <class Impl> 1049void 1050InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 1051{ 1052 memDepUnit[replay_inst->threadNumber].replay(replay_inst); 1053} 1054 1055template <class Impl> 1056void 1057InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 1058{ 1059 ThreadID tid = completed_inst->threadNumber; 1060 1061 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 1062 completed_inst->pcState(), completed_inst->seqNum); 1063 1064 ++freeEntries; 1065 1066 completed_inst->memOpDone(true); 1067 1068 memDepUnit[tid].completed(completed_inst); 1069 count[tid]--; 1070} 1071 1072template <class Impl> 1073void 1074InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 1075{ 1076 deferredMemInsts.push_back(deferred_inst); 1077} 1078 1079template <class Impl> 1080typename Impl::DynInstPtr 1081InstructionQueue<Impl>::getDeferredMemInstToExecute() 1082{ 1083 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 1084 ++it) { 1085 if ((*it)->translationCompleted() || (*it)->isSquashed()) { 1086 DynInstPtr ret = *it; 1087 deferredMemInsts.erase(it); 1088 return ret; 1089 } 1090 } 1091 return NULL; 1092} 1093 1094template <class Impl> 1095void 1096InstructionQueue<Impl>::violation(DynInstPtr &store, 1097 DynInstPtr &faulting_load) 1098{ 1099 intInstQueueWrites++; 1100 memDepUnit[store->threadNumber].violation(store, faulting_load); 1101} 1102 1103template <class Impl> 1104void 1105InstructionQueue<Impl>::squash(ThreadID tid) 1106{ 1107 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 1108 "the IQ.\n", tid); 1109 1110 // Read instruction sequence number of last instruction out of the 1111 // time buffer. 1112 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 1113 1114 // Call doSquash if there are insts in the IQ 1115 if (count[tid] > 0) { 1116 doSquash(tid); 1117 } 1118 1119 // Also tell the memory dependence unit to squash. 1120 memDepUnit[tid].squash(squashedSeqNum[tid], tid); 1121} 1122 1123template <class Impl> 1124void 1125InstructionQueue<Impl>::doSquash(ThreadID tid) 1126{ 1127 // Start at the tail. 1128 ListIt squash_it = instList[tid].end(); 1129 --squash_it; 1130 1131 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 1132 tid, squashedSeqNum[tid]); 1133 1134 // Squash any instructions younger than the squashed sequence number 1135 // given. 1136 while (squash_it != instList[tid].end() && 1137 (*squash_it)->seqNum > squashedSeqNum[tid]) { 1138 1139 DynInstPtr squashed_inst = (*squash_it); 1140 squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 1141 1142 // Only handle the instruction if it actually is in the IQ and 1143 // hasn't already been squashed in the IQ. 1144 if (squashed_inst->threadNumber != tid || 1145 squashed_inst->isSquashedInIQ()) { 1146 --squash_it; 1147 continue; 1148 } 1149 1150 if (!squashed_inst->isIssued() || 1151 (squashed_inst->isMemRef() && 1152 !squashed_inst->memOpDone())) { 1153 1154 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 1155 tid, squashed_inst->seqNum, squashed_inst->pcState()); 1156 1157 // Remove the instruction from the dependency list. 1158 if (!squashed_inst->isNonSpeculative() && 1159 !squashed_inst->isStoreConditional() && 1160 !squashed_inst->isMemBarrier() && 1161 !squashed_inst->isWriteBarrier()) { 1162 1163 for (int src_reg_idx = 0; 1164 src_reg_idx < squashed_inst->numSrcRegs(); 1165 src_reg_idx++) 1166 { 1167 PhysRegIndex src_reg = 1168 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1169 1170 // Only remove it from the dependency graph if it 1171 // was placed there in the first place. 1172 1173 // Instead of doing a linked list traversal, we 1174 // can just remove these squashed instructions 1175 // either at issue time, or when the register is 1176 // overwritten. The only downside to this is it 1177 // leaves more room for error. 1178 1179 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1180 src_reg < numPhysRegs) { 1181 dependGraph.remove(src_reg, squashed_inst); 1182 } 1183 1184 1185 ++iqSquashedOperandsExamined; 1186 } 1187 } else if (!squashed_inst->isStoreConditional() || 1188 !squashed_inst->isCompleted()) { 1189 NonSpecMapIt ns_inst_it = 1190 nonSpecInsts.find(squashed_inst->seqNum); 1191 1192 if (ns_inst_it == nonSpecInsts.end()) { 1193 assert(squashed_inst->getFault() != NoFault); 1194 } else { 1195 1196 (*ns_inst_it).second = NULL; 1197 1198 nonSpecInsts.erase(ns_inst_it); 1199 1200 ++iqSquashedNonSpecRemoved; 1201 } 1202 } 1203 1204 // Might want to also clear out the head of the dependency graph. 1205 1206 // Mark it as squashed within the IQ. 1207 squashed_inst->setSquashedInIQ(); 1208 1209 // @todo: Remove this hack where several statuses are set so the 1210 // inst will flow through the rest of the pipeline. 1211 squashed_inst->setIssued(); 1212 squashed_inst->setCanCommit(); 1213 squashed_inst->clearInIQ(); 1214 1215 //Update Thread IQ Count 1216 count[squashed_inst->threadNumber]--; 1217 1218 ++freeEntries; 1219 } 1220 1221 instList[tid].erase(squash_it--); 1222 ++iqSquashedInstsExamined; 1223 } 1224} 1225 1226template <class Impl> 1227bool 1228InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1229{ 1230 // Loop through the instruction's source registers, adding 1231 // them to the dependency list if they are not ready. 1232 int8_t total_src_regs = new_inst->numSrcRegs(); 1233 bool return_val = false; 1234 1235 for (int src_reg_idx = 0; 1236 src_reg_idx < total_src_regs; 1237 src_reg_idx++) 1238 { 1239 // Only add it to the dependency graph if it's not ready. 1240 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1241 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1242 1243 // Check the IQ's scoreboard to make sure the register 1244 // hasn't become ready while the instruction was in flight 1245 // between stages. Only if it really isn't ready should 1246 // it be added to the dependency graph. 1247 if (src_reg >= numPhysRegs) { 1248 continue; 1249 } else if (regScoreboard[src_reg] == false) { 1250 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1251 "is being added to the dependency chain.\n", 1252 new_inst->pcState(), src_reg); 1253 1254 dependGraph.insert(src_reg, new_inst); 1255 1256 // Change the return value to indicate that something 1257 // was added to the dependency graph. 1258 return_val = true; 1259 } else { 1260 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1261 "became ready before it reached the IQ.\n", 1262 new_inst->pcState(), src_reg); 1263 // Mark a register ready within the instruction. 1264 new_inst->markSrcRegReady(src_reg_idx); 1265 } 1266 } 1267 } 1268 1269 return return_val; 1270} 1271 1272template <class Impl> 1273void 1274InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 1275{ 1276 // Nothing really needs to be marked when an instruction becomes 1277 // the producer of a register's value, but for convenience a ptr 1278 // to the producing instruction will be placed in the head node of 1279 // the dependency links. 1280 int8_t total_dest_regs = new_inst->numDestRegs(); 1281 1282 for (int dest_reg_idx = 0; 1283 dest_reg_idx < total_dest_regs; 1284 dest_reg_idx++) 1285 { 1286 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1287 1288 // Instructions that use the misc regs will have a reg number 1289 // higher than the normal physical registers. In this case these 1290 // registers are not renamed, and there is no need to track 1291 // dependencies as these instructions must be executed at commit. 1292 if (dest_reg >= numPhysRegs) { 1293 continue; 1294 } 1295 1296 if (!dependGraph.empty(dest_reg)) { 1297 dependGraph.dump(); 1298 panic("Dependency graph %i not empty!", dest_reg); 1299 } 1300 1301 dependGraph.setInst(dest_reg, new_inst); 1302 1303 // Mark the scoreboard to say it's not yet ready. 1304 regScoreboard[dest_reg] = false; 1305 } 1306} 1307 1308template <class Impl> 1309void 1310InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1311{ 1312 // If the instruction now has all of its source registers 1313 // available, then add it to the list of ready instructions. 1314 if (inst->readyToIssue()) { 1315 1316 //Add the instruction to the proper ready list. 1317 if (inst->isMemRef()) { 1318 1319 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1320 1321 // Message to the mem dependence unit that this instruction has 1322 // its registers ready. 1323 memDepUnit[inst->threadNumber].regsReady(inst); 1324 1325 return; 1326 } 1327 1328 OpClass op_class = inst->opClass(); 1329 1330 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1331 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1332 inst->pcState(), op_class, inst->seqNum); 1333 1334 readyInsts[op_class].push(inst); 1335 1336 // Will need to reorder the list if either a queue is not on the list, 1337 // or it has an older instruction than last time. 1338 if (!queueOnList[op_class]) { 1339 addToOrderList(op_class); 1340 } else if (readyInsts[op_class].top()->seqNum < 1341 (*readyIt[op_class]).oldestInst) { 1342 listOrder.erase(readyIt[op_class]); 1343 addToOrderList(op_class); 1344 } 1345 } 1346} 1347 1348template <class Impl> 1349int 1350InstructionQueue<Impl>::countInsts() 1351{ 1352#if 0 1353 //ksewell:This works but definitely could use a cleaner write 1354 //with a more intuitive way of counting. Right now it's 1355 //just brute force .... 1356 // Change the #if if you want to use this method. 1357 int total_insts = 0; 1358 1359 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1360 ListIt count_it = instList[tid].begin(); 1361 1362 while (count_it != instList[tid].end()) { 1363 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1364 if (!(*count_it)->isIssued()) { 1365 ++total_insts; 1366 } else if ((*count_it)->isMemRef() && 1367 !(*count_it)->memOpDone) { 1368 // Loads that have not been marked as executed still count 1369 // towards the total instructions. 1370 ++total_insts; 1371 } 1372 } 1373 1374 ++count_it; 1375 } 1376 } 1377 1378 return total_insts; 1379#else 1380 return numEntries - freeEntries; 1381#endif 1382} 1383 1384template <class Impl> 1385void 1386InstructionQueue<Impl>::dumpLists() 1387{ 1388 for (int i = 0; i < Num_OpClasses; ++i) { 1389 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1390 1391 cprintf("\n"); 1392 } 1393 1394 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1395 1396 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1397 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1398 1399 cprintf("Non speculative list: "); 1400 1401 while (non_spec_it != non_spec_end_it) { 1402 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 1403 (*non_spec_it).second->seqNum); 1404 ++non_spec_it; 1405 } 1406 1407 cprintf("\n"); 1408 1409 ListOrderIt list_order_it = listOrder.begin(); 1410 ListOrderIt list_order_end_it = listOrder.end(); 1411 int i = 1; 1412 1413 cprintf("List order: "); 1414 1415 while (list_order_it != list_order_end_it) { 1416 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1417 (*list_order_it).oldestInst); 1418 1419 ++list_order_it; 1420 ++i; 1421 } 1422 1423 cprintf("\n"); 1424} 1425 1426 1427template <class Impl> 1428void 1429InstructionQueue<Impl>::dumpInsts() 1430{ 1431 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1432 int num = 0; 1433 int valid_num = 0; 1434 ListIt inst_list_it = instList[tid].begin(); 1435 1436 while (inst_list_it != instList[tid].end()) { 1437 cprintf("Instruction:%i\n", num); 1438 if (!(*inst_list_it)->isSquashed()) { 1439 if (!(*inst_list_it)->isIssued()) { 1440 ++valid_num; 1441 cprintf("Count:%i\n", valid_num); 1442 } else if ((*inst_list_it)->isMemRef() && 1443 !(*inst_list_it)->memOpDone()) { 1444 // Loads that have not been marked as executed 1445 // still count towards the total instructions. 1446 ++valid_num; 1447 cprintf("Count:%i\n", valid_num); 1448 } 1449 } 1450 1451 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1452 "Issued:%i\nSquashed:%i\n", 1453 (*inst_list_it)->pcState(), 1454 (*inst_list_it)->seqNum, 1455 (*inst_list_it)->threadNumber, 1456 (*inst_list_it)->isIssued(), 1457 (*inst_list_it)->isSquashed()); 1458 1459 if ((*inst_list_it)->isMemRef()) { 1460 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1461 } 1462 1463 cprintf("\n"); 1464 1465 inst_list_it++; 1466 ++num; 1467 } 1468 } 1469 1470 cprintf("Insts to Execute list:\n"); 1471 1472 int num = 0; 1473 int valid_num = 0; 1474 ListIt inst_list_it = instsToExecute.begin(); 1475 1476 while (inst_list_it != instsToExecute.end()) 1477 { 1478 cprintf("Instruction:%i\n", 1479 num); 1480 if (!(*inst_list_it)->isSquashed()) { 1481 if (!(*inst_list_it)->isIssued()) { 1482 ++valid_num; 1483 cprintf("Count:%i\n", valid_num); 1484 } else if ((*inst_list_it)->isMemRef() && 1485 !(*inst_list_it)->memOpDone()) { 1486 // Loads that have not been marked as executed 1487 // still count towards the total instructions. 1488 ++valid_num; 1489 cprintf("Count:%i\n", valid_num); 1490 } 1491 } 1492 1493 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1494 "Issued:%i\nSquashed:%i\n", 1495 (*inst_list_it)->pcState(), 1496 (*inst_list_it)->seqNum, 1497 (*inst_list_it)->threadNumber, 1498 (*inst_list_it)->isIssued(), 1499 (*inst_list_it)->isSquashed()); 1500 1501 if ((*inst_list_it)->isMemRef()) { 1502 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1503 } 1504 1505 cprintf("\n"); 1506 1507 inst_list_it++; 1508 ++num; 1509 } 1510} 1511