inst_queue_impl.hh revision 2935
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292831Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322064SN/A#include <limits> 331060SN/A#include <vector> 341060SN/A 351696SN/A#include "sim/root.hh" 361689SN/A 372292SN/A#include "cpu/o3/fu_pool.hh" 381717SN/A#include "cpu/o3/inst_queue.hh" 391060SN/A 402292SN/Ausing namespace std; 411060SN/A 421061SN/Atemplate <class Impl> 432292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 442292SN/A int fu_idx, 452292SN/A InstructionQueue<Impl> *iq_ptr) 462292SN/A : Event(&mainEventQueue, Stat_Event_Pri), 472326SN/A inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 481060SN/A{ 492292SN/A this->setFlags(Event::AutoDelete); 502292SN/A} 512292SN/A 522292SN/Atemplate <class Impl> 532292SN/Avoid 542292SN/AInstructionQueue<Impl>::FUCompletion::process() 552292SN/A{ 562326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 572292SN/A inst = NULL; 582292SN/A} 592292SN/A 602292SN/A 612292SN/Atemplate <class Impl> 622292SN/Aconst char * 632292SN/AInstructionQueue<Impl>::FUCompletion::description() 642292SN/A{ 652292SN/A return "Functional unit completion event"; 662292SN/A} 672292SN/A 682292SN/Atemplate <class Impl> 692292SN/AInstructionQueue<Impl>::InstructionQueue(Params *params) 702669Sktlim@umich.edu : fuPool(params->fuPool), 712292SN/A numEntries(params->numIQEntries), 722292SN/A totalWidth(params->issueWidth), 732292SN/A numPhysIntRegs(params->numPhysIntRegs), 742292SN/A numPhysFloatRegs(params->numPhysFloatRegs), 752292SN/A commitToIEWDelay(params->commitToIEWDelay) 762292SN/A{ 772292SN/A assert(fuPool); 782292SN/A 792307SN/A switchedOut = false; 802307SN/A 812292SN/A numThreads = params->numberOfThreads; 821060SN/A 831060SN/A // Set the number of physical registers as the number of int + float 841060SN/A numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 851060SN/A 862292SN/A DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs); 871060SN/A 881060SN/A //Create an entry for each physical register within the 891060SN/A //dependency graph. 902326SN/A dependGraph.resize(numPhysRegs); 911060SN/A 921060SN/A // Resize the register scoreboard. 931060SN/A regScoreboard.resize(numPhysRegs); 941060SN/A 952292SN/A //Initialize Mem Dependence Units 962292SN/A for (int i = 0; i < numThreads; i++) { 972292SN/A memDepUnit[i].init(params,i); 982292SN/A memDepUnit[i].setIQ(this); 991060SN/A } 1001060SN/A 1012307SN/A resetState(); 1022292SN/A 1032292SN/A string policy = params->smtIQPolicy; 1042292SN/A 1052292SN/A //Convert string to lowercase 1062292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1072292SN/A (int(*)(int)) tolower); 1082292SN/A 1092292SN/A //Figure out resource sharing policy 1102292SN/A if (policy == "dynamic") { 1112292SN/A iqPolicy = Dynamic; 1122292SN/A 1132292SN/A //Set Max Entries to Total ROB Capacity 1142292SN/A for (int i = 0; i < numThreads; i++) { 1152292SN/A maxEntries[i] = numEntries; 1162292SN/A } 1172292SN/A 1182292SN/A } else if (policy == "partitioned") { 1192292SN/A iqPolicy = Partitioned; 1202292SN/A 1212292SN/A //@todo:make work if part_amt doesnt divide evenly. 1222292SN/A int part_amt = numEntries / numThreads; 1232292SN/A 1242292SN/A //Divide ROB up evenly 1252292SN/A for (int i = 0; i < numThreads; i++) { 1262292SN/A maxEntries[i] = part_amt; 1272292SN/A } 1282292SN/A 1292831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1302292SN/A "%i entries per thread.\n",part_amt); 1312292SN/A 1322292SN/A } else if (policy == "threshold") { 1332292SN/A iqPolicy = Threshold; 1342292SN/A 1352292SN/A double threshold = (double)params->smtIQThreshold / 100; 1362292SN/A 1372292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1382292SN/A 1392292SN/A //Divide up by threshold amount 1402292SN/A for (int i = 0; i < numThreads; i++) { 1412292SN/A maxEntries[i] = thresholdIQ; 1422292SN/A } 1432292SN/A 1442831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1452292SN/A "%i entries per thread.\n",thresholdIQ); 1462292SN/A } else { 1472292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1482292SN/A "Partitioned, Threshold}"); 1492292SN/A } 1502292SN/A} 1512292SN/A 1522292SN/Atemplate <class Impl> 1532292SN/AInstructionQueue<Impl>::~InstructionQueue() 1542292SN/A{ 1552326SN/A dependGraph.reset(); 1562348SN/A#ifdef DEBUG 1572326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1582326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1592348SN/A#endif 1602292SN/A} 1612292SN/A 1622292SN/Atemplate <class Impl> 1632292SN/Astd::string 1642292SN/AInstructionQueue<Impl>::name() const 1652292SN/A{ 1662292SN/A return cpu->name() + ".iq"; 1671060SN/A} 1681060SN/A 1691061SN/Atemplate <class Impl> 1701060SN/Avoid 1711062SN/AInstructionQueue<Impl>::regStats() 1721062SN/A{ 1732301SN/A using namespace Stats; 1741062SN/A iqInstsAdded 1751062SN/A .name(name() + ".iqInstsAdded") 1761062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1771062SN/A .prereq(iqInstsAdded); 1781062SN/A 1791062SN/A iqNonSpecInstsAdded 1801062SN/A .name(name() + ".iqNonSpecInstsAdded") 1811062SN/A .desc("Number of non-speculative instructions added to the IQ") 1821062SN/A .prereq(iqNonSpecInstsAdded); 1831062SN/A 1842301SN/A iqInstsIssued 1852301SN/A .name(name() + ".iqInstsIssued") 1862301SN/A .desc("Number of instructions issued") 1872301SN/A .prereq(iqInstsIssued); 1881062SN/A 1891062SN/A iqIntInstsIssued 1901062SN/A .name(name() + ".iqIntInstsIssued") 1911062SN/A .desc("Number of integer instructions issued") 1921062SN/A .prereq(iqIntInstsIssued); 1931062SN/A 1941062SN/A iqFloatInstsIssued 1951062SN/A .name(name() + ".iqFloatInstsIssued") 1961062SN/A .desc("Number of float instructions issued") 1971062SN/A .prereq(iqFloatInstsIssued); 1981062SN/A 1991062SN/A iqBranchInstsIssued 2001062SN/A .name(name() + ".iqBranchInstsIssued") 2011062SN/A .desc("Number of branch instructions issued") 2021062SN/A .prereq(iqBranchInstsIssued); 2031062SN/A 2041062SN/A iqMemInstsIssued 2051062SN/A .name(name() + ".iqMemInstsIssued") 2061062SN/A .desc("Number of memory instructions issued") 2071062SN/A .prereq(iqMemInstsIssued); 2081062SN/A 2091062SN/A iqMiscInstsIssued 2101062SN/A .name(name() + ".iqMiscInstsIssued") 2111062SN/A .desc("Number of miscellaneous instructions issued") 2121062SN/A .prereq(iqMiscInstsIssued); 2131062SN/A 2141062SN/A iqSquashedInstsIssued 2151062SN/A .name(name() + ".iqSquashedInstsIssued") 2161062SN/A .desc("Number of squashed instructions issued") 2171062SN/A .prereq(iqSquashedInstsIssued); 2181062SN/A 2191062SN/A iqSquashedInstsExamined 2201062SN/A .name(name() + ".iqSquashedInstsExamined") 2211062SN/A .desc("Number of squashed instructions iterated over during squash;" 2221062SN/A " mainly for profiling") 2231062SN/A .prereq(iqSquashedInstsExamined); 2241062SN/A 2251062SN/A iqSquashedOperandsExamined 2261062SN/A .name(name() + ".iqSquashedOperandsExamined") 2271062SN/A .desc("Number of squashed operands that are examined and possibly " 2281062SN/A "removed from graph") 2291062SN/A .prereq(iqSquashedOperandsExamined); 2301062SN/A 2311062SN/A iqSquashedNonSpecRemoved 2321062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2331062SN/A .desc("Number of squashed non-spec instructions that were removed") 2341062SN/A .prereq(iqSquashedNonSpecRemoved); 2351062SN/A 2362326SN/A queueResDist 2372301SN/A .init(Num_OpClasses, 0, 99, 2) 2382301SN/A .name(name() + ".IQ:residence:") 2392301SN/A .desc("cycles from dispatch to issue") 2402301SN/A .flags(total | pdf | cdf ) 2412301SN/A ; 2422301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2432326SN/A queueResDist.subname(i, opClassStrings[i]); 2442301SN/A } 2452326SN/A numIssuedDist 2462307SN/A .init(0,totalWidth,1) 2472301SN/A .name(name() + ".ISSUE:issued_per_cycle") 2482301SN/A .desc("Number of insts issued each cycle") 2492307SN/A .flags(pdf) 2502301SN/A ; 2512301SN/A/* 2522301SN/A dist_unissued 2532301SN/A .init(Num_OpClasses+2) 2542301SN/A .name(name() + ".ISSUE:unissued_cause") 2552301SN/A .desc("Reason ready instruction not issued") 2562301SN/A .flags(pdf | dist) 2572301SN/A ; 2582301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2592301SN/A dist_unissued.subname(i, unissued_names[i]); 2602301SN/A } 2612301SN/A*/ 2622326SN/A statIssuedInstType 2632301SN/A .init(numThreads,Num_OpClasses) 2642301SN/A .name(name() + ".ISSUE:FU_type") 2652301SN/A .desc("Type of FU issued") 2662301SN/A .flags(total | pdf | dist) 2672301SN/A ; 2682326SN/A statIssuedInstType.ysubnames(opClassStrings); 2692301SN/A 2702301SN/A // 2712301SN/A // How long did instructions for a particular FU type wait prior to issue 2722301SN/A // 2732301SN/A 2742326SN/A issueDelayDist 2752301SN/A .init(Num_OpClasses,0,99,2) 2762301SN/A .name(name() + ".ISSUE:") 2772301SN/A .desc("cycles from operands ready to issue") 2782301SN/A .flags(pdf | cdf) 2792301SN/A ; 2802301SN/A 2812301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2822301SN/A stringstream subname; 2832301SN/A subname << opClassStrings[i] << "_delay"; 2842326SN/A issueDelayDist.subname(i, subname.str()); 2852301SN/A } 2862301SN/A 2872326SN/A issueRate 2882301SN/A .name(name() + ".ISSUE:rate") 2892301SN/A .desc("Inst issue rate") 2902301SN/A .flags(total) 2912301SN/A ; 2922326SN/A issueRate = iqInstsIssued / cpu->numCycles; 2932727Sktlim@umich.edu 2942326SN/A statFuBusy 2952301SN/A .init(Num_OpClasses) 2962301SN/A .name(name() + ".ISSUE:fu_full") 2972301SN/A .desc("attempts to use FU when none available") 2982301SN/A .flags(pdf | dist) 2992301SN/A ; 3002301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3012326SN/A statFuBusy.subname(i, opClassStrings[i]); 3022301SN/A } 3032301SN/A 3042326SN/A fuBusy 3052301SN/A .init(numThreads) 3062301SN/A .name(name() + ".ISSUE:fu_busy_cnt") 3072301SN/A .desc("FU busy when requested") 3082301SN/A .flags(total) 3092301SN/A ; 3102301SN/A 3112326SN/A fuBusyRate 3122301SN/A .name(name() + ".ISSUE:fu_busy_rate") 3132301SN/A .desc("FU busy rate (busy events/executed inst)") 3142301SN/A .flags(total) 3152301SN/A ; 3162326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3172301SN/A 3182292SN/A for ( int i=0; i < numThreads; i++) { 3192292SN/A // Tell mem dependence unit to reg stats as well. 3202292SN/A memDepUnit[i].regStats(); 3212292SN/A } 3221062SN/A} 3231062SN/A 3241062SN/Atemplate <class Impl> 3251062SN/Avoid 3262307SN/AInstructionQueue<Impl>::resetState() 3271060SN/A{ 3282307SN/A //Initialize thread IQ counts 3292307SN/A for (int i = 0; i <numThreads; i++) { 3302307SN/A count[i] = 0; 3312307SN/A instList[i].clear(); 3322307SN/A } 3331060SN/A 3342307SN/A // Initialize the number of free IQ entries. 3352307SN/A freeEntries = numEntries; 3362307SN/A 3372307SN/A // Note that in actuality, the registers corresponding to the logical 3382307SN/A // registers start off as ready. However this doesn't matter for the 3392307SN/A // IQ as the instruction should have been correctly told if those 3402307SN/A // registers are ready in rename. Thus it can all be initialized as 3412307SN/A // unready. 3422307SN/A for (int i = 0; i < numPhysRegs; ++i) { 3432307SN/A regScoreboard[i] = false; 3442307SN/A } 3452307SN/A 3462307SN/A for (int i = 0; i < numThreads; ++i) { 3472307SN/A squashedSeqNum[i] = 0; 3482307SN/A } 3492307SN/A 3502307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 3512307SN/A while (!readyInsts[i].empty()) 3522307SN/A readyInsts[i].pop(); 3532307SN/A queueOnList[i] = false; 3542307SN/A readyIt[i] = listOrder.end(); 3552307SN/A } 3562307SN/A nonSpecInsts.clear(); 3572307SN/A listOrder.clear(); 3581060SN/A} 3591060SN/A 3601061SN/Atemplate <class Impl> 3611060SN/Avoid 3622292SN/AInstructionQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3631060SN/A{ 3642292SN/A DPRINTF(IQ, "Setting active threads list pointer.\n"); 3652292SN/A activeThreads = at_ptr; 3662064SN/A} 3672064SN/A 3682064SN/Atemplate <class Impl> 3692064SN/Avoid 3702292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 3712064SN/A{ 3722292SN/A DPRINTF(IQ, "Set the issue to execute queue.\n"); 3731060SN/A issueToExecuteQueue = i2e_ptr; 3741060SN/A} 3751060SN/A 3761061SN/Atemplate <class Impl> 3771060SN/Avoid 3781060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3791060SN/A{ 3802292SN/A DPRINTF(IQ, "Set the time buffer.\n"); 3811060SN/A timeBuffer = tb_ptr; 3821060SN/A 3831060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3841060SN/A} 3851060SN/A 3861684SN/Atemplate <class Impl> 3872307SN/Avoid 3882307SN/AInstructionQueue<Impl>::switchOut() 3892307SN/A{ 3902307SN/A resetState(); 3912326SN/A dependGraph.reset(); 3922307SN/A switchedOut = true; 3932307SN/A for (int i = 0; i < numThreads; ++i) { 3942307SN/A memDepUnit[i].switchOut(); 3952307SN/A } 3962307SN/A} 3972307SN/A 3982307SN/Atemplate <class Impl> 3992307SN/Avoid 4002307SN/AInstructionQueue<Impl>::takeOverFrom() 4012307SN/A{ 4022307SN/A switchedOut = false; 4032307SN/A} 4042307SN/A 4052307SN/Atemplate <class Impl> 4062292SN/Aint 4072292SN/AInstructionQueue<Impl>::entryAmount(int num_threads) 4082292SN/A{ 4092292SN/A if (iqPolicy == Partitioned) { 4102292SN/A return numEntries / num_threads; 4112292SN/A } else { 4122292SN/A return 0; 4132292SN/A } 4142292SN/A} 4152292SN/A 4162292SN/A 4172292SN/Atemplate <class Impl> 4182292SN/Avoid 4192292SN/AInstructionQueue<Impl>::resetEntries() 4202292SN/A{ 4212292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4222292SN/A int active_threads = (*activeThreads).size(); 4232292SN/A 4242292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4252292SN/A list<unsigned>::iterator list_end = (*activeThreads).end(); 4262292SN/A 4272292SN/A while (threads != list_end) { 4282292SN/A if (iqPolicy == Partitioned) { 4292292SN/A maxEntries[*threads++] = numEntries / active_threads; 4302292SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4312292SN/A maxEntries[*threads++] = numEntries; 4322292SN/A } 4332292SN/A } 4342292SN/A } 4352292SN/A} 4362292SN/A 4372292SN/Atemplate <class Impl> 4381684SN/Aunsigned 4391684SN/AInstructionQueue<Impl>::numFreeEntries() 4401684SN/A{ 4411684SN/A return freeEntries; 4421684SN/A} 4431684SN/A 4442292SN/Atemplate <class Impl> 4452292SN/Aunsigned 4462292SN/AInstructionQueue<Impl>::numFreeEntries(unsigned tid) 4472292SN/A{ 4482292SN/A return maxEntries[tid] - count[tid]; 4492292SN/A} 4502292SN/A 4511060SN/A// Might want to do something more complex if it knows how many instructions 4521060SN/A// will be issued this cycle. 4531061SN/Atemplate <class Impl> 4541060SN/Abool 4551060SN/AInstructionQueue<Impl>::isFull() 4561060SN/A{ 4571060SN/A if (freeEntries == 0) { 4581060SN/A return(true); 4591060SN/A } else { 4601060SN/A return(false); 4611060SN/A } 4621060SN/A} 4631060SN/A 4641061SN/Atemplate <class Impl> 4652292SN/Abool 4662292SN/AInstructionQueue<Impl>::isFull(unsigned tid) 4672292SN/A{ 4682292SN/A if (numFreeEntries(tid) == 0) { 4692292SN/A return(true); 4702292SN/A } else { 4712292SN/A return(false); 4722292SN/A } 4732292SN/A} 4742292SN/A 4752292SN/Atemplate <class Impl> 4762292SN/Abool 4772292SN/AInstructionQueue<Impl>::hasReadyInsts() 4782292SN/A{ 4792292SN/A if (!listOrder.empty()) { 4802292SN/A return true; 4812292SN/A } 4822292SN/A 4832292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4842292SN/A if (!readyInsts[i].empty()) { 4852292SN/A return true; 4862292SN/A } 4872292SN/A } 4882292SN/A 4892292SN/A return false; 4902292SN/A} 4912292SN/A 4922292SN/Atemplate <class Impl> 4931060SN/Avoid 4941061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 4951060SN/A{ 4961060SN/A // Make sure the instruction is valid 4971060SN/A assert(new_inst); 4981060SN/A 4992326SN/A DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n", 5002326SN/A new_inst->seqNum, new_inst->readPC()); 5011060SN/A 5021060SN/A assert(freeEntries != 0); 5031060SN/A 5042292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5051060SN/A 5062064SN/A --freeEntries; 5071060SN/A 5082292SN/A new_inst->setInIQ(); 5091060SN/A 5101060SN/A // Look through its source registers (physical regs), and mark any 5111060SN/A // dependencies. 5121060SN/A addToDependents(new_inst); 5131060SN/A 5141060SN/A // Have this instruction set itself as the producer of its destination 5151060SN/A // register(s). 5162326SN/A addToProducers(new_inst); 5171060SN/A 5181061SN/A if (new_inst->isMemRef()) { 5192292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5201062SN/A } else { 5211062SN/A addIfReady(new_inst); 5221061SN/A } 5231061SN/A 5241062SN/A ++iqInstsAdded; 5251060SN/A 5262292SN/A count[new_inst->threadNumber]++; 5272292SN/A 5281060SN/A assert(freeEntries == (numEntries - countInsts())); 5291060SN/A} 5301060SN/A 5311061SN/Atemplate <class Impl> 5321061SN/Avoid 5332292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5341061SN/A{ 5351061SN/A // @todo: Clean up this code; can do it by setting inst as unable 5361061SN/A // to issue, then calling normal insert on the inst. 5371061SN/A 5382292SN/A assert(new_inst); 5391061SN/A 5402292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 5411061SN/A 5422326SN/A DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x " 5432326SN/A "to the IQ.\n", 5442326SN/A new_inst->seqNum, new_inst->readPC()); 5452064SN/A 5461061SN/A assert(freeEntries != 0); 5471061SN/A 5482292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5491061SN/A 5502064SN/A --freeEntries; 5511061SN/A 5522292SN/A new_inst->setInIQ(); 5531061SN/A 5541061SN/A // Have this instruction set itself as the producer of its destination 5551061SN/A // register(s). 5562326SN/A addToProducers(new_inst); 5571061SN/A 5581061SN/A // If it's a memory instruction, add it to the memory dependency 5591061SN/A // unit. 5602292SN/A if (new_inst->isMemRef()) { 5612292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 5621061SN/A } 5631062SN/A 5641062SN/A ++iqNonSpecInstsAdded; 5652292SN/A 5662292SN/A count[new_inst->threadNumber]++; 5672292SN/A 5682292SN/A assert(freeEntries == (numEntries - countInsts())); 5691061SN/A} 5701061SN/A 5711061SN/Atemplate <class Impl> 5721060SN/Avoid 5732292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 5741060SN/A{ 5752292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 5761060SN/A 5772292SN/A insertNonSpec(barr_inst); 5782292SN/A} 5791060SN/A 5802064SN/Atemplate <class Impl> 5812333SN/Atypename Impl::DynInstPtr 5822333SN/AInstructionQueue<Impl>::getInstToExecute() 5832333SN/A{ 5842333SN/A assert(!instsToExecute.empty()); 5852333SN/A DynInstPtr inst = instsToExecute.front(); 5862333SN/A instsToExecute.pop_front(); 5872333SN/A return inst; 5882333SN/A} 5891060SN/A 5902333SN/Atemplate <class Impl> 5912064SN/Avoid 5922292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 5932292SN/A{ 5942292SN/A assert(!readyInsts[op_class].empty()); 5952292SN/A 5962292SN/A ListOrderEntry queue_entry; 5972292SN/A 5982292SN/A queue_entry.queueType = op_class; 5992292SN/A 6002292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6012292SN/A 6022292SN/A ListOrderIt list_it = listOrder.begin(); 6032292SN/A ListOrderIt list_end_it = listOrder.end(); 6042292SN/A 6052292SN/A while (list_it != list_end_it) { 6062292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6072292SN/A break; 6082292SN/A } 6092292SN/A 6102292SN/A list_it++; 6111060SN/A } 6121060SN/A 6132292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6142292SN/A queueOnList[op_class] = true; 6152292SN/A} 6161060SN/A 6172292SN/Atemplate <class Impl> 6182292SN/Avoid 6192292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6202292SN/A{ 6212292SN/A // Get iterator of next item on the list 6222292SN/A // Delete the original iterator 6232292SN/A // Determine if the next item is either the end of the list or younger 6242292SN/A // than the new instruction. If so, then add in a new iterator right here. 6252292SN/A // If not, then move along. 6262292SN/A ListOrderEntry queue_entry; 6272292SN/A OpClass op_class = (*list_order_it).queueType; 6282292SN/A ListOrderIt next_it = list_order_it; 6292292SN/A 6302292SN/A ++next_it; 6312292SN/A 6322292SN/A queue_entry.queueType = op_class; 6332292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6342292SN/A 6352292SN/A while (next_it != listOrder.end() && 6362292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 6372292SN/A ++next_it; 6381060SN/A } 6391060SN/A 6402292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 6411060SN/A} 6421060SN/A 6432292SN/Atemplate <class Impl> 6442292SN/Avoid 6452292SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 6462292SN/A{ 6472292SN/A // The CPU could have been sleeping until this op completed (*extremely* 6482292SN/A // long latency op). Wake it if it was. This may be overkill. 6492307SN/A if (isSwitchedOut()) { 6502307SN/A return; 6512307SN/A } 6522307SN/A 6532292SN/A iewStage->wakeCPU(); 6542292SN/A 6552326SN/A if (fu_idx > -1) 6562326SN/A fuPool->freeUnitNextCycle(fu_idx); 6572292SN/A 6582326SN/A // @todo: Ensure that these FU Completions happen at the beginning 6592326SN/A // of a cycle, otherwise they could add too many instructions to 6602326SN/A // the queue. 6612333SN/A issueToExecuteQueue->access(0)->size++; 6622333SN/A instsToExecute.push_back(inst); 6632292SN/A} 6642292SN/A 6651061SN/A// @todo: Figure out a better way to remove the squashed items from the 6661061SN/A// lists. Checking the top item of each list to see if it's squashed 6671061SN/A// wastes time and forces jumps. 6681061SN/Atemplate <class Impl> 6691060SN/Avoid 6701060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 6711060SN/A{ 6722292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 6732292SN/A "the IQ.\n"); 6741060SN/A 6751060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 6761060SN/A 6772292SN/A // Have iterator to head of the list 6782292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 6792292SN/A // Try to get a FU that can do what this op needs. 6802292SN/A // If successful, change the oldestInst to the new top of the list, put 6812292SN/A // the queue in the proper place in the list. 6822292SN/A // Increment the iterator. 6832292SN/A // This will avoid trying to schedule a certain op class if there are no 6842292SN/A // FUs that handle it. 6852292SN/A ListOrderIt order_it = listOrder.begin(); 6862292SN/A ListOrderIt order_end_it = listOrder.end(); 6872292SN/A int total_issued = 0; 6881060SN/A 6892333SN/A while (total_issued < totalWidth && 6902820Sktlim@umich.edu iewStage->canIssue() && 6912326SN/A order_it != order_end_it) { 6922292SN/A OpClass op_class = (*order_it).queueType; 6931060SN/A 6942292SN/A assert(!readyInsts[op_class].empty()); 6951060SN/A 6962292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 6971060SN/A 6982292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 6991060SN/A 7002292SN/A if (issuing_inst->isSquashed()) { 7012292SN/A readyInsts[op_class].pop(); 7021060SN/A 7032292SN/A if (!readyInsts[op_class].empty()) { 7042292SN/A moveToYoungerInst(order_it); 7052292SN/A } else { 7062292SN/A readyIt[op_class] = listOrder.end(); 7072292SN/A queueOnList[op_class] = false; 7081060SN/A } 7091060SN/A 7102292SN/A listOrder.erase(order_it++); 7111060SN/A 7122292SN/A ++iqSquashedInstsIssued; 7132292SN/A 7142292SN/A continue; 7151060SN/A } 7161060SN/A 7172326SN/A int idx = -2; 7182326SN/A int op_latency = 1; 7192301SN/A int tid = issuing_inst->threadNumber; 7201060SN/A 7212326SN/A if (op_class != No_OpClass) { 7222326SN/A idx = fuPool->getUnit(op_class); 7231060SN/A 7242326SN/A if (idx > -1) { 7252326SN/A op_latency = fuPool->getOpLatency(op_class); 7261060SN/A } 7271060SN/A } 7281060SN/A 7292348SN/A // If we have an instruction that doesn't require a FU, or a 7302348SN/A // valid FU, then schedule for execution. 7312326SN/A if (idx == -2 || idx != -1) { 7322292SN/A if (op_latency == 1) { 7332292SN/A i2e_info->size++; 7342333SN/A instsToExecute.push_back(issuing_inst); 7351060SN/A 7362326SN/A // Add the FU onto the list of FU's to be freed next 7372326SN/A // cycle if we used one. 7382326SN/A if (idx >= 0) 7392326SN/A fuPool->freeUnitNextCycle(idx); 7402292SN/A } else { 7412292SN/A int issue_latency = fuPool->getIssueLatency(op_class); 7422326SN/A // Generate completion event for the FU 7432326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 7442326SN/A idx, this); 7451060SN/A 7462326SN/A execution->schedule(curTick + cpu->cycles(issue_latency - 1)); 7471060SN/A 7482326SN/A // @todo: Enforce that issue_latency == 1 or op_latency 7492292SN/A if (issue_latency > 1) { 7502348SN/A // If FU isn't pipelined, then it must be freed 7512348SN/A // upon the execution completing. 7522326SN/A execution->setFreeFU(); 7532292SN/A } else { 7542292SN/A // Add the FU onto the list of FU's to be freed next cycle. 7552326SN/A fuPool->freeUnitNextCycle(idx); 7562292SN/A } 7571060SN/A } 7581060SN/A 7592292SN/A DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x " 7602292SN/A "[sn:%lli]\n", 7612301SN/A tid, issuing_inst->readPC(), 7622292SN/A issuing_inst->seqNum); 7631060SN/A 7642292SN/A readyInsts[op_class].pop(); 7651061SN/A 7662292SN/A if (!readyInsts[op_class].empty()) { 7672292SN/A moveToYoungerInst(order_it); 7682292SN/A } else { 7692292SN/A readyIt[op_class] = listOrder.end(); 7702292SN/A queueOnList[op_class] = false; 7711060SN/A } 7721060SN/A 7732064SN/A issuing_inst->setIssued(); 7742292SN/A ++total_issued; 7752064SN/A 7762292SN/A if (!issuing_inst->isMemRef()) { 7772292SN/A // Memory instructions can not be freed from the IQ until they 7782292SN/A // complete. 7792292SN/A ++freeEntries; 7802301SN/A count[tid]--; 7812731Sktlim@umich.edu issuing_inst->clearInIQ(); 7822292SN/A } else { 7832301SN/A memDepUnit[tid].issue(issuing_inst); 7842292SN/A } 7852292SN/A 7862292SN/A listOrder.erase(order_it++); 7872326SN/A statIssuedInstType[tid][op_class]++; 7882820Sktlim@umich.edu iewStage->incrWb(issuing_inst->seqNum); 7892292SN/A } else { 7902326SN/A statFuBusy[op_class]++; 7912326SN/A fuBusy[tid]++; 7922292SN/A ++order_it; 7931060SN/A } 7941060SN/A } 7951062SN/A 7962326SN/A numIssuedDist.sample(total_issued); 7972326SN/A iqInstsIssued+= total_issued; 7982307SN/A 7992348SN/A // If we issued any instructions, tell the CPU we had activity. 8002292SN/A if (total_issued) { 8012292SN/A cpu->activityThisCycle(); 8022292SN/A } else { 8032292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8042292SN/A } 8051060SN/A} 8061060SN/A 8071061SN/Atemplate <class Impl> 8081060SN/Avoid 8091061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 8101060SN/A{ 8112292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 8122292SN/A "to execute.\n", inst); 8131062SN/A 8142292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 8151060SN/A 8161061SN/A assert(inst_it != nonSpecInsts.end()); 8171060SN/A 8182292SN/A unsigned tid = (*inst_it).second->threadNumber; 8192292SN/A 8201061SN/A (*inst_it).second->setCanIssue(); 8211060SN/A 8221062SN/A if (!(*inst_it).second->isMemRef()) { 8231062SN/A addIfReady((*inst_it).second); 8241062SN/A } else { 8252292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 8261062SN/A } 8271060SN/A 8282292SN/A (*inst_it).second = NULL; 8292292SN/A 8301061SN/A nonSpecInsts.erase(inst_it); 8311060SN/A} 8321060SN/A 8331061SN/Atemplate <class Impl> 8341061SN/Avoid 8352292SN/AInstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid) 8362292SN/A{ 8372292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 8382292SN/A tid,inst); 8392292SN/A 8402292SN/A ListIt iq_it = instList[tid].begin(); 8412292SN/A 8422292SN/A while (iq_it != instList[tid].end() && 8432292SN/A (*iq_it)->seqNum <= inst) { 8442292SN/A ++iq_it; 8452292SN/A instList[tid].pop_front(); 8462292SN/A } 8472292SN/A 8482292SN/A assert(freeEntries == (numEntries - countInsts())); 8492292SN/A} 8502292SN/A 8512292SN/Atemplate <class Impl> 8522301SN/Aint 8531684SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 8541684SN/A{ 8552301SN/A int dependents = 0; 8562301SN/A 8572292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 8582292SN/A 8592292SN/A assert(!completed_inst->isSquashed()); 8601684SN/A 8611684SN/A // Tell the memory dependence unit to wake any dependents on this 8622292SN/A // instruction if it is a memory instruction. Also complete the memory 8632326SN/A // instruction at this point since we know it executed without issues. 8642326SN/A // @todo: Might want to rename "completeMemInst" to something that 8652326SN/A // indicates that it won't need to be replayed, and call this 8662326SN/A // earlier. Might not be a big deal. 8671684SN/A if (completed_inst->isMemRef()) { 8682292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 8692292SN/A completeMemInst(completed_inst); 8702292SN/A } else if (completed_inst->isMemBarrier() || 8712292SN/A completed_inst->isWriteBarrier()) { 8722292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 8731684SN/A } 8741684SN/A 8751684SN/A for (int dest_reg_idx = 0; 8761684SN/A dest_reg_idx < completed_inst->numDestRegs(); 8771684SN/A dest_reg_idx++) 8781684SN/A { 8791684SN/A PhysRegIndex dest_reg = 8801684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 8811684SN/A 8821684SN/A // Special case of uniq or control registers. They are not 8831684SN/A // handled by the IQ and thus have no dependency graph entry. 8841684SN/A // @todo Figure out a cleaner way to handle this. 8851684SN/A if (dest_reg >= numPhysRegs) { 8861684SN/A continue; 8871684SN/A } 8881684SN/A 8892292SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 8901684SN/A (int) dest_reg); 8911684SN/A 8922326SN/A //Go through the dependency chain, marking the registers as 8932326SN/A //ready within the waiting instructions. 8942326SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg); 8951684SN/A 8962326SN/A while (dep_inst) { 8972292SN/A DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n", 8982326SN/A dep_inst->readPC()); 8991684SN/A 9001684SN/A // Might want to give more information to the instruction 9012326SN/A // so that it knows which of its source registers is 9022326SN/A // ready. However that would mean that the dependency 9032326SN/A // graph entries would need to hold the src_reg_idx. 9042326SN/A dep_inst->markSrcRegReady(); 9051684SN/A 9062326SN/A addIfReady(dep_inst); 9071684SN/A 9082326SN/A dep_inst = dependGraph.pop(dest_reg); 9091684SN/A 9102301SN/A ++dependents; 9111684SN/A } 9121684SN/A 9132326SN/A // Reset the head node now that all of its dependents have 9142326SN/A // been woken up. 9152326SN/A assert(dependGraph.empty(dest_reg)); 9162326SN/A dependGraph.clearInst(dest_reg); 9171684SN/A 9181684SN/A // Mark the scoreboard as having that register ready. 9191684SN/A regScoreboard[dest_reg] = true; 9201684SN/A } 9212301SN/A return dependents; 9222064SN/A} 9232064SN/A 9242064SN/Atemplate <class Impl> 9252064SN/Avoid 9262292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 9272064SN/A{ 9282292SN/A OpClass op_class = ready_inst->opClass(); 9292292SN/A 9302292SN/A readyInsts[op_class].push(ready_inst); 9312292SN/A 9322326SN/A // Will need to reorder the list if either a queue is not on the list, 9332326SN/A // or it has an older instruction than last time. 9342326SN/A if (!queueOnList[op_class]) { 9352326SN/A addToOrderList(op_class); 9362326SN/A } else if (readyInsts[op_class].top()->seqNum < 9372326SN/A (*readyIt[op_class]).oldestInst) { 9382326SN/A listOrder.erase(readyIt[op_class]); 9392326SN/A addToOrderList(op_class); 9402326SN/A } 9412326SN/A 9422292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 9432292SN/A "the ready list, PC %#x opclass:%i [sn:%lli].\n", 9442292SN/A ready_inst->readPC(), op_class, ready_inst->seqNum); 9452064SN/A} 9462064SN/A 9472064SN/Atemplate <class Impl> 9482064SN/Avoid 9492292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 9502064SN/A{ 9512292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 9522064SN/A} 9532064SN/A 9542064SN/Atemplate <class Impl> 9552064SN/Avoid 9562292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 9572064SN/A{ 9582292SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 9592292SN/A} 9602292SN/A 9612292SN/Atemplate <class Impl> 9622292SN/Avoid 9632292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 9642292SN/A{ 9652292SN/A int tid = completed_inst->threadNumber; 9662292SN/A 9672292SN/A DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n", 9682292SN/A completed_inst->readPC(), completed_inst->seqNum); 9692292SN/A 9702292SN/A ++freeEntries; 9712292SN/A 9722292SN/A completed_inst->memOpDone = true; 9732292SN/A 9742292SN/A memDepUnit[tid].completed(completed_inst); 9752292SN/A 9762292SN/A count[tid]--; 9771684SN/A} 9781684SN/A 9791684SN/Atemplate <class Impl> 9801684SN/Avoid 9811061SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 9821061SN/A DynInstPtr &faulting_load) 9831061SN/A{ 9842292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 9851061SN/A} 9861061SN/A 9871061SN/Atemplate <class Impl> 9881060SN/Avoid 9892292SN/AInstructionQueue<Impl>::squash(unsigned tid) 9901060SN/A{ 9912292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 9922292SN/A "the IQ.\n", tid); 9931060SN/A 9941060SN/A // Read instruction sequence number of last instruction out of the 9951060SN/A // time buffer. 9962935Sksewell@umich.edu#if THE_ISA == ALPHA_ISA 9972292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 9982935Sksewell@umich.edu#else 9992935Sksewell@umich.edu squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 10002935Sksewell@umich.edu#endif 10011060SN/A 10021681SN/A // Call doSquash if there are insts in the IQ 10032292SN/A if (count[tid] > 0) { 10042292SN/A doSquash(tid); 10051681SN/A } 10061061SN/A 10071061SN/A // Also tell the memory dependence unit to squash. 10082292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 10091060SN/A} 10101060SN/A 10111061SN/Atemplate <class Impl> 10121061SN/Avoid 10132292SN/AInstructionQueue<Impl>::doSquash(unsigned tid) 10141061SN/A{ 10152326SN/A // Start at the tail. 10162326SN/A ListIt squash_it = instList[tid].end(); 10172326SN/A --squash_it; 10181061SN/A 10192292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 10202292SN/A tid, squashedSeqNum[tid]); 10211061SN/A 10221061SN/A // Squash any instructions younger than the squashed sequence number 10231061SN/A // given. 10242326SN/A while (squash_it != instList[tid].end() && 10252326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 10262292SN/A 10272326SN/A DynInstPtr squashed_inst = (*squash_it); 10281061SN/A 10291061SN/A // Only handle the instruction if it actually is in the IQ and 10301061SN/A // hasn't already been squashed in the IQ. 10312292SN/A if (squashed_inst->threadNumber != tid || 10322292SN/A squashed_inst->isSquashedInIQ()) { 10332326SN/A --squash_it; 10342292SN/A continue; 10352292SN/A } 10362292SN/A 10372292SN/A if (!squashed_inst->isIssued() || 10382292SN/A (squashed_inst->isMemRef() && 10392292SN/A !squashed_inst->memOpDone)) { 10401062SN/A 10411061SN/A // Remove the instruction from the dependency list. 10422292SN/A if (!squashed_inst->isNonSpeculative() && 10432336SN/A !squashed_inst->isStoreConditional() && 10442292SN/A !squashed_inst->isMemBarrier() && 10452292SN/A !squashed_inst->isWriteBarrier()) { 10461061SN/A 10471061SN/A for (int src_reg_idx = 0; 10481681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 10491061SN/A src_reg_idx++) 10501061SN/A { 10511061SN/A PhysRegIndex src_reg = 10521061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 10531061SN/A 10542326SN/A // Only remove it from the dependency graph if it 10552326SN/A // was placed there in the first place. 10562326SN/A 10572326SN/A // Instead of doing a linked list traversal, we 10582326SN/A // can just remove these squashed instructions 10592326SN/A // either at issue time, or when the register is 10602326SN/A // overwritten. The only downside to this is it 10612326SN/A // leaves more room for error. 10622292SN/A 10631061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 10641061SN/A src_reg < numPhysRegs) { 10652326SN/A dependGraph.remove(src_reg, squashed_inst); 10661061SN/A } 10671062SN/A 10682292SN/A 10691062SN/A ++iqSquashedOperandsExamined; 10701061SN/A } 10712064SN/A } else { 10722292SN/A NonSpecMapIt ns_inst_it = 10732292SN/A nonSpecInsts.find(squashed_inst->seqNum); 10742292SN/A assert(ns_inst_it != nonSpecInsts.end()); 10751062SN/A 10762292SN/A (*ns_inst_it).second = NULL; 10771681SN/A 10782292SN/A nonSpecInsts.erase(ns_inst_it); 10791062SN/A 10801062SN/A ++iqSquashedNonSpecRemoved; 10811061SN/A } 10821061SN/A 10831061SN/A // Might want to also clear out the head of the dependency graph. 10841061SN/A 10851061SN/A // Mark it as squashed within the IQ. 10861061SN/A squashed_inst->setSquashedInIQ(); 10871061SN/A 10882292SN/A // @todo: Remove this hack where several statuses are set so the 10892292SN/A // inst will flow through the rest of the pipeline. 10901681SN/A squashed_inst->setIssued(); 10911681SN/A squashed_inst->setCanCommit(); 10922731Sktlim@umich.edu squashed_inst->clearInIQ(); 10932292SN/A 10942292SN/A //Update Thread IQ Count 10952292SN/A count[squashed_inst->threadNumber]--; 10961681SN/A 10971681SN/A ++freeEntries; 10981061SN/A 10992326SN/A DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x " 11002326SN/A "squashed.\n", 11012326SN/A tid, squashed_inst->seqNum, squashed_inst->readPC()); 11021061SN/A } 11031061SN/A 11042326SN/A instList[tid].erase(squash_it--); 11051062SN/A ++iqSquashedInstsExamined; 11061061SN/A } 11071060SN/A} 11081060SN/A 11091061SN/Atemplate <class Impl> 11101060SN/Abool 11111061SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 11121060SN/A{ 11131060SN/A // Loop through the instruction's source registers, adding 11141060SN/A // them to the dependency list if they are not ready. 11151060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 11161060SN/A bool return_val = false; 11171060SN/A 11181060SN/A for (int src_reg_idx = 0; 11191060SN/A src_reg_idx < total_src_regs; 11201060SN/A src_reg_idx++) 11211060SN/A { 11221060SN/A // Only add it to the dependency graph if it's not ready. 11231060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 11241060SN/A PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 11251060SN/A 11261060SN/A // Check the IQ's scoreboard to make sure the register 11271060SN/A // hasn't become ready while the instruction was in flight 11281060SN/A // between stages. Only if it really isn't ready should 11291060SN/A // it be added to the dependency graph. 11301061SN/A if (src_reg >= numPhysRegs) { 11311061SN/A continue; 11321061SN/A } else if (regScoreboard[src_reg] == false) { 11332292SN/A DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 11341060SN/A "is being added to the dependency chain.\n", 11351060SN/A new_inst->readPC(), src_reg); 11361060SN/A 11372326SN/A dependGraph.insert(src_reg, new_inst); 11381060SN/A 11391060SN/A // Change the return value to indicate that something 11401060SN/A // was added to the dependency graph. 11411060SN/A return_val = true; 11421060SN/A } else { 11432292SN/A DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 11441060SN/A "became ready before it reached the IQ.\n", 11451060SN/A new_inst->readPC(), src_reg); 11461060SN/A // Mark a register ready within the instruction. 11472326SN/A new_inst->markSrcRegReady(src_reg_idx); 11481060SN/A } 11491060SN/A } 11501060SN/A } 11511060SN/A 11521060SN/A return return_val; 11531060SN/A} 11541060SN/A 11551061SN/Atemplate <class Impl> 11561060SN/Avoid 11572326SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 11581060SN/A{ 11592326SN/A // Nothing really needs to be marked when an instruction becomes 11602326SN/A // the producer of a register's value, but for convenience a ptr 11612326SN/A // to the producing instruction will be placed in the head node of 11622326SN/A // the dependency links. 11631060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 11641060SN/A 11651060SN/A for (int dest_reg_idx = 0; 11661060SN/A dest_reg_idx < total_dest_regs; 11671060SN/A dest_reg_idx++) 11681060SN/A { 11691061SN/A PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 11701061SN/A 11711061SN/A // Instructions that use the misc regs will have a reg number 11721061SN/A // higher than the normal physical registers. In this case these 11731061SN/A // registers are not renamed, and there is no need to track 11741061SN/A // dependencies as these instructions must be executed at commit. 11751061SN/A if (dest_reg >= numPhysRegs) { 11761061SN/A continue; 11771060SN/A } 11781060SN/A 11792326SN/A if (!dependGraph.empty(dest_reg)) { 11802326SN/A dependGraph.dump(); 11812292SN/A panic("Dependency graph %i not empty!", dest_reg); 11822064SN/A } 11831062SN/A 11842326SN/A dependGraph.setInst(dest_reg, new_inst); 11851062SN/A 11861060SN/A // Mark the scoreboard to say it's not yet ready. 11871060SN/A regScoreboard[dest_reg] = false; 11881060SN/A } 11891060SN/A} 11901060SN/A 11911061SN/Atemplate <class Impl> 11921060SN/Avoid 11931061SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 11941060SN/A{ 11952326SN/A // If the instruction now has all of its source registers 11961060SN/A // available, then add it to the list of ready instructions. 11971060SN/A if (inst->readyToIssue()) { 11981061SN/A 11991060SN/A //Add the instruction to the proper ready list. 12002292SN/A if (inst->isMemRef()) { 12011061SN/A 12022292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 12031061SN/A 12041062SN/A // Message to the mem dependence unit that this instruction has 12051062SN/A // its registers ready. 12062292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 12071062SN/A 12082292SN/A return; 12092292SN/A } 12101062SN/A 12112292SN/A OpClass op_class = inst->opClass(); 12121061SN/A 12132292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 12142292SN/A "the ready list, PC %#x opclass:%i [sn:%lli].\n", 12152292SN/A inst->readPC(), op_class, inst->seqNum); 12161061SN/A 12172292SN/A readyInsts[op_class].push(inst); 12181061SN/A 12192326SN/A // Will need to reorder the list if either a queue is not on the list, 12202326SN/A // or it has an older instruction than last time. 12212326SN/A if (!queueOnList[op_class]) { 12222326SN/A addToOrderList(op_class); 12232326SN/A } else if (readyInsts[op_class].top()->seqNum < 12242326SN/A (*readyIt[op_class]).oldestInst) { 12252326SN/A listOrder.erase(readyIt[op_class]); 12262326SN/A addToOrderList(op_class); 12271060SN/A } 12281060SN/A } 12291060SN/A} 12301060SN/A 12311061SN/Atemplate <class Impl> 12321061SN/Aint 12331061SN/AInstructionQueue<Impl>::countInsts() 12341061SN/A{ 12352698Sktlim@umich.edu#if 0 12362292SN/A //ksewell:This works but definitely could use a cleaner write 12372292SN/A //with a more intuitive way of counting. Right now it's 12382292SN/A //just brute force .... 12392698Sktlim@umich.edu // Change the #if if you want to use this method. 12401061SN/A int total_insts = 0; 12411061SN/A 12422292SN/A for (int i = 0; i < numThreads; ++i) { 12432292SN/A ListIt count_it = instList[i].begin(); 12441681SN/A 12452292SN/A while (count_it != instList[i].end()) { 12462292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 12472292SN/A if (!(*count_it)->isIssued()) { 12482292SN/A ++total_insts; 12492292SN/A } else if ((*count_it)->isMemRef() && 12502292SN/A !(*count_it)->memOpDone) { 12512292SN/A // Loads that have not been marked as executed still count 12522292SN/A // towards the total instructions. 12532292SN/A ++total_insts; 12542292SN/A } 12552292SN/A } 12562292SN/A 12572292SN/A ++count_it; 12581061SN/A } 12591061SN/A } 12601061SN/A 12611061SN/A return total_insts; 12622292SN/A#else 12632292SN/A return numEntries - freeEntries; 12642292SN/A#endif 12651681SN/A} 12661681SN/A 12671681SN/Atemplate <class Impl> 12681681SN/Avoid 12691061SN/AInstructionQueue<Impl>::dumpLists() 12701061SN/A{ 12712292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 12722292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 12731061SN/A 12742292SN/A cprintf("\n"); 12752292SN/A } 12761061SN/A 12771061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 12781061SN/A 12792292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 12802292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 12811061SN/A 12821061SN/A cprintf("Non speculative list: "); 12831061SN/A 12842292SN/A while (non_spec_it != non_spec_end_it) { 12852292SN/A cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(), 12862292SN/A (*non_spec_it).second->seqNum); 12871061SN/A ++non_spec_it; 12881061SN/A } 12891061SN/A 12901061SN/A cprintf("\n"); 12911061SN/A 12922292SN/A ListOrderIt list_order_it = listOrder.begin(); 12932292SN/A ListOrderIt list_order_end_it = listOrder.end(); 12942292SN/A int i = 1; 12952292SN/A 12962292SN/A cprintf("List order: "); 12972292SN/A 12982292SN/A while (list_order_it != list_order_end_it) { 12992292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 13002292SN/A (*list_order_it).oldestInst); 13012292SN/A 13022292SN/A ++list_order_it; 13032292SN/A ++i; 13042292SN/A } 13052292SN/A 13062292SN/A cprintf("\n"); 13071061SN/A} 13082292SN/A 13092292SN/A 13102292SN/Atemplate <class Impl> 13112292SN/Avoid 13122292SN/AInstructionQueue<Impl>::dumpInsts() 13132292SN/A{ 13142292SN/A for (int i = 0; i < numThreads; ++i) { 13152292SN/A int num = 0; 13162292SN/A int valid_num = 0; 13172292SN/A ListIt inst_list_it = instList[i].begin(); 13182292SN/A 13192292SN/A while (inst_list_it != instList[i].end()) 13202292SN/A { 13212292SN/A cprintf("Instruction:%i\n", 13222292SN/A num); 13232292SN/A if (!(*inst_list_it)->isSquashed()) { 13242292SN/A if (!(*inst_list_it)->isIssued()) { 13252292SN/A ++valid_num; 13262292SN/A cprintf("Count:%i\n", valid_num); 13272292SN/A } else if ((*inst_list_it)->isMemRef() && 13282292SN/A !(*inst_list_it)->memOpDone) { 13292326SN/A // Loads that have not been marked as executed 13302326SN/A // still count towards the total instructions. 13312292SN/A ++valid_num; 13322292SN/A cprintf("Count:%i\n", valid_num); 13332292SN/A } 13342292SN/A } 13352292SN/A 13362292SN/A cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 13372292SN/A "Issued:%i\nSquashed:%i\n", 13382292SN/A (*inst_list_it)->readPC(), 13392292SN/A (*inst_list_it)->seqNum, 13402292SN/A (*inst_list_it)->threadNumber, 13412292SN/A (*inst_list_it)->isIssued(), 13422292SN/A (*inst_list_it)->isSquashed()); 13432292SN/A 13442292SN/A if ((*inst_list_it)->isMemRef()) { 13452292SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 13462292SN/A } 13472292SN/A 13482292SN/A cprintf("\n"); 13492292SN/A 13502292SN/A inst_list_it++; 13512292SN/A ++num; 13522292SN/A } 13532292SN/A } 13542348SN/A 13552348SN/A cprintf("Insts to Execute list:\n"); 13562348SN/A 13572348SN/A int num = 0; 13582348SN/A int valid_num = 0; 13592348SN/A ListIt inst_list_it = instsToExecute.begin(); 13602348SN/A 13612348SN/A while (inst_list_it != instsToExecute.end()) 13622348SN/A { 13632348SN/A cprintf("Instruction:%i\n", 13642348SN/A num); 13652348SN/A if (!(*inst_list_it)->isSquashed()) { 13662348SN/A if (!(*inst_list_it)->isIssued()) { 13672348SN/A ++valid_num; 13682348SN/A cprintf("Count:%i\n", valid_num); 13692348SN/A } else if ((*inst_list_it)->isMemRef() && 13702348SN/A !(*inst_list_it)->memOpDone) { 13712348SN/A // Loads that have not been marked as executed 13722348SN/A // still count towards the total instructions. 13732348SN/A ++valid_num; 13742348SN/A cprintf("Count:%i\n", valid_num); 13752348SN/A } 13762348SN/A } 13772348SN/A 13782348SN/A cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 13792348SN/A "Issued:%i\nSquashed:%i\n", 13802348SN/A (*inst_list_it)->readPC(), 13812348SN/A (*inst_list_it)->seqNum, 13822348SN/A (*inst_list_it)->threadNumber, 13832348SN/A (*inst_list_it)->isIssued(), 13842348SN/A (*inst_list_it)->isSquashed()); 13852348SN/A 13862348SN/A if ((*inst_list_it)->isMemRef()) { 13872348SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 13882348SN/A } 13892348SN/A 13902348SN/A cprintf("\n"); 13912348SN/A 13922348SN/A inst_list_it++; 13932348SN/A ++num; 13942348SN/A } 13952292SN/A} 1396