inst_queue_impl.hh revision 12110
11689SN/A/* 210333Smitch.hayenga@arm.com * Copyright (c) 2011-2014 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422831Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_INST_QUEUE_IMPL_HH__ 479944Smatt.horsnell@ARM.com 482064SN/A#include <limits> 491060SN/A#include <vector> 501060SN/A 512292SN/A#include "cpu/o3/fu_pool.hh" 521717SN/A#include "cpu/o3/inst_queue.hh" 538232Snate@binkert.org#include "debug/IQ.hh" 544762Snate@binkert.org#include "enums/OpClass.hh" 556221Snate@binkert.org#include "params/DerivO3CPU.hh" 564762Snate@binkert.org#include "sim/core.hh" 571060SN/A 588737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 598737Skoansin.tan@gmail.com// we open up the entire namespace std 608737Skoansin.tan@gmail.comusing std::list; 615529Snate@binkert.org 621061SN/Atemplate <class Impl> 632292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 645606Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 658581Ssteve.reinhardt@amd.com : Event(Stat_Event_Pri, AutoDelete), 668581Ssteve.reinhardt@amd.com inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 671060SN/A{ 682292SN/A} 692292SN/A 702292SN/Atemplate <class Impl> 712292SN/Avoid 722292SN/AInstructionQueue<Impl>::FUCompletion::process() 732292SN/A{ 742326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 752292SN/A inst = NULL; 762292SN/A} 772292SN/A 782292SN/A 792292SN/Atemplate <class Impl> 802292SN/Aconst char * 815336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const 822292SN/A{ 834873Sstever@eecs.umich.edu return "Functional unit completion"; 842292SN/A} 852292SN/A 862292SN/Atemplate <class Impl> 874329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 885529Snate@binkert.org DerivO3CPUParams *params) 894329Sktlim@umich.edu : cpu(cpu_ptr), 904329Sktlim@umich.edu iewStage(iew_ptr), 914329Sktlim@umich.edu fuPool(params->fuPool), 922292SN/A numEntries(params->numIQEntries), 932292SN/A totalWidth(params->issueWidth), 942292SN/A commitToIEWDelay(params->commitToIEWDelay) 952292SN/A{ 962292SN/A assert(fuPool); 972292SN/A 985529Snate@binkert.org numThreads = params->numThreads; 991060SN/A 1009920Syasuko.eckert@amd.com // Set the number of total physical registers 10112109SRekai.GonzalezAlberquilla@arm.com // As the vector registers have two addressing modes, they are added twice 1029920Syasuko.eckert@amd.com numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 10312109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs + 10412109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs * TheISA::NumVecElemPerVecReg + 10512109SRekai.GonzalezAlberquilla@arm.com params->numPhysCCRegs; 1061060SN/A 1071060SN/A //Create an entry for each physical register within the 1081060SN/A //dependency graph. 1092326SN/A dependGraph.resize(numPhysRegs); 1101060SN/A 1111060SN/A // Resize the register scoreboard. 1121060SN/A regScoreboard.resize(numPhysRegs); 1131060SN/A 1142292SN/A //Initialize Mem Dependence Units 1156221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1166221Snate@binkert.org memDepUnit[tid].init(params, tid); 1176221Snate@binkert.org memDepUnit[tid].setIQ(this); 1181060SN/A } 1191060SN/A 1202307SN/A resetState(); 1212292SN/A 1222980Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1232292SN/A 1242292SN/A //Convert string to lowercase 1252292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1262292SN/A (int(*)(int)) tolower); 1272292SN/A 1282292SN/A //Figure out resource sharing policy 1292292SN/A if (policy == "dynamic") { 1302292SN/A iqPolicy = Dynamic; 1312292SN/A 1322292SN/A //Set Max Entries to Total ROB Capacity 1336221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1346221Snate@binkert.org maxEntries[tid] = numEntries; 1352292SN/A } 1362292SN/A 1372292SN/A } else if (policy == "partitioned") { 1382292SN/A iqPolicy = Partitioned; 1392292SN/A 1402292SN/A //@todo:make work if part_amt doesnt divide evenly. 1412292SN/A int part_amt = numEntries / numThreads; 1422292SN/A 1432292SN/A //Divide ROB up evenly 1446221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1456221Snate@binkert.org maxEntries[tid] = part_amt; 1462292SN/A } 1472292SN/A 1482831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1492292SN/A "%i entries per thread.\n",part_amt); 1502292SN/A } else if (policy == "threshold") { 1512292SN/A iqPolicy = Threshold; 1522292SN/A 1532292SN/A double threshold = (double)params->smtIQThreshold / 100; 1542292SN/A 1552292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1562292SN/A 1572292SN/A //Divide up by threshold amount 1586221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1596221Snate@binkert.org maxEntries[tid] = thresholdIQ; 1602292SN/A } 1612292SN/A 1622831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1632292SN/A "%i entries per thread.\n",thresholdIQ); 1642292SN/A } else { 1652292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1662292SN/A "Partitioned, Threshold}"); 1672292SN/A } 1682292SN/A} 1692292SN/A 1702292SN/Atemplate <class Impl> 1712292SN/AInstructionQueue<Impl>::~InstructionQueue() 1722292SN/A{ 1732326SN/A dependGraph.reset(); 1742348SN/A#ifdef DEBUG 1752326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1762326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1772348SN/A#endif 1782292SN/A} 1792292SN/A 1802292SN/Atemplate <class Impl> 1812292SN/Astd::string 1822292SN/AInstructionQueue<Impl>::name() const 1832292SN/A{ 1842292SN/A return cpu->name() + ".iq"; 1851060SN/A} 1861060SN/A 1871061SN/Atemplate <class Impl> 1881060SN/Avoid 1891062SN/AInstructionQueue<Impl>::regStats() 1901062SN/A{ 1912301SN/A using namespace Stats; 1921062SN/A iqInstsAdded 1931062SN/A .name(name() + ".iqInstsAdded") 1941062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1951062SN/A .prereq(iqInstsAdded); 1961062SN/A 1971062SN/A iqNonSpecInstsAdded 1981062SN/A .name(name() + ".iqNonSpecInstsAdded") 1991062SN/A .desc("Number of non-speculative instructions added to the IQ") 2001062SN/A .prereq(iqNonSpecInstsAdded); 2011062SN/A 2022301SN/A iqInstsIssued 2032301SN/A .name(name() + ".iqInstsIssued") 2042301SN/A .desc("Number of instructions issued") 2052301SN/A .prereq(iqInstsIssued); 2061062SN/A 2071062SN/A iqIntInstsIssued 2081062SN/A .name(name() + ".iqIntInstsIssued") 2091062SN/A .desc("Number of integer instructions issued") 2101062SN/A .prereq(iqIntInstsIssued); 2111062SN/A 2121062SN/A iqFloatInstsIssued 2131062SN/A .name(name() + ".iqFloatInstsIssued") 2141062SN/A .desc("Number of float instructions issued") 2151062SN/A .prereq(iqFloatInstsIssued); 2161062SN/A 2171062SN/A iqBranchInstsIssued 2181062SN/A .name(name() + ".iqBranchInstsIssued") 2191062SN/A .desc("Number of branch instructions issued") 2201062SN/A .prereq(iqBranchInstsIssued); 2211062SN/A 2221062SN/A iqMemInstsIssued 2231062SN/A .name(name() + ".iqMemInstsIssued") 2241062SN/A .desc("Number of memory instructions issued") 2251062SN/A .prereq(iqMemInstsIssued); 2261062SN/A 2271062SN/A iqMiscInstsIssued 2281062SN/A .name(name() + ".iqMiscInstsIssued") 2291062SN/A .desc("Number of miscellaneous instructions issued") 2301062SN/A .prereq(iqMiscInstsIssued); 2311062SN/A 2321062SN/A iqSquashedInstsIssued 2331062SN/A .name(name() + ".iqSquashedInstsIssued") 2341062SN/A .desc("Number of squashed instructions issued") 2351062SN/A .prereq(iqSquashedInstsIssued); 2361062SN/A 2371062SN/A iqSquashedInstsExamined 2381062SN/A .name(name() + ".iqSquashedInstsExamined") 2391062SN/A .desc("Number of squashed instructions iterated over during squash;" 2401062SN/A " mainly for profiling") 2411062SN/A .prereq(iqSquashedInstsExamined); 2421062SN/A 2431062SN/A iqSquashedOperandsExamined 2441062SN/A .name(name() + ".iqSquashedOperandsExamined") 2451062SN/A .desc("Number of squashed operands that are examined and possibly " 2461062SN/A "removed from graph") 2471062SN/A .prereq(iqSquashedOperandsExamined); 2481062SN/A 2491062SN/A iqSquashedNonSpecRemoved 2501062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2511062SN/A .desc("Number of squashed non-spec instructions that were removed") 2521062SN/A .prereq(iqSquashedNonSpecRemoved); 2532361SN/A/* 2542326SN/A queueResDist 2552301SN/A .init(Num_OpClasses, 0, 99, 2) 2562301SN/A .name(name() + ".IQ:residence:") 2572301SN/A .desc("cycles from dispatch to issue") 2582301SN/A .flags(total | pdf | cdf ) 2592301SN/A ; 2602301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2612326SN/A queueResDist.subname(i, opClassStrings[i]); 2622301SN/A } 2632361SN/A*/ 2642326SN/A numIssuedDist 2652307SN/A .init(0,totalWidth,1) 2668240Snate@binkert.org .name(name() + ".issued_per_cycle") 2672301SN/A .desc("Number of insts issued each cycle") 2682307SN/A .flags(pdf) 2692301SN/A ; 2702301SN/A/* 2712301SN/A dist_unissued 2722301SN/A .init(Num_OpClasses+2) 2738240Snate@binkert.org .name(name() + ".unissued_cause") 2742301SN/A .desc("Reason ready instruction not issued") 2752301SN/A .flags(pdf | dist) 2762301SN/A ; 2772301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2782301SN/A dist_unissued.subname(i, unissued_names[i]); 2792301SN/A } 2802301SN/A*/ 2812326SN/A statIssuedInstType 2824762Snate@binkert.org .init(numThreads,Enums::Num_OpClass) 2838240Snate@binkert.org .name(name() + ".FU_type") 2842301SN/A .desc("Type of FU issued") 2852301SN/A .flags(total | pdf | dist) 2862301SN/A ; 2874762Snate@binkert.org statIssuedInstType.ysubnames(Enums::OpClassStrings); 2882301SN/A 2892301SN/A // 2902301SN/A // How long did instructions for a particular FU type wait prior to issue 2912301SN/A // 2922361SN/A/* 2932326SN/A issueDelayDist 2942301SN/A .init(Num_OpClasses,0,99,2) 2958240Snate@binkert.org .name(name() + ".") 2962301SN/A .desc("cycles from operands ready to issue") 2972301SN/A .flags(pdf | cdf) 2982301SN/A ; 2992301SN/A 3002301SN/A for (int i=0; i<Num_OpClasses; ++i) { 3012980Sgblack@eecs.umich.edu std::stringstream subname; 3022301SN/A subname << opClassStrings[i] << "_delay"; 3032326SN/A issueDelayDist.subname(i, subname.str()); 3042301SN/A } 3052361SN/A*/ 3062326SN/A issueRate 3078240Snate@binkert.org .name(name() + ".rate") 3082301SN/A .desc("Inst issue rate") 3092301SN/A .flags(total) 3102301SN/A ; 3112326SN/A issueRate = iqInstsIssued / cpu->numCycles; 3122727Sktlim@umich.edu 3132326SN/A statFuBusy 3142301SN/A .init(Num_OpClasses) 3158240Snate@binkert.org .name(name() + ".fu_full") 3162301SN/A .desc("attempts to use FU when none available") 3172301SN/A .flags(pdf | dist) 3182301SN/A ; 3192301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3204762Snate@binkert.org statFuBusy.subname(i, Enums::OpClassStrings[i]); 3212301SN/A } 3222301SN/A 3232326SN/A fuBusy 3242301SN/A .init(numThreads) 3258240Snate@binkert.org .name(name() + ".fu_busy_cnt") 3262301SN/A .desc("FU busy when requested") 3272301SN/A .flags(total) 3282301SN/A ; 3292301SN/A 3302326SN/A fuBusyRate 3318240Snate@binkert.org .name(name() + ".fu_busy_rate") 3322301SN/A .desc("FU busy rate (busy events/executed inst)") 3332301SN/A .flags(total) 3342301SN/A ; 3352326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3362301SN/A 3376221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3382292SN/A // Tell mem dependence unit to reg stats as well. 3396221Snate@binkert.org memDepUnit[tid].regStats(); 3402292SN/A } 3417897Shestness@cs.utexas.edu 3427897Shestness@cs.utexas.edu intInstQueueReads 3437897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3447897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3457897Shestness@cs.utexas.edu .flags(total); 3467897Shestness@cs.utexas.edu 3477897Shestness@cs.utexas.edu intInstQueueWrites 3487897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3497897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3507897Shestness@cs.utexas.edu .flags(total); 3517897Shestness@cs.utexas.edu 3527897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3537897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3547897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3557897Shestness@cs.utexas.edu .flags(total); 3567897Shestness@cs.utexas.edu 3577897Shestness@cs.utexas.edu fpInstQueueReads 3587897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3597897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3607897Shestness@cs.utexas.edu .flags(total); 3617897Shestness@cs.utexas.edu 3627897Shestness@cs.utexas.edu fpInstQueueWrites 3637897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3647897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3657897Shestness@cs.utexas.edu .flags(total); 3667897Shestness@cs.utexas.edu 36712110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWakeupAccesses 3687897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3697897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3707897Shestness@cs.utexas.edu .flags(total); 3717897Shestness@cs.utexas.edu 3727897Shestness@cs.utexas.edu intAluAccesses 3737897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 3747897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 3757897Shestness@cs.utexas.edu .flags(total); 3767897Shestness@cs.utexas.edu 3777897Shestness@cs.utexas.edu fpAluAccesses 3787897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 3797897Shestness@cs.utexas.edu .desc("Number of floating point alu accesses") 3807897Shestness@cs.utexas.edu .flags(total); 3817897Shestness@cs.utexas.edu 3821062SN/A} 3831062SN/A 3841062SN/Atemplate <class Impl> 3851062SN/Avoid 3862307SN/AInstructionQueue<Impl>::resetState() 3871060SN/A{ 3882307SN/A //Initialize thread IQ counts 3896221Snate@binkert.org for (ThreadID tid = 0; tid <numThreads; tid++) { 3906221Snate@binkert.org count[tid] = 0; 3916221Snate@binkert.org instList[tid].clear(); 3922307SN/A } 3931060SN/A 3942307SN/A // Initialize the number of free IQ entries. 3952307SN/A freeEntries = numEntries; 3962307SN/A 3972307SN/A // Note that in actuality, the registers corresponding to the logical 3982307SN/A // registers start off as ready. However this doesn't matter for the 3992307SN/A // IQ as the instruction should have been correctly told if those 4002307SN/A // registers are ready in rename. Thus it can all be initialized as 4012307SN/A // unready. 4022307SN/A for (int i = 0; i < numPhysRegs; ++i) { 4032307SN/A regScoreboard[i] = false; 4042307SN/A } 4052307SN/A 4066221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 4076221Snate@binkert.org squashedSeqNum[tid] = 0; 4082307SN/A } 4092307SN/A 4102307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4112307SN/A while (!readyInsts[i].empty()) 4122307SN/A readyInsts[i].pop(); 4132307SN/A queueOnList[i] = false; 4142307SN/A readyIt[i] = listOrder.end(); 4152307SN/A } 4162307SN/A nonSpecInsts.clear(); 4172307SN/A listOrder.clear(); 4187944SGiacomo.Gabrielli@arm.com deferredMemInsts.clear(); 41910333Smitch.hayenga@arm.com blockedMemInsts.clear(); 42010333Smitch.hayenga@arm.com retryMemInsts.clear(); 42110511Smitch.hayenga@arm.com wbOutstanding = 0; 4221060SN/A} 4231060SN/A 4241061SN/Atemplate <class Impl> 4251060SN/Avoid 4266221Snate@binkert.orgInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4271060SN/A{ 4282292SN/A activeThreads = at_ptr; 4292064SN/A} 4302064SN/A 4312064SN/Atemplate <class Impl> 4322064SN/Avoid 4332292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4342064SN/A{ 4354318Sktlim@umich.edu issueToExecuteQueue = i2e_ptr; 4361060SN/A} 4371060SN/A 4381061SN/Atemplate <class Impl> 4391060SN/Avoid 4401060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4411060SN/A{ 4421060SN/A timeBuffer = tb_ptr; 4431060SN/A 4441060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4451060SN/A} 4461060SN/A 4471684SN/Atemplate <class Impl> 44810510Smitch.hayenga@arm.combool 44910510Smitch.hayenga@arm.comInstructionQueue<Impl>::isDrained() const 45010510Smitch.hayenga@arm.com{ 45110511Smitch.hayenga@arm.com bool drained = dependGraph.empty() && 45210511Smitch.hayenga@arm.com instsToExecute.empty() && 45310511Smitch.hayenga@arm.com wbOutstanding == 0; 45410510Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) 45510510Smitch.hayenga@arm.com drained = drained && memDepUnit[tid].isDrained(); 45610510Smitch.hayenga@arm.com 45710510Smitch.hayenga@arm.com return drained; 45810510Smitch.hayenga@arm.com} 45910510Smitch.hayenga@arm.com 46010510Smitch.hayenga@arm.comtemplate <class Impl> 4612307SN/Avoid 4629444SAndreas.Sandberg@ARM.comInstructionQueue<Impl>::drainSanityCheck() const 4632307SN/A{ 4649444SAndreas.Sandberg@ARM.com assert(dependGraph.empty()); 4659444SAndreas.Sandberg@ARM.com assert(instsToExecute.empty()); 4669444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; ++tid) 4679444SAndreas.Sandberg@ARM.com memDepUnit[tid].drainSanityCheck(); 4682307SN/A} 4692307SN/A 4702307SN/Atemplate <class Impl> 4712307SN/Avoid 4722307SN/AInstructionQueue<Impl>::takeOverFrom() 4732307SN/A{ 4749444SAndreas.Sandberg@ARM.com resetState(); 4752307SN/A} 4762307SN/A 4772307SN/Atemplate <class Impl> 4782292SN/Aint 4796221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4802292SN/A{ 4812292SN/A if (iqPolicy == Partitioned) { 4822292SN/A return numEntries / num_threads; 4832292SN/A } else { 4842292SN/A return 0; 4852292SN/A } 4862292SN/A} 4872292SN/A 4882292SN/A 4892292SN/Atemplate <class Impl> 4902292SN/Avoid 4912292SN/AInstructionQueue<Impl>::resetEntries() 4922292SN/A{ 4932292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4943867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 4952292SN/A 4966221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4976221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4982292SN/A 4993867Sbinkertn@umich.edu while (threads != end) { 5006221Snate@binkert.org ThreadID tid = *threads++; 5013867Sbinkertn@umich.edu 5022292SN/A if (iqPolicy == Partitioned) { 5033867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 50411321Ssteve.reinhardt@amd.com } else if (iqPolicy == Threshold && active_threads == 1) { 5053867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 5062292SN/A } 5072292SN/A } 5082292SN/A } 5092292SN/A} 5102292SN/A 5112292SN/Atemplate <class Impl> 5121684SN/Aunsigned 5131684SN/AInstructionQueue<Impl>::numFreeEntries() 5141684SN/A{ 5151684SN/A return freeEntries; 5161684SN/A} 5171684SN/A 5182292SN/Atemplate <class Impl> 5192292SN/Aunsigned 5206221Snate@binkert.orgInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5212292SN/A{ 5222292SN/A return maxEntries[tid] - count[tid]; 5232292SN/A} 5242292SN/A 5251060SN/A// Might want to do something more complex if it knows how many instructions 5261060SN/A// will be issued this cycle. 5271061SN/Atemplate <class Impl> 5281060SN/Abool 5291060SN/AInstructionQueue<Impl>::isFull() 5301060SN/A{ 5311060SN/A if (freeEntries == 0) { 5321060SN/A return(true); 5331060SN/A } else { 5341060SN/A return(false); 5351060SN/A } 5361060SN/A} 5371060SN/A 5381061SN/Atemplate <class Impl> 5392292SN/Abool 5406221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid) 5412292SN/A{ 5422292SN/A if (numFreeEntries(tid) == 0) { 5432292SN/A return(true); 5442292SN/A } else { 5452292SN/A return(false); 5462292SN/A } 5472292SN/A} 5482292SN/A 5492292SN/Atemplate <class Impl> 5502292SN/Abool 5512292SN/AInstructionQueue<Impl>::hasReadyInsts() 5522292SN/A{ 5532292SN/A if (!listOrder.empty()) { 5542292SN/A return true; 5552292SN/A } 5562292SN/A 5572292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5582292SN/A if (!readyInsts[i].empty()) { 5592292SN/A return true; 5602292SN/A } 5612292SN/A } 5622292SN/A 5632292SN/A return false; 5642292SN/A} 5652292SN/A 5662292SN/Atemplate <class Impl> 5671060SN/Avoid 5681061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5691060SN/A{ 57012110SRekai.GonzalezAlberquilla@arm.com if (new_inst->isFloating()) { 57112110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 57212110SRekai.GonzalezAlberquilla@arm.com } else if (new_inst->isVector()) { 57312110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 57412110SRekai.GonzalezAlberquilla@arm.com } else { 57512110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 57612110SRekai.GonzalezAlberquilla@arm.com } 5771060SN/A // Make sure the instruction is valid 5781060SN/A assert(new_inst); 5791060SN/A 5807720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5817720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 5821060SN/A 5831060SN/A assert(freeEntries != 0); 5841060SN/A 5852292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5861060SN/A 5872064SN/A --freeEntries; 5881060SN/A 5892292SN/A new_inst->setInIQ(); 5901060SN/A 5911060SN/A // Look through its source registers (physical regs), and mark any 5921060SN/A // dependencies. 5931060SN/A addToDependents(new_inst); 5941060SN/A 5951060SN/A // Have this instruction set itself as the producer of its destination 5961060SN/A // register(s). 5972326SN/A addToProducers(new_inst); 5981060SN/A 5991061SN/A if (new_inst->isMemRef()) { 6002292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 6011062SN/A } else { 6021062SN/A addIfReady(new_inst); 6031061SN/A } 6041061SN/A 6051062SN/A ++iqInstsAdded; 6061060SN/A 6072292SN/A count[new_inst->threadNumber]++; 6082292SN/A 6091060SN/A assert(freeEntries == (numEntries - countInsts())); 6101060SN/A} 6111060SN/A 6121061SN/Atemplate <class Impl> 6131061SN/Avoid 6142292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 6151061SN/A{ 6161061SN/A // @todo: Clean up this code; can do it by setting inst as unable 6171061SN/A // to issue, then calling normal insert on the inst. 61812110SRekai.GonzalezAlberquilla@arm.com if (new_inst->isFloating()) { 61912110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 62012110SRekai.GonzalezAlberquilla@arm.com } else if (new_inst->isVector()) { 62112110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 62212110SRekai.GonzalezAlberquilla@arm.com } else { 62312110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 62412110SRekai.GonzalezAlberquilla@arm.com } 6251061SN/A 6262292SN/A assert(new_inst); 6271061SN/A 6282292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 6291061SN/A 6307720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6312326SN/A "to the IQ.\n", 6327720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 6332064SN/A 6341061SN/A assert(freeEntries != 0); 6351061SN/A 6362292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6371061SN/A 6382064SN/A --freeEntries; 6391061SN/A 6402292SN/A new_inst->setInIQ(); 6411061SN/A 6421061SN/A // Have this instruction set itself as the producer of its destination 6431061SN/A // register(s). 6442326SN/A addToProducers(new_inst); 6451061SN/A 6461061SN/A // If it's a memory instruction, add it to the memory dependency 6471061SN/A // unit. 6482292SN/A if (new_inst->isMemRef()) { 6492292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6501061SN/A } 6511062SN/A 6521062SN/A ++iqNonSpecInstsAdded; 6532292SN/A 6542292SN/A count[new_inst->threadNumber]++; 6552292SN/A 6562292SN/A assert(freeEntries == (numEntries - countInsts())); 6571061SN/A} 6581061SN/A 6591061SN/Atemplate <class Impl> 6601060SN/Avoid 6612292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 6621060SN/A{ 6632292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6641060SN/A 6652292SN/A insertNonSpec(barr_inst); 6662292SN/A} 6671060SN/A 6682064SN/Atemplate <class Impl> 6692333SN/Atypename Impl::DynInstPtr 6702333SN/AInstructionQueue<Impl>::getInstToExecute() 6712333SN/A{ 6722333SN/A assert(!instsToExecute.empty()); 6732333SN/A DynInstPtr inst = instsToExecute.front(); 6742333SN/A instsToExecute.pop_front(); 67512110SRekai.GonzalezAlberquilla@arm.com if (inst->isFloating()) { 6767897Shestness@cs.utexas.edu fpInstQueueReads++; 67712110SRekai.GonzalezAlberquilla@arm.com } else if (inst->isVector()) { 67812110SRekai.GonzalezAlberquilla@arm.com vecInstQueueReads++; 6797897Shestness@cs.utexas.edu } else { 6807897Shestness@cs.utexas.edu intInstQueueReads++; 6817897Shestness@cs.utexas.edu } 6822333SN/A return inst; 6832333SN/A} 6841060SN/A 6852333SN/Atemplate <class Impl> 6862064SN/Avoid 6872292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6882292SN/A{ 6892292SN/A assert(!readyInsts[op_class].empty()); 6902292SN/A 6912292SN/A ListOrderEntry queue_entry; 6922292SN/A 6932292SN/A queue_entry.queueType = op_class; 6942292SN/A 6952292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6962292SN/A 6972292SN/A ListOrderIt list_it = listOrder.begin(); 6982292SN/A ListOrderIt list_end_it = listOrder.end(); 6992292SN/A 7002292SN/A while (list_it != list_end_it) { 7012292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 7022292SN/A break; 7032292SN/A } 7042292SN/A 7052292SN/A list_it++; 7061060SN/A } 7071060SN/A 7082292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 7092292SN/A queueOnList[op_class] = true; 7102292SN/A} 7111060SN/A 7122292SN/Atemplate <class Impl> 7132292SN/Avoid 7142292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 7152292SN/A{ 7162292SN/A // Get iterator of next item on the list 7172292SN/A // Delete the original iterator 7182292SN/A // Determine if the next item is either the end of the list or younger 7192292SN/A // than the new instruction. If so, then add in a new iterator right here. 7202292SN/A // If not, then move along. 7212292SN/A ListOrderEntry queue_entry; 7222292SN/A OpClass op_class = (*list_order_it).queueType; 7232292SN/A ListOrderIt next_it = list_order_it; 7242292SN/A 7252292SN/A ++next_it; 7262292SN/A 7272292SN/A queue_entry.queueType = op_class; 7282292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7292292SN/A 7302292SN/A while (next_it != listOrder.end() && 7312292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 7322292SN/A ++next_it; 7331060SN/A } 7341060SN/A 7352292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7361060SN/A} 7371060SN/A 7382292SN/Atemplate <class Impl> 7392292SN/Avoid 7402292SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 7412292SN/A{ 7422367SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7439444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 7442292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7452292SN/A // long latency op). Wake it if it was. This may be overkill. 74610511Smitch.hayenga@arm.com --wbOutstanding; 7472292SN/A iewStage->wakeCPU(); 7482292SN/A 7492326SN/A if (fu_idx > -1) 7502326SN/A fuPool->freeUnitNextCycle(fu_idx); 7512292SN/A 7522326SN/A // @todo: Ensure that these FU Completions happen at the beginning 7532326SN/A // of a cycle, otherwise they could add too many instructions to 7542326SN/A // the queue. 7555327Smengke97@hotmail.com issueToExecuteQueue->access(-1)->size++; 7562333SN/A instsToExecute.push_back(inst); 7572292SN/A} 7582292SN/A 7591061SN/A// @todo: Figure out a better way to remove the squashed items from the 7601061SN/A// lists. Checking the top item of each list to see if it's squashed 7611061SN/A// wastes time and forces jumps. 7621061SN/Atemplate <class Impl> 7631060SN/Avoid 7641060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7651060SN/A{ 7662292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7672292SN/A "the IQ.\n"); 7681060SN/A 7691060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7701060SN/A 77110333Smitch.hayenga@arm.com DynInstPtr mem_inst; 77210333Smitch.hayenga@arm.com while (mem_inst = getDeferredMemInstToExecute()) { 77310333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 77410333Smitch.hayenga@arm.com } 77510333Smitch.hayenga@arm.com 77610333Smitch.hayenga@arm.com // See if any cache blocked instructions are able to be executed 77710333Smitch.hayenga@arm.com while (mem_inst = getBlockedMemInstToExecute()) { 77810333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 7797944SGiacomo.Gabrielli@arm.com } 7807944SGiacomo.Gabrielli@arm.com 7812292SN/A // Have iterator to head of the list 7822292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7832292SN/A // Try to get a FU that can do what this op needs. 7842292SN/A // If successful, change the oldestInst to the new top of the list, put 7852292SN/A // the queue in the proper place in the list. 7862292SN/A // Increment the iterator. 7872292SN/A // This will avoid trying to schedule a certain op class if there are no 7882292SN/A // FUs that handle it. 78910333Smitch.hayenga@arm.com int total_issued = 0; 7902292SN/A ListOrderIt order_it = listOrder.begin(); 7912292SN/A ListOrderIt order_end_it = listOrder.end(); 7921060SN/A 79310333Smitch.hayenga@arm.com while (total_issued < totalWidth && order_it != order_end_it) { 7942292SN/A OpClass op_class = (*order_it).queueType; 7951060SN/A 7962292SN/A assert(!readyInsts[op_class].empty()); 7971060SN/A 7982292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7991060SN/A 80012110SRekai.GonzalezAlberquilla@arm.com if (issuing_inst->isFloating()) { 80112110SRekai.GonzalezAlberquilla@arm.com fpInstQueueReads++; 80212110SRekai.GonzalezAlberquilla@arm.com } else if (issuing_inst->isVector()) { 80312110SRekai.GonzalezAlberquilla@arm.com vecInstQueueReads++; 80412110SRekai.GonzalezAlberquilla@arm.com } else { 80512110SRekai.GonzalezAlberquilla@arm.com intInstQueueReads++; 80612110SRekai.GonzalezAlberquilla@arm.com } 8077897Shestness@cs.utexas.edu 8082292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 8091060SN/A 8102292SN/A if (issuing_inst->isSquashed()) { 8112292SN/A readyInsts[op_class].pop(); 8121060SN/A 8132292SN/A if (!readyInsts[op_class].empty()) { 8142292SN/A moveToYoungerInst(order_it); 8152292SN/A } else { 8162292SN/A readyIt[op_class] = listOrder.end(); 8172292SN/A queueOnList[op_class] = false; 8181060SN/A } 8191060SN/A 8202292SN/A listOrder.erase(order_it++); 8211060SN/A 8222292SN/A ++iqSquashedInstsIssued; 8232292SN/A 8242292SN/A continue; 8251060SN/A } 8261060SN/A 82711365SRekai.GonzalezAlberquilla@arm.com int idx = FUPool::NoCapableFU; 8289184Sandreas.hansson@arm.com Cycles op_latency = Cycles(1); 8296221Snate@binkert.org ThreadID tid = issuing_inst->threadNumber; 8301060SN/A 8312326SN/A if (op_class != No_OpClass) { 8322326SN/A idx = fuPool->getUnit(op_class); 83312110SRekai.GonzalezAlberquilla@arm.com if (issuing_inst->isFloating()) { 83412110SRekai.GonzalezAlberquilla@arm.com fpAluAccesses++; 83512110SRekai.GonzalezAlberquilla@arm.com } else if (issuing_inst->isVector()) { 83612110SRekai.GonzalezAlberquilla@arm.com vecAluAccesses++; 83712110SRekai.GonzalezAlberquilla@arm.com } else { 83812110SRekai.GonzalezAlberquilla@arm.com intAluAccesses++; 83912110SRekai.GonzalezAlberquilla@arm.com } 84011365SRekai.GonzalezAlberquilla@arm.com if (idx > FUPool::NoFreeFU) { 8412326SN/A op_latency = fuPool->getOpLatency(op_class); 8421060SN/A } 8431060SN/A } 8441060SN/A 8452348SN/A // If we have an instruction that doesn't require a FU, or a 8462348SN/A // valid FU, then schedule for execution. 84711365SRekai.GonzalezAlberquilla@arm.com if (idx != FUPool::NoFreeFU) { 8489184Sandreas.hansson@arm.com if (op_latency == Cycles(1)) { 8492292SN/A i2e_info->size++; 8502333SN/A instsToExecute.push_back(issuing_inst); 8511060SN/A 8522326SN/A // Add the FU onto the list of FU's to be freed next 8532326SN/A // cycle if we used one. 8542326SN/A if (idx >= 0) 8552326SN/A fuPool->freeUnitNextCycle(idx); 8562292SN/A } else { 85710807Snilay@cs.wisc.edu bool pipelined = fuPool->isPipelined(op_class); 8582326SN/A // Generate completion event for the FU 85910511Smitch.hayenga@arm.com ++wbOutstanding; 8602326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8612326SN/A idx, this); 8621060SN/A 8639180Sandreas.hansson@arm.com cpu->schedule(execution, 8649180Sandreas.hansson@arm.com cpu->clockEdge(Cycles(op_latency - 1))); 8651060SN/A 86610807Snilay@cs.wisc.edu if (!pipelined) { 8672348SN/A // If FU isn't pipelined, then it must be freed 8682348SN/A // upon the execution completing. 8692326SN/A execution->setFreeFU(); 8702292SN/A } else { 8712292SN/A // Add the FU onto the list of FU's to be freed next cycle. 8722326SN/A fuPool->freeUnitNextCycle(idx); 8732292SN/A } 8741060SN/A } 8751060SN/A 8767720Sgblack@eecs.umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8772292SN/A "[sn:%lli]\n", 8787720Sgblack@eecs.umich.edu tid, issuing_inst->pcState(), 8792292SN/A issuing_inst->seqNum); 8801060SN/A 8812292SN/A readyInsts[op_class].pop(); 8821061SN/A 8832292SN/A if (!readyInsts[op_class].empty()) { 8842292SN/A moveToYoungerInst(order_it); 8852292SN/A } else { 8862292SN/A readyIt[op_class] = listOrder.end(); 8872292SN/A queueOnList[op_class] = false; 8881060SN/A } 8891060SN/A 8902064SN/A issuing_inst->setIssued(); 8912292SN/A ++total_issued; 8922064SN/A 8938471SGiacomo.Gabrielli@arm.com#if TRACING_ON 8949046SAli.Saidi@ARM.com issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 8958471SGiacomo.Gabrielli@arm.com#endif 8968471SGiacomo.Gabrielli@arm.com 8972292SN/A if (!issuing_inst->isMemRef()) { 8982292SN/A // Memory instructions can not be freed from the IQ until they 8992292SN/A // complete. 9002292SN/A ++freeEntries; 9012301SN/A count[tid]--; 9022731Sktlim@umich.edu issuing_inst->clearInIQ(); 9032292SN/A } else { 9042301SN/A memDepUnit[tid].issue(issuing_inst); 9052292SN/A } 9062292SN/A 9072292SN/A listOrder.erase(order_it++); 9082326SN/A statIssuedInstType[tid][op_class]++; 9092292SN/A } else { 9102326SN/A statFuBusy[op_class]++; 9112326SN/A fuBusy[tid]++; 9122292SN/A ++order_it; 9131060SN/A } 9141060SN/A } 9151062SN/A 9162326SN/A numIssuedDist.sample(total_issued); 9172326SN/A iqInstsIssued+= total_issued; 9182307SN/A 9192348SN/A // If we issued any instructions, tell the CPU we had activity. 9208071SAli.Saidi@ARM.com // @todo If the way deferred memory instructions are handeled due to 9218071SAli.Saidi@ARM.com // translation changes then the deferredMemInsts condition should be removed 9228071SAli.Saidi@ARM.com // from the code below. 92310333Smitch.hayenga@arm.com if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) { 9242292SN/A cpu->activityThisCycle(); 9252292SN/A } else { 9262292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 9272292SN/A } 9281060SN/A} 9291060SN/A 9301061SN/Atemplate <class Impl> 9311060SN/Avoid 9321061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 9331060SN/A{ 9342292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 9352292SN/A "to execute.\n", inst); 9361062SN/A 9372292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9381060SN/A 9391061SN/A assert(inst_it != nonSpecInsts.end()); 9401060SN/A 9416221Snate@binkert.org ThreadID tid = (*inst_it).second->threadNumber; 9422292SN/A 9434033Sktlim@umich.edu (*inst_it).second->setAtCommit(); 9444033Sktlim@umich.edu 9451061SN/A (*inst_it).second->setCanIssue(); 9461060SN/A 9471062SN/A if (!(*inst_it).second->isMemRef()) { 9481062SN/A addIfReady((*inst_it).second); 9491062SN/A } else { 9502292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9511062SN/A } 9521060SN/A 9532292SN/A (*inst_it).second = NULL; 9542292SN/A 9551061SN/A nonSpecInsts.erase(inst_it); 9561060SN/A} 9571060SN/A 9581061SN/Atemplate <class Impl> 9591061SN/Avoid 9606221Snate@binkert.orgInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9612292SN/A{ 9622292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9632292SN/A tid,inst); 9642292SN/A 9652292SN/A ListIt iq_it = instList[tid].begin(); 9662292SN/A 9672292SN/A while (iq_it != instList[tid].end() && 9682292SN/A (*iq_it)->seqNum <= inst) { 9692292SN/A ++iq_it; 9702292SN/A instList[tid].pop_front(); 9712292SN/A } 9722292SN/A 9732292SN/A assert(freeEntries == (numEntries - countInsts())); 9742292SN/A} 9752292SN/A 9762292SN/Atemplate <class Impl> 9772301SN/Aint 9781684SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 9791684SN/A{ 9802301SN/A int dependents = 0; 9812301SN/A 9827897Shestness@cs.utexas.edu // The instruction queue here takes care of both floating and int ops 9837897Shestness@cs.utexas.edu if (completed_inst->isFloating()) { 98412110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWakeupAccesses++; 98512110SRekai.GonzalezAlberquilla@arm.com } else if (completed_inst->isVector()) { 98612110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWakeupAccesses++; 9877897Shestness@cs.utexas.edu } else { 9887897Shestness@cs.utexas.edu intInstQueueWakeupAccesses++; 9897897Shestness@cs.utexas.edu } 9907897Shestness@cs.utexas.edu 9912292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 9922292SN/A 9932292SN/A assert(!completed_inst->isSquashed()); 9941684SN/A 9951684SN/A // Tell the memory dependence unit to wake any dependents on this 9962292SN/A // instruction if it is a memory instruction. Also complete the memory 9972326SN/A // instruction at this point since we know it executed without issues. 9982326SN/A // @todo: Might want to rename "completeMemInst" to something that 9992326SN/A // indicates that it won't need to be replayed, and call this 10002326SN/A // earlier. Might not be a big deal. 10011684SN/A if (completed_inst->isMemRef()) { 10022292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 10032292SN/A completeMemInst(completed_inst); 10042292SN/A } else if (completed_inst->isMemBarrier() || 10052292SN/A completed_inst->isWriteBarrier()) { 10062292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 10071684SN/A } 10081684SN/A 10091684SN/A for (int dest_reg_idx = 0; 10101684SN/A dest_reg_idx < completed_inst->numDestRegs(); 10111684SN/A dest_reg_idx++) 10121684SN/A { 101312105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = 10141684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 10151684SN/A 10161684SN/A // Special case of uniq or control registers. They are not 10171684SN/A // handled by the IQ and thus have no dependency graph entry. 101812105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 101912105Snathanael.premillieu@arm.com DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n", 102012106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className()); 10211684SN/A continue; 10221684SN/A } 10231684SN/A 102412105Snathanael.premillieu@arm.com DPRINTF(IQ, "Waking any dependents on register %i (%s).\n", 102512106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), 102612106SRekai.GonzalezAlberquilla@arm.com dest_reg->className()); 10271684SN/A 10282326SN/A //Go through the dependency chain, marking the registers as 10292326SN/A //ready within the waiting instructions. 103012106SRekai.GonzalezAlberquilla@arm.com DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10311684SN/A 10322326SN/A while (dep_inst) { 10337599Sminkyu.jeong@arm.com DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 10347720Sgblack@eecs.umich.edu "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 10351684SN/A 10361684SN/A // Might want to give more information to the instruction 10372326SN/A // so that it knows which of its source registers is 10382326SN/A // ready. However that would mean that the dependency 10392326SN/A // graph entries would need to hold the src_reg_idx. 10402326SN/A dep_inst->markSrcRegReady(); 10411684SN/A 10422326SN/A addIfReady(dep_inst); 10431684SN/A 104412106SRekai.GonzalezAlberquilla@arm.com dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10451684SN/A 10462301SN/A ++dependents; 10471684SN/A } 10481684SN/A 10492326SN/A // Reset the head node now that all of its dependents have 10502326SN/A // been woken up. 105112106SRekai.GonzalezAlberquilla@arm.com assert(dependGraph.empty(dest_reg->flatIndex())); 105212106SRekai.GonzalezAlberquilla@arm.com dependGraph.clearInst(dest_reg->flatIndex()); 10531684SN/A 10541684SN/A // Mark the scoreboard as having that register ready. 105512106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = true; 10561684SN/A } 10572301SN/A return dependents; 10582064SN/A} 10592064SN/A 10602064SN/Atemplate <class Impl> 10612064SN/Avoid 10622292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 10632064SN/A{ 10642292SN/A OpClass op_class = ready_inst->opClass(); 10652292SN/A 10662292SN/A readyInsts[op_class].push(ready_inst); 10672292SN/A 10682326SN/A // Will need to reorder the list if either a queue is not on the list, 10692326SN/A // or it has an older instruction than last time. 10702326SN/A if (!queueOnList[op_class]) { 10712326SN/A addToOrderList(op_class); 10722326SN/A } else if (readyInsts[op_class].top()->seqNum < 10732326SN/A (*readyIt[op_class]).oldestInst) { 10742326SN/A listOrder.erase(readyIt[op_class]); 10752326SN/A addToOrderList(op_class); 10762326SN/A } 10772326SN/A 10782292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10797720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 10807720Sgblack@eecs.umich.edu ready_inst->pcState(), op_class, ready_inst->seqNum); 10812064SN/A} 10822064SN/A 10832064SN/Atemplate <class Impl> 10842064SN/Avoid 10852292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 10862064SN/A{ 10874033Sktlim@umich.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 10887944SGiacomo.Gabrielli@arm.com 10897944SGiacomo.Gabrielli@arm.com // Reset DTB translation state 10909046SAli.Saidi@ARM.com resched_inst->translationStarted(false); 10919046SAli.Saidi@ARM.com resched_inst->translationCompleted(false); 10927944SGiacomo.Gabrielli@arm.com 10934033Sktlim@umich.edu resched_inst->clearCanIssue(); 10942292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 10952064SN/A} 10962064SN/A 10972064SN/Atemplate <class Impl> 10982064SN/Avoid 10992292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 11002064SN/A{ 110110333Smitch.hayenga@arm.com memDepUnit[replay_inst->threadNumber].replay(); 11022292SN/A} 11032292SN/A 11042292SN/Atemplate <class Impl> 11052292SN/Avoid 11062292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 11072292SN/A{ 11086221Snate@binkert.org ThreadID tid = completed_inst->threadNumber; 11092292SN/A 11107720Sgblack@eecs.umich.edu DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 11117720Sgblack@eecs.umich.edu completed_inst->pcState(), completed_inst->seqNum); 11122292SN/A 11132292SN/A ++freeEntries; 11142292SN/A 11159046SAli.Saidi@ARM.com completed_inst->memOpDone(true); 11162292SN/A 11172292SN/A memDepUnit[tid].completed(completed_inst); 11182292SN/A count[tid]--; 11191684SN/A} 11201684SN/A 11211684SN/Atemplate <class Impl> 11221684SN/Avoid 11237944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 11247944SGiacomo.Gabrielli@arm.com{ 11257944SGiacomo.Gabrielli@arm.com deferredMemInsts.push_back(deferred_inst); 11267944SGiacomo.Gabrielli@arm.com} 11277944SGiacomo.Gabrielli@arm.com 11287944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 112910333Smitch.hayenga@arm.comvoid 113010333Smitch.hayenga@arm.comInstructionQueue<Impl>::blockMemInst(DynInstPtr &blocked_inst) 113110333Smitch.hayenga@arm.com{ 113210333Smitch.hayenga@arm.com blocked_inst->translationStarted(false); 113310333Smitch.hayenga@arm.com blocked_inst->translationCompleted(false); 113410333Smitch.hayenga@arm.com 113510333Smitch.hayenga@arm.com blocked_inst->clearIssued(); 113610333Smitch.hayenga@arm.com blocked_inst->clearCanIssue(); 113710333Smitch.hayenga@arm.com blockedMemInsts.push_back(blocked_inst); 113810333Smitch.hayenga@arm.com} 113910333Smitch.hayenga@arm.com 114010333Smitch.hayenga@arm.comtemplate <class Impl> 114110333Smitch.hayenga@arm.comvoid 114210333Smitch.hayenga@arm.comInstructionQueue<Impl>::cacheUnblocked() 114310333Smitch.hayenga@arm.com{ 114410333Smitch.hayenga@arm.com retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts); 114510333Smitch.hayenga@arm.com // Get the CPU ticking again 114610333Smitch.hayenga@arm.com cpu->wakeCPU(); 114710333Smitch.hayenga@arm.com} 114810333Smitch.hayenga@arm.com 114910333Smitch.hayenga@arm.comtemplate <class Impl> 11507944SGiacomo.Gabrielli@arm.comtypename Impl::DynInstPtr 11517944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::getDeferredMemInstToExecute() 11527944SGiacomo.Gabrielli@arm.com{ 11537944SGiacomo.Gabrielli@arm.com for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 11547944SGiacomo.Gabrielli@arm.com ++it) { 11559046SAli.Saidi@ARM.com if ((*it)->translationCompleted() || (*it)->isSquashed()) { 115610333Smitch.hayenga@arm.com DynInstPtr mem_inst = *it; 11577944SGiacomo.Gabrielli@arm.com deferredMemInsts.erase(it); 115810333Smitch.hayenga@arm.com return mem_inst; 11597944SGiacomo.Gabrielli@arm.com } 11607944SGiacomo.Gabrielli@arm.com } 116110333Smitch.hayenga@arm.com return nullptr; 116210333Smitch.hayenga@arm.com} 116310333Smitch.hayenga@arm.com 116410333Smitch.hayenga@arm.comtemplate <class Impl> 116510333Smitch.hayenga@arm.comtypename Impl::DynInstPtr 116610333Smitch.hayenga@arm.comInstructionQueue<Impl>::getBlockedMemInstToExecute() 116710333Smitch.hayenga@arm.com{ 116810333Smitch.hayenga@arm.com if (retryMemInsts.empty()) { 116910333Smitch.hayenga@arm.com return nullptr; 117010333Smitch.hayenga@arm.com } else { 117110333Smitch.hayenga@arm.com DynInstPtr mem_inst = retryMemInsts.front(); 117210333Smitch.hayenga@arm.com retryMemInsts.pop_front(); 117310333Smitch.hayenga@arm.com return mem_inst; 117410333Smitch.hayenga@arm.com } 11757944SGiacomo.Gabrielli@arm.com} 11767944SGiacomo.Gabrielli@arm.com 11777944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 11787944SGiacomo.Gabrielli@arm.comvoid 11791061SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 11801061SN/A DynInstPtr &faulting_load) 11811061SN/A{ 11827897Shestness@cs.utexas.edu intInstQueueWrites++; 11832292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 11841061SN/A} 11851061SN/A 11861061SN/Atemplate <class Impl> 11871060SN/Avoid 11886221Snate@binkert.orgInstructionQueue<Impl>::squash(ThreadID tid) 11891060SN/A{ 11902292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 11912292SN/A "the IQ.\n", tid); 11921060SN/A 11931060SN/A // Read instruction sequence number of last instruction out of the 11941060SN/A // time buffer. 11952292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 11961060SN/A 119710797Sbrandon.potter@amd.com doSquash(tid); 11981061SN/A 11991061SN/A // Also tell the memory dependence unit to squash. 12002292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 12011060SN/A} 12021060SN/A 12031061SN/Atemplate <class Impl> 12041061SN/Avoid 12056221Snate@binkert.orgInstructionQueue<Impl>::doSquash(ThreadID tid) 12061061SN/A{ 12072326SN/A // Start at the tail. 12082326SN/A ListIt squash_it = instList[tid].end(); 12092326SN/A --squash_it; 12101061SN/A 12112292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 12122292SN/A tid, squashedSeqNum[tid]); 12131061SN/A 12141061SN/A // Squash any instructions younger than the squashed sequence number 12151061SN/A // given. 12162326SN/A while (squash_it != instList[tid].end() && 12172326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 12182292SN/A 12192326SN/A DynInstPtr squashed_inst = (*squash_it); 122012110SRekai.GonzalezAlberquilla@arm.com if (squashed_inst->isFloating()) { 122112110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 122212110SRekai.GonzalezAlberquilla@arm.com } else if (squashed_inst->isVector()) { 122312110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 122412110SRekai.GonzalezAlberquilla@arm.com } else { 122512110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 122612110SRekai.GonzalezAlberquilla@arm.com } 12271061SN/A 12281061SN/A // Only handle the instruction if it actually is in the IQ and 12291061SN/A // hasn't already been squashed in the IQ. 12302292SN/A if (squashed_inst->threadNumber != tid || 12312292SN/A squashed_inst->isSquashedInIQ()) { 12322326SN/A --squash_it; 12332292SN/A continue; 12342292SN/A } 12352292SN/A 12362292SN/A if (!squashed_inst->isIssued() || 12372292SN/A (squashed_inst->isMemRef() && 12389046SAli.Saidi@ARM.com !squashed_inst->memOpDone())) { 12391062SN/A 12407720Sgblack@eecs.umich.edu DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 12417720Sgblack@eecs.umich.edu tid, squashed_inst->seqNum, squashed_inst->pcState()); 12422367SN/A 124310032SGiacomo.Gabrielli@arm.com bool is_acq_rel = squashed_inst->isMemBarrier() && 124410032SGiacomo.Gabrielli@arm.com (squashed_inst->isLoad() || 124510032SGiacomo.Gabrielli@arm.com (squashed_inst->isStore() && 124610032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional())); 124710032SGiacomo.Gabrielli@arm.com 12481061SN/A // Remove the instruction from the dependency list. 124910032SGiacomo.Gabrielli@arm.com if (is_acq_rel || 125010032SGiacomo.Gabrielli@arm.com (!squashed_inst->isNonSpeculative() && 125110032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional() && 125210032SGiacomo.Gabrielli@arm.com !squashed_inst->isMemBarrier() && 125310032SGiacomo.Gabrielli@arm.com !squashed_inst->isWriteBarrier())) { 12541061SN/A 12551061SN/A for (int src_reg_idx = 0; 12561681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 12571061SN/A src_reg_idx++) 12581061SN/A { 125912105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = 12601061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 12611061SN/A 12622326SN/A // Only remove it from the dependency graph if it 12632326SN/A // was placed there in the first place. 12642326SN/A 12652326SN/A // Instead of doing a linked list traversal, we 12662326SN/A // can just remove these squashed instructions 12672326SN/A // either at issue time, or when the register is 12682326SN/A // overwritten. The only downside to this is it 12692326SN/A // leaves more room for error. 12702292SN/A 12711061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 127212105Snathanael.premillieu@arm.com !src_reg->isFixedMapping()) { 127312106SRekai.GonzalezAlberquilla@arm.com dependGraph.remove(src_reg->flatIndex(), 127412106SRekai.GonzalezAlberquilla@arm.com squashed_inst); 12751061SN/A } 12761062SN/A 12772292SN/A 12781062SN/A ++iqSquashedOperandsExamined; 12791061SN/A } 12804033Sktlim@umich.edu } else if (!squashed_inst->isStoreConditional() || 12814033Sktlim@umich.edu !squashed_inst->isCompleted()) { 12822292SN/A NonSpecMapIt ns_inst_it = 12832292SN/A nonSpecInsts.find(squashed_inst->seqNum); 12848275SAli.Saidi@ARM.com 128510017Sandreas.hansson@arm.com // we remove non-speculative instructions from 128610017Sandreas.hansson@arm.com // nonSpecInsts already when they are ready, and so we 128710017Sandreas.hansson@arm.com // cannot always expect to find them 12884033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 128910017Sandreas.hansson@arm.com // loads that became ready but stalled on a 129010017Sandreas.hansson@arm.com // blocked cache are alreayd removed from 129110017Sandreas.hansson@arm.com // nonSpecInsts, and have not faulted 129210017Sandreas.hansson@arm.com assert(squashed_inst->getFault() != NoFault || 129310017Sandreas.hansson@arm.com squashed_inst->isMemRef()); 12944033Sktlim@umich.edu } else { 12951062SN/A 12964033Sktlim@umich.edu (*ns_inst_it).second = NULL; 12971681SN/A 12984033Sktlim@umich.edu nonSpecInsts.erase(ns_inst_it); 12991062SN/A 13004033Sktlim@umich.edu ++iqSquashedNonSpecRemoved; 13014033Sktlim@umich.edu } 13021061SN/A } 13031061SN/A 13041061SN/A // Might want to also clear out the head of the dependency graph. 13051061SN/A 13061061SN/A // Mark it as squashed within the IQ. 13071061SN/A squashed_inst->setSquashedInIQ(); 13081061SN/A 13092292SN/A // @todo: Remove this hack where several statuses are set so the 13102292SN/A // inst will flow through the rest of the pipeline. 13111681SN/A squashed_inst->setIssued(); 13121681SN/A squashed_inst->setCanCommit(); 13132731Sktlim@umich.edu squashed_inst->clearInIQ(); 13142292SN/A 13152292SN/A //Update Thread IQ Count 13162292SN/A count[squashed_inst->threadNumber]--; 13171681SN/A 13181681SN/A ++freeEntries; 13191061SN/A } 13201061SN/A 13212326SN/A instList[tid].erase(squash_it--); 13221062SN/A ++iqSquashedInstsExamined; 13231061SN/A } 13241060SN/A} 13251060SN/A 13261061SN/Atemplate <class Impl> 13271060SN/Abool 13281061SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 13291060SN/A{ 13301060SN/A // Loop through the instruction's source registers, adding 13311060SN/A // them to the dependency list if they are not ready. 13321060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 13331060SN/A bool return_val = false; 13341060SN/A 13351060SN/A for (int src_reg_idx = 0; 13361060SN/A src_reg_idx < total_src_regs; 13371060SN/A src_reg_idx++) 13381060SN/A { 13391060SN/A // Only add it to the dependency graph if it's not ready. 13401060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 134112105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 13421060SN/A 13431060SN/A // Check the IQ's scoreboard to make sure the register 13441060SN/A // hasn't become ready while the instruction was in flight 13451060SN/A // between stages. Only if it really isn't ready should 13461060SN/A // it be added to the dependency graph. 134712105Snathanael.premillieu@arm.com if (src_reg->isFixedMapping()) { 13481061SN/A continue; 134912106SRekai.GonzalezAlberquilla@arm.com } else if (!regScoreboard[src_reg->flatIndex()]) { 135012105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13511060SN/A "is being added to the dependency chain.\n", 135212106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 135312106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 13541060SN/A 135512106SRekai.GonzalezAlberquilla@arm.com dependGraph.insert(src_reg->flatIndex(), new_inst); 13561060SN/A 13571060SN/A // Change the return value to indicate that something 13581060SN/A // was added to the dependency graph. 13591060SN/A return_val = true; 13601060SN/A } else { 136112105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13621060SN/A "became ready before it reached the IQ.\n", 136312106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 136412106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 13651060SN/A // Mark a register ready within the instruction. 13662326SN/A new_inst->markSrcRegReady(src_reg_idx); 13671060SN/A } 13681060SN/A } 13691060SN/A } 13701060SN/A 13711060SN/A return return_val; 13721060SN/A} 13731060SN/A 13741061SN/Atemplate <class Impl> 13751060SN/Avoid 13762326SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 13771060SN/A{ 13782326SN/A // Nothing really needs to be marked when an instruction becomes 13792326SN/A // the producer of a register's value, but for convenience a ptr 13802326SN/A // to the producing instruction will be placed in the head node of 13812326SN/A // the dependency links. 13821060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 13831060SN/A 13841060SN/A for (int dest_reg_idx = 0; 13851060SN/A dest_reg_idx < total_dest_regs; 13861060SN/A dest_reg_idx++) 13871060SN/A { 138812105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 13891061SN/A 139012105Snathanael.premillieu@arm.com // Some registers have fixed mapping, and there is no need to track 13911061SN/A // dependencies as these instructions must be executed at commit. 139212105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 13931061SN/A continue; 13941060SN/A } 13951060SN/A 139612106SRekai.GonzalezAlberquilla@arm.com if (!dependGraph.empty(dest_reg->flatIndex())) { 13972326SN/A dependGraph.dump(); 139812105Snathanael.premillieu@arm.com panic("Dependency graph %i (%s) (flat: %i) not empty!", 139912106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className(), 140012106SRekai.GonzalezAlberquilla@arm.com dest_reg->flatIndex()); 14012064SN/A } 14021062SN/A 140312106SRekai.GonzalezAlberquilla@arm.com dependGraph.setInst(dest_reg->flatIndex(), new_inst); 14041062SN/A 14051060SN/A // Mark the scoreboard to say it's not yet ready. 140612106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = false; 14071060SN/A } 14081060SN/A} 14091060SN/A 14101061SN/Atemplate <class Impl> 14111060SN/Avoid 14121061SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 14131060SN/A{ 14142326SN/A // If the instruction now has all of its source registers 14151060SN/A // available, then add it to the list of ready instructions. 14161060SN/A if (inst->readyToIssue()) { 14171061SN/A 14181060SN/A //Add the instruction to the proper ready list. 14192292SN/A if (inst->isMemRef()) { 14201061SN/A 14212292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 14221061SN/A 14231062SN/A // Message to the mem dependence unit that this instruction has 14241062SN/A // its registers ready. 14252292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 14261062SN/A 14272292SN/A return; 14282292SN/A } 14291062SN/A 14302292SN/A OpClass op_class = inst->opClass(); 14311061SN/A 14322292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 14337720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 14347720Sgblack@eecs.umich.edu inst->pcState(), op_class, inst->seqNum); 14351061SN/A 14362292SN/A readyInsts[op_class].push(inst); 14371061SN/A 14382326SN/A // Will need to reorder the list if either a queue is not on the list, 14392326SN/A // or it has an older instruction than last time. 14402326SN/A if (!queueOnList[op_class]) { 14412326SN/A addToOrderList(op_class); 14422326SN/A } else if (readyInsts[op_class].top()->seqNum < 14432326SN/A (*readyIt[op_class]).oldestInst) { 14442326SN/A listOrder.erase(readyIt[op_class]); 14452326SN/A addToOrderList(op_class); 14461060SN/A } 14471060SN/A } 14481060SN/A} 14491060SN/A 14501061SN/Atemplate <class Impl> 14511061SN/Aint 14521061SN/AInstructionQueue<Impl>::countInsts() 14531061SN/A{ 14542698Sktlim@umich.edu#if 0 14552292SN/A //ksewell:This works but definitely could use a cleaner write 14562292SN/A //with a more intuitive way of counting. Right now it's 14572292SN/A //just brute force .... 14582698Sktlim@umich.edu // Change the #if if you want to use this method. 14591061SN/A int total_insts = 0; 14601061SN/A 14616221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 14626221Snate@binkert.org ListIt count_it = instList[tid].begin(); 14631681SN/A 14646221Snate@binkert.org while (count_it != instList[tid].end()) { 14652292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 14662292SN/A if (!(*count_it)->isIssued()) { 14672292SN/A ++total_insts; 14682292SN/A } else if ((*count_it)->isMemRef() && 14692292SN/A !(*count_it)->memOpDone) { 14702292SN/A // Loads that have not been marked as executed still count 14712292SN/A // towards the total instructions. 14722292SN/A ++total_insts; 14732292SN/A } 14742292SN/A } 14752292SN/A 14762292SN/A ++count_it; 14771061SN/A } 14781061SN/A } 14791061SN/A 14801061SN/A return total_insts; 14812292SN/A#else 14822292SN/A return numEntries - freeEntries; 14832292SN/A#endif 14841681SN/A} 14851681SN/A 14861681SN/Atemplate <class Impl> 14871681SN/Avoid 14881061SN/AInstructionQueue<Impl>::dumpLists() 14891061SN/A{ 14902292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 14912292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 14921061SN/A 14932292SN/A cprintf("\n"); 14942292SN/A } 14951061SN/A 14961061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 14971061SN/A 14982292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 14992292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 15001061SN/A 15011061SN/A cprintf("Non speculative list: "); 15021061SN/A 15032292SN/A while (non_spec_it != non_spec_end_it) { 15047720Sgblack@eecs.umich.edu cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 15052292SN/A (*non_spec_it).second->seqNum); 15061061SN/A ++non_spec_it; 15071061SN/A } 15081061SN/A 15091061SN/A cprintf("\n"); 15101061SN/A 15112292SN/A ListOrderIt list_order_it = listOrder.begin(); 15122292SN/A ListOrderIt list_order_end_it = listOrder.end(); 15132292SN/A int i = 1; 15142292SN/A 15152292SN/A cprintf("List order: "); 15162292SN/A 15172292SN/A while (list_order_it != list_order_end_it) { 15182292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 15192292SN/A (*list_order_it).oldestInst); 15202292SN/A 15212292SN/A ++list_order_it; 15222292SN/A ++i; 15232292SN/A } 15242292SN/A 15252292SN/A cprintf("\n"); 15261061SN/A} 15272292SN/A 15282292SN/A 15292292SN/Atemplate <class Impl> 15302292SN/Avoid 15312292SN/AInstructionQueue<Impl>::dumpInsts() 15322292SN/A{ 15336221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 15342292SN/A int num = 0; 15352292SN/A int valid_num = 0; 15366221Snate@binkert.org ListIt inst_list_it = instList[tid].begin(); 15372292SN/A 15386221Snate@binkert.org while (inst_list_it != instList[tid].end()) { 15396221Snate@binkert.org cprintf("Instruction:%i\n", num); 15402292SN/A if (!(*inst_list_it)->isSquashed()) { 15412292SN/A if (!(*inst_list_it)->isIssued()) { 15422292SN/A ++valid_num; 15432292SN/A cprintf("Count:%i\n", valid_num); 15442292SN/A } else if ((*inst_list_it)->isMemRef() && 15459046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 15462326SN/A // Loads that have not been marked as executed 15472326SN/A // still count towards the total instructions. 15482292SN/A ++valid_num; 15492292SN/A cprintf("Count:%i\n", valid_num); 15502292SN/A } 15512292SN/A } 15522292SN/A 15537720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 15542292SN/A "Issued:%i\nSquashed:%i\n", 15557720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 15562292SN/A (*inst_list_it)->seqNum, 15572292SN/A (*inst_list_it)->threadNumber, 15582292SN/A (*inst_list_it)->isIssued(), 15592292SN/A (*inst_list_it)->isSquashed()); 15602292SN/A 15612292SN/A if ((*inst_list_it)->isMemRef()) { 15629046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 15632292SN/A } 15642292SN/A 15652292SN/A cprintf("\n"); 15662292SN/A 15672292SN/A inst_list_it++; 15682292SN/A ++num; 15692292SN/A } 15702292SN/A } 15712348SN/A 15722348SN/A cprintf("Insts to Execute list:\n"); 15732348SN/A 15742348SN/A int num = 0; 15752348SN/A int valid_num = 0; 15762348SN/A ListIt inst_list_it = instsToExecute.begin(); 15772348SN/A 15782348SN/A while (inst_list_it != instsToExecute.end()) 15792348SN/A { 15802348SN/A cprintf("Instruction:%i\n", 15812348SN/A num); 15822348SN/A if (!(*inst_list_it)->isSquashed()) { 15832348SN/A if (!(*inst_list_it)->isIssued()) { 15842348SN/A ++valid_num; 15852348SN/A cprintf("Count:%i\n", valid_num); 15862348SN/A } else if ((*inst_list_it)->isMemRef() && 15879046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 15882348SN/A // Loads that have not been marked as executed 15892348SN/A // still count towards the total instructions. 15902348SN/A ++valid_num; 15912348SN/A cprintf("Count:%i\n", valid_num); 15922348SN/A } 15932348SN/A } 15942348SN/A 15957720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 15962348SN/A "Issued:%i\nSquashed:%i\n", 15977720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 15982348SN/A (*inst_list_it)->seqNum, 15992348SN/A (*inst_list_it)->threadNumber, 16002348SN/A (*inst_list_it)->isIssued(), 16012348SN/A (*inst_list_it)->isSquashed()); 16022348SN/A 16032348SN/A if ((*inst_list_it)->isMemRef()) { 16049046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 16052348SN/A } 16062348SN/A 16072348SN/A cprintf("\n"); 16082348SN/A 16092348SN/A inst_list_it++; 16102348SN/A ++num; 16112348SN/A } 16122292SN/A} 16139944Smatt.horsnell@ARM.com 16149944Smatt.horsnell@ARM.com#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1615