iew_impl.hh revision 8073
11689SN/A/* 27598Sminkyu.jeong@arm.com * Copyright (c) 2010 ARM Limited 37598Sminkyu.jeong@arm.com * All rights reserved. 47598Sminkyu.jeong@arm.com * 57598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137598Sminkyu.jeong@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 431060SN/A// @todo: Fix the instantaneous communication among all the stages within 441060SN/A// iew. There's a clear delay between issue and execute, yet backwards 451689SN/A// communication happens simultaneously. 461060SN/A 471060SN/A#include <queue> 481060SN/A 497813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 512292SN/A#include "cpu/o3/fu_pool.hh" 521717SN/A#include "cpu/o3/iew.hh" 535529Snate@binkert.org#include "params/DerivO3CPU.hh" 541060SN/A 556221Snate@binkert.orgusing namespace std; 566221Snate@binkert.org 571681SN/Atemplate<class Impl> 585529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 592873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 604329Sktlim@umich.edu cpu(_cpu), 614329Sktlim@umich.edu instQueue(_cpu, this, params), 624329Sktlim@umich.edu ldstQueue(_cpu, this, params), 632292SN/A fuPool(params->fuPool), 642292SN/A commitToIEWDelay(params->commitToIEWDelay), 652292SN/A renameToIEWDelay(params->renameToIEWDelay), 662292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 672820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 682292SN/A issueWidth(params->issueWidth), 692820Sktlim@umich.edu wbOutstanding(0), 702820Sktlim@umich.edu wbWidth(params->wbWidth), 715529Snate@binkert.org numThreads(params->numThreads), 722307SN/A switchedOut(false) 731060SN/A{ 742292SN/A _status = Active; 752292SN/A exeStatus = Running; 762292SN/A wbStatus = Idle; 771060SN/A 781060SN/A // Setup wire to read instructions coming from issue. 791060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 801060SN/A 811060SN/A // Instruction queue needs the queue between issue and execute. 821060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 831681SN/A 846221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 856221Snate@binkert.org dispatchStatus[tid] = Running; 866221Snate@binkert.org stalls[tid].commit = false; 876221Snate@binkert.org fetchRedirect[tid] = false; 882292SN/A } 892292SN/A 902820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 912820Sktlim@umich.edu 922292SN/A updateLSQNextCycle = false; 932292SN/A 942820Sktlim@umich.edu ableToIssue = true; 952820Sktlim@umich.edu 962292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 972292SN/A} 982292SN/A 992292SN/Atemplate <class Impl> 1002292SN/Astd::string 1012292SN/ADefaultIEW<Impl>::name() const 1022292SN/A{ 1032292SN/A return cpu->name() + ".iew"; 1041060SN/A} 1051060SN/A 1061681SN/Atemplate <class Impl> 1071062SN/Avoid 1082292SN/ADefaultIEW<Impl>::regStats() 1091062SN/A{ 1102301SN/A using namespace Stats; 1112301SN/A 1121062SN/A instQueue.regStats(); 1132727Sktlim@umich.edu ldstQueue.regStats(); 1141062SN/A 1151062SN/A iewIdleCycles 1161062SN/A .name(name() + ".iewIdleCycles") 1171062SN/A .desc("Number of cycles IEW is idle"); 1181062SN/A 1191062SN/A iewSquashCycles 1201062SN/A .name(name() + ".iewSquashCycles") 1211062SN/A .desc("Number of cycles IEW is squashing"); 1221062SN/A 1231062SN/A iewBlockCycles 1241062SN/A .name(name() + ".iewBlockCycles") 1251062SN/A .desc("Number of cycles IEW is blocking"); 1261062SN/A 1271062SN/A iewUnblockCycles 1281062SN/A .name(name() + ".iewUnblockCycles") 1291062SN/A .desc("Number of cycles IEW is unblocking"); 1301062SN/A 1311062SN/A iewDispatchedInsts 1321062SN/A .name(name() + ".iewDispatchedInsts") 1331062SN/A .desc("Number of instructions dispatched to IQ"); 1341062SN/A 1351062SN/A iewDispSquashedInsts 1361062SN/A .name(name() + ".iewDispSquashedInsts") 1371062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1381062SN/A 1391062SN/A iewDispLoadInsts 1401062SN/A .name(name() + ".iewDispLoadInsts") 1411062SN/A .desc("Number of dispatched load instructions"); 1421062SN/A 1431062SN/A iewDispStoreInsts 1441062SN/A .name(name() + ".iewDispStoreInsts") 1451062SN/A .desc("Number of dispatched store instructions"); 1461062SN/A 1471062SN/A iewDispNonSpecInsts 1481062SN/A .name(name() + ".iewDispNonSpecInsts") 1491062SN/A .desc("Number of dispatched non-speculative instructions"); 1501062SN/A 1511062SN/A iewIQFullEvents 1521062SN/A .name(name() + ".iewIQFullEvents") 1531062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1541062SN/A 1552292SN/A iewLSQFullEvents 1562292SN/A .name(name() + ".iewLSQFullEvents") 1572292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1582292SN/A 1591062SN/A memOrderViolationEvents 1601062SN/A .name(name() + ".memOrderViolationEvents") 1611062SN/A .desc("Number of memory order violations"); 1621062SN/A 1631062SN/A predictedTakenIncorrect 1641062SN/A .name(name() + ".predictedTakenIncorrect") 1651062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1662292SN/A 1672292SN/A predictedNotTakenIncorrect 1682292SN/A .name(name() + ".predictedNotTakenIncorrect") 1692292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1702292SN/A 1712292SN/A branchMispredicts 1722292SN/A .name(name() + ".branchMispredicts") 1732292SN/A .desc("Number of branch mispredicts detected at execute"); 1742292SN/A 1752292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1762301SN/A 1772727Sktlim@umich.edu iewExecutedInsts 1782353SN/A .name(name() + ".iewExecutedInsts") 1792727Sktlim@umich.edu .desc("Number of executed instructions"); 1802727Sktlim@umich.edu 1812727Sktlim@umich.edu iewExecLoadInsts 1826221Snate@binkert.org .init(cpu->numThreads) 1832353SN/A .name(name() + ".iewExecLoadInsts") 1842727Sktlim@umich.edu .desc("Number of load instructions executed") 1852727Sktlim@umich.edu .flags(total); 1862727Sktlim@umich.edu 1872727Sktlim@umich.edu iewExecSquashedInsts 1882353SN/A .name(name() + ".iewExecSquashedInsts") 1892727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1902727Sktlim@umich.edu 1912727Sktlim@umich.edu iewExecutedSwp 1926221Snate@binkert.org .init(cpu->numThreads) 1932301SN/A .name(name() + ".EXEC:swp") 1942301SN/A .desc("number of swp insts executed") 1952727Sktlim@umich.edu .flags(total); 1962301SN/A 1972727Sktlim@umich.edu iewExecutedNop 1986221Snate@binkert.org .init(cpu->numThreads) 1992301SN/A .name(name() + ".EXEC:nop") 2002301SN/A .desc("number of nop insts executed") 2012727Sktlim@umich.edu .flags(total); 2022301SN/A 2032727Sktlim@umich.edu iewExecutedRefs 2046221Snate@binkert.org .init(cpu->numThreads) 2052301SN/A .name(name() + ".EXEC:refs") 2062301SN/A .desc("number of memory reference insts executed") 2072727Sktlim@umich.edu .flags(total); 2082301SN/A 2092727Sktlim@umich.edu iewExecutedBranches 2106221Snate@binkert.org .init(cpu->numThreads) 2112301SN/A .name(name() + ".EXEC:branches") 2122301SN/A .desc("Number of branches executed") 2132727Sktlim@umich.edu .flags(total); 2142301SN/A 2152301SN/A iewExecStoreInsts 2162301SN/A .name(name() + ".EXEC:stores") 2172301SN/A .desc("Number of stores executed") 2182727Sktlim@umich.edu .flags(total); 2192727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2202727Sktlim@umich.edu 2212727Sktlim@umich.edu iewExecRate 2222727Sktlim@umich.edu .name(name() + ".EXEC:rate") 2232727Sktlim@umich.edu .desc("Inst execution rate") 2242727Sktlim@umich.edu .flags(total); 2252727Sktlim@umich.edu 2262727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2272301SN/A 2282301SN/A iewInstsToCommit 2296221Snate@binkert.org .init(cpu->numThreads) 2302301SN/A .name(name() + ".WB:sent") 2312301SN/A .desc("cumulative count of insts sent to commit") 2322727Sktlim@umich.edu .flags(total); 2332301SN/A 2342326SN/A writebackCount 2356221Snate@binkert.org .init(cpu->numThreads) 2362301SN/A .name(name() + ".WB:count") 2372301SN/A .desc("cumulative count of insts written-back") 2382727Sktlim@umich.edu .flags(total); 2392301SN/A 2402326SN/A producerInst 2416221Snate@binkert.org .init(cpu->numThreads) 2422301SN/A .name(name() + ".WB:producers") 2432301SN/A .desc("num instructions producing a value") 2442727Sktlim@umich.edu .flags(total); 2452301SN/A 2462326SN/A consumerInst 2476221Snate@binkert.org .init(cpu->numThreads) 2482301SN/A .name(name() + ".WB:consumers") 2492301SN/A .desc("num instructions consuming a value") 2502727Sktlim@umich.edu .flags(total); 2512301SN/A 2522326SN/A wbPenalized 2536221Snate@binkert.org .init(cpu->numThreads) 2542301SN/A .name(name() + ".WB:penalized") 2552301SN/A .desc("number of instrctions required to write to 'other' IQ") 2562727Sktlim@umich.edu .flags(total); 2572301SN/A 2582326SN/A wbPenalizedRate 2592301SN/A .name(name() + ".WB:penalized_rate") 2602301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2612727Sktlim@umich.edu .flags(total); 2622301SN/A 2632326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2642301SN/A 2652326SN/A wbFanout 2662301SN/A .name(name() + ".WB:fanout") 2672301SN/A .desc("average fanout of values written-back") 2682727Sktlim@umich.edu .flags(total); 2692301SN/A 2702326SN/A wbFanout = producerInst / consumerInst; 2712301SN/A 2722326SN/A wbRate 2732301SN/A .name(name() + ".WB:rate") 2742301SN/A .desc("insts written-back per cycle") 2752727Sktlim@umich.edu .flags(total); 2762326SN/A wbRate = writebackCount / cpu->numCycles; 2771062SN/A} 2781062SN/A 2791681SN/Atemplate<class Impl> 2801060SN/Avoid 2812292SN/ADefaultIEW<Impl>::initStage() 2821060SN/A{ 2836221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2842292SN/A toRename->iewInfo[tid].usedIQ = true; 2852292SN/A toRename->iewInfo[tid].freeIQEntries = 2862292SN/A instQueue.numFreeEntries(tid); 2872292SN/A 2882292SN/A toRename->iewInfo[tid].usedLSQ = true; 2892292SN/A toRename->iewInfo[tid].freeLSQEntries = 2902292SN/A ldstQueue.numFreeEntries(tid); 2912292SN/A } 2922292SN/A 2932733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 2941060SN/A} 2951060SN/A 2961681SN/Atemplate<class Impl> 2971060SN/Avoid 2982292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2991060SN/A{ 3001060SN/A timeBuffer = tb_ptr; 3011060SN/A 3021060SN/A // Setup wire to read information from time buffer, from commit. 3031060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3041060SN/A 3051060SN/A // Setup wire to write information back to previous stages. 3061060SN/A toRename = timeBuffer->getWire(0); 3071060SN/A 3082292SN/A toFetch = timeBuffer->getWire(0); 3092292SN/A 3101060SN/A // Instruction queue also needs main time buffer. 3111060SN/A instQueue.setTimeBuffer(tb_ptr); 3121060SN/A} 3131060SN/A 3141681SN/Atemplate<class Impl> 3151060SN/Avoid 3162292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3171060SN/A{ 3181060SN/A renameQueue = rq_ptr; 3191060SN/A 3201060SN/A // Setup wire to read information from rename queue. 3211060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3221060SN/A} 3231060SN/A 3241681SN/Atemplate<class Impl> 3251060SN/Avoid 3262292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3271060SN/A{ 3281060SN/A iewQueue = iq_ptr; 3291060SN/A 3301060SN/A // Setup wire to write instructions to commit. 3311060SN/A toCommit = iewQueue->getWire(0); 3321060SN/A} 3331060SN/A 3341681SN/Atemplate<class Impl> 3351060SN/Avoid 3366221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3371060SN/A{ 3382292SN/A activeThreads = at_ptr; 3392292SN/A 3402292SN/A ldstQueue.setActiveThreads(at_ptr); 3412292SN/A instQueue.setActiveThreads(at_ptr); 3421060SN/A} 3431060SN/A 3441681SN/Atemplate<class Impl> 3451060SN/Avoid 3462292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3471060SN/A{ 3482292SN/A scoreboard = sb_ptr; 3491060SN/A} 3501060SN/A 3512307SN/Atemplate <class Impl> 3522863Sktlim@umich.edubool 3532843Sktlim@umich.eduDefaultIEW<Impl>::drain() 3542307SN/A{ 3552843Sktlim@umich.edu // IEW is ready to drain at any time. 3562843Sktlim@umich.edu cpu->signalDrained(); 3572863Sktlim@umich.edu return true; 3581681SN/A} 3591681SN/A 3602316SN/Atemplate <class Impl> 3611681SN/Avoid 3622843Sktlim@umich.eduDefaultIEW<Impl>::resume() 3632843Sktlim@umich.edu{ 3642843Sktlim@umich.edu} 3652843Sktlim@umich.edu 3662843Sktlim@umich.edutemplate <class Impl> 3672843Sktlim@umich.eduvoid 3682843Sktlim@umich.eduDefaultIEW<Impl>::switchOut() 3691681SN/A{ 3702348SN/A // Clear any state. 3712307SN/A switchedOut = true; 3722367SN/A assert(insts[0].empty()); 3732367SN/A assert(skidBuffer[0].empty()); 3741681SN/A 3752307SN/A instQueue.switchOut(); 3762307SN/A ldstQueue.switchOut(); 3772307SN/A fuPool->switchOut(); 3782307SN/A 3796221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3806221Snate@binkert.org while (!insts[tid].empty()) 3816221Snate@binkert.org insts[tid].pop(); 3826221Snate@binkert.org while (!skidBuffer[tid].empty()) 3836221Snate@binkert.org skidBuffer[tid].pop(); 3842307SN/A } 3851681SN/A} 3861681SN/A 3872307SN/Atemplate <class Impl> 3881681SN/Avoid 3892307SN/ADefaultIEW<Impl>::takeOverFrom() 3901060SN/A{ 3912348SN/A // Reset all state. 3922307SN/A _status = Active; 3932307SN/A exeStatus = Running; 3942307SN/A wbStatus = Idle; 3952307SN/A switchedOut = false; 3961060SN/A 3972307SN/A instQueue.takeOverFrom(); 3982307SN/A ldstQueue.takeOverFrom(); 3992307SN/A fuPool->takeOverFrom(); 4001060SN/A 4012307SN/A initStage(); 4022307SN/A cpu->activityThisCycle(); 4031060SN/A 4046221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4056221Snate@binkert.org dispatchStatus[tid] = Running; 4066221Snate@binkert.org stalls[tid].commit = false; 4076221Snate@binkert.org fetchRedirect[tid] = false; 4082307SN/A } 4091060SN/A 4102307SN/A updateLSQNextCycle = false; 4112307SN/A 4122873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4132307SN/A issueToExecQueue.advance(); 4141060SN/A } 4151060SN/A} 4161060SN/A 4171681SN/Atemplate<class Impl> 4181060SN/Avoid 4196221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4202107SN/A{ 4216221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4222107SN/A 4232292SN/A // Tell the IQ to start squashing. 4242292SN/A instQueue.squash(tid); 4252107SN/A 4262292SN/A // Tell the LDSTQ to start squashing. 4272326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4282292SN/A updatedQueues = true; 4292107SN/A 4302292SN/A // Clear the skid buffer in case it has any data in it. 4312935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4324632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4332935Sksewell@umich.edu 4342292SN/A while (!skidBuffer[tid].empty()) { 4352292SN/A if (skidBuffer[tid].front()->isLoad() || 4362292SN/A skidBuffer[tid].front()->isStore() ) { 4372292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4382292SN/A } 4392107SN/A 4402292SN/A toRename->iewInfo[tid].dispatched++; 4412107SN/A 4422292SN/A skidBuffer[tid].pop(); 4432292SN/A } 4442107SN/A 4452702Sktlim@umich.edu emptyRenameInsts(tid); 4462107SN/A} 4472107SN/A 4482107SN/Atemplate<class Impl> 4492107SN/Avoid 4506221Snate@binkert.orgDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4512292SN/A{ 4527720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4537720Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4542292SN/A 4557852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 4567852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4577852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4587852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4597852SMatt.Horsnell@arm.com toCommit->mispredPC[tid] = inst->instAddr(); 4607852SMatt.Horsnell@arm.com toCommit->branchMispredict[tid] = true; 4617852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 4622935Sksewell@umich.edu 4637852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 4647852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 4652292SN/A 4667852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4677852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 4687852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 4692292SN/A 4707852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 4717852SMatt.Horsnell@arm.com } 4727852SMatt.Horsnell@arm.com 4732292SN/A} 4742292SN/A 4752292SN/Atemplate<class Impl> 4762292SN/Avoid 4776221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 4782292SN/A{ 4792292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4807720Sgblack@eecs.umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4812292SN/A 4827852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 4837852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4847852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4857852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4867852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 4877852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 4887852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4897852SMatt.Horsnell@arm.com toCommit->branchMispredict[tid] = false; 4902292SN/A 4917852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 4922292SN/A 4937852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 4947852SMatt.Horsnell@arm.com } 4952292SN/A} 4962292SN/A 4972292SN/Atemplate<class Impl> 4982292SN/Avoid 4996221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5002292SN/A{ 5012292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5027720Sgblack@eecs.umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5037852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 5047852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 5057852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 5062292SN/A 5077852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5087852SMatt.Horsnell@arm.com toCommit->pc[tid] = inst->pcState(); 5097852SMatt.Horsnell@arm.com toCommit->branchMispredict[tid] = false; 5102292SN/A 5117852SMatt.Horsnell@arm.com // Must include the broadcasted SN in the squash. 5127852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = true; 5132292SN/A 5147852SMatt.Horsnell@arm.com ldstQueue.setLoadBlockedHandled(tid); 5152292SN/A 5167852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5177852SMatt.Horsnell@arm.com } 5182292SN/A} 5192292SN/A 5202292SN/Atemplate<class Impl> 5212292SN/Avoid 5226221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5232292SN/A{ 5242292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5252292SN/A 5262292SN/A if (dispatchStatus[tid] != Blocked && 5272292SN/A dispatchStatus[tid] != Unblocking) { 5282292SN/A toRename->iewBlock[tid] = true; 5292292SN/A wroteToTimeBuffer = true; 5302292SN/A } 5312292SN/A 5322292SN/A // Add the current inputs to the skid buffer so they can be 5332292SN/A // reprocessed when this stage unblocks. 5342292SN/A skidInsert(tid); 5352292SN/A 5362292SN/A dispatchStatus[tid] = Blocked; 5372292SN/A} 5382292SN/A 5392292SN/Atemplate<class Impl> 5402292SN/Avoid 5416221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5422292SN/A{ 5432292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5442292SN/A "buffer %u.\n",tid, tid); 5452292SN/A 5462292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5472292SN/A // Also switch status to running. 5482292SN/A if (skidBuffer[tid].empty()) { 5492292SN/A toRename->iewUnblock[tid] = true; 5502292SN/A wroteToTimeBuffer = true; 5512292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5522292SN/A dispatchStatus[tid] = Running; 5532292SN/A } 5542292SN/A} 5552292SN/A 5562292SN/Atemplate<class Impl> 5572292SN/Avoid 5582292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5591060SN/A{ 5601681SN/A instQueue.wakeDependents(inst); 5611060SN/A} 5621060SN/A 5632292SN/Atemplate<class Impl> 5642292SN/Avoid 5652292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5662292SN/A{ 5672292SN/A instQueue.rescheduleMemInst(inst); 5682292SN/A} 5691681SN/A 5701681SN/Atemplate<class Impl> 5711060SN/Avoid 5722292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5731060SN/A{ 5742292SN/A instQueue.replayMemInst(inst); 5752292SN/A} 5761060SN/A 5772292SN/Atemplate<class Impl> 5782292SN/Avoid 5792292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5802292SN/A{ 5813221Sktlim@umich.edu // This function should not be called after writebackInsts in a 5823221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 5833221Sktlim@umich.edu // being added to the queue to commit without being processed by 5843221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 5853221Sktlim@umich.edu 5862292SN/A // First check the time slot that this instruction will write 5872292SN/A // to. If there are free write ports at the time, then go ahead 5882292SN/A // and write the instruction to that time. If there are not, 5892292SN/A // keep looking back to see where's the first time there's a 5902326SN/A // free slot. 5912292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5922292SN/A ++wbNumInst; 5932820Sktlim@umich.edu if (wbNumInst == wbWidth) { 5942292SN/A ++wbCycle; 5952292SN/A wbNumInst = 0; 5962292SN/A } 5972292SN/A 5982353SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 5992292SN/A } 6002292SN/A 6012353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6022353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6032292SN/A // Add finished instruction to queue to commit. 6042292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6052292SN/A (*iewQueue)[wbCycle].size++; 6062292SN/A} 6072292SN/A 6082292SN/Atemplate <class Impl> 6092292SN/Aunsigned 6102292SN/ADefaultIEW<Impl>::validInstsFromRename() 6112292SN/A{ 6122292SN/A unsigned inst_count = 0; 6132292SN/A 6142292SN/A for (int i=0; i<fromRename->size; i++) { 6152731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6162292SN/A inst_count++; 6172292SN/A } 6182292SN/A 6192292SN/A return inst_count; 6202292SN/A} 6212292SN/A 6222292SN/Atemplate<class Impl> 6232292SN/Avoid 6246221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6252292SN/A{ 6262292SN/A DynInstPtr inst = NULL; 6272292SN/A 6282292SN/A while (!insts[tid].empty()) { 6292292SN/A inst = insts[tid].front(); 6302292SN/A 6312292SN/A insts[tid].pop(); 6322292SN/A 6337720Sgblack@eecs.umich.edu DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6342292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6357720Sgblack@eecs.umich.edu inst->pcState(),tid); 6362292SN/A 6372292SN/A skidBuffer[tid].push(inst); 6382292SN/A } 6392292SN/A 6402292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6412292SN/A "Skidbuffer Exceeded Max Size"); 6422292SN/A} 6432292SN/A 6442292SN/Atemplate<class Impl> 6452292SN/Aint 6462292SN/ADefaultIEW<Impl>::skidCount() 6472292SN/A{ 6482292SN/A int max=0; 6492292SN/A 6506221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6516221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6522292SN/A 6533867Sbinkertn@umich.edu while (threads != end) { 6546221Snate@binkert.org ThreadID tid = *threads++; 6553867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6562292SN/A if (max < thread_count) 6572292SN/A max = thread_count; 6582292SN/A } 6592292SN/A 6602292SN/A return max; 6612292SN/A} 6622292SN/A 6632292SN/Atemplate<class Impl> 6642292SN/Abool 6652292SN/ADefaultIEW<Impl>::skidsEmpty() 6662292SN/A{ 6676221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6686221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6692292SN/A 6703867Sbinkertn@umich.edu while (threads != end) { 6716221Snate@binkert.org ThreadID tid = *threads++; 6723867Sbinkertn@umich.edu 6733867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 6742292SN/A return false; 6752292SN/A } 6762292SN/A 6772292SN/A return true; 6781062SN/A} 6791062SN/A 6801681SN/Atemplate <class Impl> 6811062SN/Avoid 6822292SN/ADefaultIEW<Impl>::updateStatus() 6831062SN/A{ 6842292SN/A bool any_unblocking = false; 6851062SN/A 6866221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6876221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6881062SN/A 6893867Sbinkertn@umich.edu while (threads != end) { 6906221Snate@binkert.org ThreadID tid = *threads++; 6911062SN/A 6922292SN/A if (dispatchStatus[tid] == Unblocking) { 6932292SN/A any_unblocking = true; 6942292SN/A break; 6952292SN/A } 6962292SN/A } 6971062SN/A 6982292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 6992292SN/A // and there's no stores waiting to write back, and dispatch is not 7002292SN/A // unblocking, then there is no internal activity for the IEW stage. 7017897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7022292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7032292SN/A !ldstQueue.willWB() && !any_unblocking) { 7042292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7051062SN/A 7062292SN/A deactivateStage(); 7071062SN/A 7082292SN/A _status = Inactive; 7092292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7102292SN/A ldstQueue.willWB() || 7112292SN/A any_unblocking)) { 7122292SN/A // Otherwise there is internal activity. Set to active. 7132292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7141062SN/A 7152292SN/A activateStage(); 7161062SN/A 7172292SN/A _status = Active; 7181062SN/A } 7191062SN/A} 7201062SN/A 7211681SN/Atemplate <class Impl> 7221062SN/Avoid 7232292SN/ADefaultIEW<Impl>::resetEntries() 7241062SN/A{ 7252292SN/A instQueue.resetEntries(); 7262292SN/A ldstQueue.resetEntries(); 7272292SN/A} 7281062SN/A 7292292SN/Atemplate <class Impl> 7302292SN/Avoid 7316221Snate@binkert.orgDefaultIEW<Impl>::readStallSignals(ThreadID tid) 7322292SN/A{ 7332292SN/A if (fromCommit->commitBlock[tid]) { 7342292SN/A stalls[tid].commit = true; 7352292SN/A } 7361062SN/A 7372292SN/A if (fromCommit->commitUnblock[tid]) { 7382292SN/A assert(stalls[tid].commit); 7392292SN/A stalls[tid].commit = false; 7402292SN/A } 7412292SN/A} 7422292SN/A 7432292SN/Atemplate <class Impl> 7442292SN/Abool 7456221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7462292SN/A{ 7472292SN/A bool ret_val(false); 7482292SN/A 7492292SN/A if (stalls[tid].commit) { 7502292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7512292SN/A ret_val = true; 7522292SN/A } else if (instQueue.isFull(tid)) { 7532292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7542292SN/A ret_val = true; 7552292SN/A } else if (ldstQueue.isFull(tid)) { 7562292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7572292SN/A 7582292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7592292SN/A 7602292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7612292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7622292SN/A } 7632292SN/A 7642292SN/A if (ldstQueue.numStores(tid) > 0) { 7652292SN/A 7662292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7672292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7682292SN/A } 7692292SN/A 7702292SN/A ret_val = true; 7712292SN/A } else if (ldstQueue.isStalled(tid)) { 7722292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7732292SN/A ret_val = true; 7742292SN/A } 7752292SN/A 7762292SN/A return ret_val; 7772292SN/A} 7782292SN/A 7792292SN/Atemplate <class Impl> 7802292SN/Avoid 7816221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7822292SN/A{ 7832292SN/A // Check if there's a squash signal, squash if there is 7842292SN/A // Check stall signals, block if there is. 7852292SN/A // If status was Blocked 7862292SN/A // if so then go to unblocking 7872292SN/A // If status was Squashing 7882292SN/A // check if squashing is not high. Switch to running this cycle. 7892292SN/A 7902292SN/A readStallSignals(tid); 7912292SN/A 7922292SN/A if (fromCommit->commitInfo[tid].squash) { 7932292SN/A squash(tid); 7942292SN/A 7952292SN/A if (dispatchStatus[tid] == Blocked || 7962292SN/A dispatchStatus[tid] == Unblocking) { 7972292SN/A toRename->iewUnblock[tid] = true; 7982292SN/A wroteToTimeBuffer = true; 7992292SN/A } 8002292SN/A 8012292SN/A dispatchStatus[tid] = Squashing; 8022292SN/A fetchRedirect[tid] = false; 8032292SN/A return; 8042292SN/A } 8052292SN/A 8062292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8072702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8082292SN/A 8092292SN/A dispatchStatus[tid] = Squashing; 8102702Sktlim@umich.edu emptyRenameInsts(tid); 8112702Sktlim@umich.edu wroteToTimeBuffer = true; 8122292SN/A return; 8132292SN/A } 8142292SN/A 8152292SN/A if (checkStall(tid)) { 8162292SN/A block(tid); 8172292SN/A dispatchStatus[tid] = Blocked; 8182292SN/A return; 8192292SN/A } 8202292SN/A 8212292SN/A if (dispatchStatus[tid] == Blocked) { 8222292SN/A // Status from previous cycle was blocked, but there are no more stall 8232292SN/A // conditions. Switch over to unblocking. 8242292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8252292SN/A tid); 8262292SN/A 8272292SN/A dispatchStatus[tid] = Unblocking; 8282292SN/A 8292292SN/A unblock(tid); 8302292SN/A 8312292SN/A return; 8322292SN/A } 8332292SN/A 8342292SN/A if (dispatchStatus[tid] == Squashing) { 8352292SN/A // Switch status to running if rename isn't being told to block or 8362292SN/A // squash this cycle. 8372292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8382292SN/A tid); 8392292SN/A 8402292SN/A dispatchStatus[tid] = Running; 8412292SN/A 8422292SN/A return; 8432292SN/A } 8442292SN/A} 8452292SN/A 8462292SN/Atemplate <class Impl> 8472292SN/Avoid 8482292SN/ADefaultIEW<Impl>::sortInsts() 8492292SN/A{ 8502292SN/A int insts_from_rename = fromRename->size; 8512326SN/A#ifdef DEBUG 8526221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8536221Snate@binkert.org assert(insts[tid].empty()); 8542326SN/A#endif 8552292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8562292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8572292SN/A } 8582292SN/A} 8592292SN/A 8602292SN/Atemplate <class Impl> 8612292SN/Avoid 8626221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8632702Sktlim@umich.edu{ 8644632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8652935Sksewell@umich.edu 8662702Sktlim@umich.edu while (!insts[tid].empty()) { 8672935Sksewell@umich.edu 8682702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8692702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8702702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8712702Sktlim@umich.edu } 8722702Sktlim@umich.edu 8732702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8742702Sktlim@umich.edu 8752702Sktlim@umich.edu insts[tid].pop(); 8762702Sktlim@umich.edu } 8772702Sktlim@umich.edu} 8782702Sktlim@umich.edu 8792702Sktlim@umich.edutemplate <class Impl> 8802702Sktlim@umich.eduvoid 8812292SN/ADefaultIEW<Impl>::wakeCPU() 8822292SN/A{ 8832292SN/A cpu->wakeCPU(); 8842292SN/A} 8852292SN/A 8862292SN/Atemplate <class Impl> 8872292SN/Avoid 8882292SN/ADefaultIEW<Impl>::activityThisCycle() 8892292SN/A{ 8902292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8912292SN/A cpu->activityThisCycle(); 8922292SN/A} 8932292SN/A 8942292SN/Atemplate <class Impl> 8952292SN/Ainline void 8962292SN/ADefaultIEW<Impl>::activateStage() 8972292SN/A{ 8982292SN/A DPRINTF(Activity, "Activating stage.\n"); 8992733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 9002292SN/A} 9012292SN/A 9022292SN/Atemplate <class Impl> 9032292SN/Ainline void 9042292SN/ADefaultIEW<Impl>::deactivateStage() 9052292SN/A{ 9062292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9072733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9082292SN/A} 9092292SN/A 9102292SN/Atemplate<class Impl> 9112292SN/Avoid 9126221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9132292SN/A{ 9142292SN/A // If status is Running or idle, 9152292SN/A // call dispatchInsts() 9162292SN/A // If status is Unblocking, 9172292SN/A // buffer any instructions coming from rename 9182292SN/A // continue trying to empty skid buffer 9192292SN/A // check if stall conditions have passed 9202292SN/A 9212292SN/A if (dispatchStatus[tid] == Blocked) { 9222292SN/A ++iewBlockCycles; 9232292SN/A 9242292SN/A } else if (dispatchStatus[tid] == Squashing) { 9252292SN/A ++iewSquashCycles; 9262292SN/A } 9272292SN/A 9282292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9292292SN/A // will allow, as long as it is not currently blocked. 9302292SN/A if (dispatchStatus[tid] == Running || 9312292SN/A dispatchStatus[tid] == Idle) { 9322292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9332292SN/A "dispatch.\n", tid); 9342292SN/A 9352292SN/A dispatchInsts(tid); 9362292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9372292SN/A // Make sure that the skid buffer has something in it if the 9382292SN/A // status is unblocking. 9392292SN/A assert(!skidsEmpty()); 9402292SN/A 9412292SN/A // If the status was unblocking, then instructions from the skid 9422292SN/A // buffer were used. Remove those instructions and handle 9432292SN/A // the rest of unblocking. 9442292SN/A dispatchInsts(tid); 9452292SN/A 9462292SN/A ++iewUnblockCycles; 9472292SN/A 9485215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9492292SN/A // Add the current inputs to the skid buffer so they can be 9502292SN/A // reprocessed when this stage unblocks. 9512292SN/A skidInsert(tid); 9522292SN/A } 9532292SN/A 9542292SN/A unblock(tid); 9552292SN/A } 9562292SN/A} 9572292SN/A 9582292SN/Atemplate <class Impl> 9592292SN/Avoid 9606221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9612292SN/A{ 9622292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9632292SN/A // otherwise. 9642292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9652292SN/A dispatchStatus[tid] == Unblocking ? 9662292SN/A skidBuffer[tid] : insts[tid]; 9672292SN/A 9682292SN/A int insts_to_add = insts_to_dispatch.size(); 9692292SN/A 9702292SN/A DynInstPtr inst; 9712292SN/A bool add_to_iq = false; 9722292SN/A int dis_num_inst = 0; 9732292SN/A 9742292SN/A // Loop through the instructions, putting them in the instruction 9752292SN/A // queue. 9762292SN/A for ( ; dis_num_inst < insts_to_add && 9772820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9782292SN/A ++dis_num_inst) 9792292SN/A { 9802292SN/A inst = insts_to_dispatch.front(); 9812292SN/A 9822292SN/A if (dispatchStatus[tid] == Unblocking) { 9832292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9842292SN/A "buffer\n", tid); 9852292SN/A } 9862292SN/A 9872292SN/A // Make sure there's a valid instruction there. 9882292SN/A assert(inst); 9892292SN/A 9907720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 9912292SN/A "IQ.\n", 9927720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 9932292SN/A 9942292SN/A // Be sure to mark these instructions as ready so that the 9952292SN/A // commit stage can go ahead and execute them, and mark 9962292SN/A // them as issued so the IQ doesn't reprocess them. 9972292SN/A 9982292SN/A // Check for squashed instructions. 9992292SN/A if (inst->isSquashed()) { 10002292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10012292SN/A "not adding to IQ.\n", tid); 10022292SN/A 10032292SN/A ++iewDispSquashedInsts; 10042292SN/A 10052292SN/A insts_to_dispatch.pop(); 10062292SN/A 10072292SN/A //Tell Rename That An Instruction has been processed 10082292SN/A if (inst->isLoad() || inst->isStore()) { 10092292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10102292SN/A } 10112292SN/A toRename->iewInfo[tid].dispatched++; 10122292SN/A 10132292SN/A continue; 10142292SN/A } 10152292SN/A 10162292SN/A // Check for full conditions. 10172292SN/A if (instQueue.isFull(tid)) { 10182292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10192292SN/A 10202292SN/A // Call function to start blocking. 10212292SN/A block(tid); 10222292SN/A 10232292SN/A // Set unblock to false. Special case where we are using 10242292SN/A // skidbuffer (unblocking) instructions but then we still 10252292SN/A // get full in the IQ. 10262292SN/A toRename->iewUnblock[tid] = false; 10272292SN/A 10282292SN/A ++iewIQFullEvents; 10292292SN/A break; 10302292SN/A } else if (ldstQueue.isFull(tid)) { 10312292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10322292SN/A 10332292SN/A // Call function to start blocking. 10342292SN/A block(tid); 10352292SN/A 10362292SN/A // Set unblock to false. Special case where we are using 10372292SN/A // skidbuffer (unblocking) instructions but then we still 10382292SN/A // get full in the IQ. 10392292SN/A toRename->iewUnblock[tid] = false; 10402292SN/A 10412292SN/A ++iewLSQFullEvents; 10422292SN/A break; 10432292SN/A } 10442292SN/A 10452292SN/A // Otherwise issue the instruction just fine. 10462292SN/A if (inst->isLoad()) { 10472292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10482292SN/A "encountered, adding to LSQ.\n", tid); 10492292SN/A 10502292SN/A // Reserve a spot in the load store queue for this 10512292SN/A // memory access. 10522292SN/A ldstQueue.insertLoad(inst); 10532292SN/A 10542292SN/A ++iewDispLoadInsts; 10552292SN/A 10562292SN/A add_to_iq = true; 10572292SN/A 10582292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10592292SN/A } else if (inst->isStore()) { 10602292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10612292SN/A "encountered, adding to LSQ.\n", tid); 10622292SN/A 10632292SN/A ldstQueue.insertStore(inst); 10642292SN/A 10652292SN/A ++iewDispStoreInsts; 10662292SN/A 10672336SN/A if (inst->isStoreConditional()) { 10682336SN/A // Store conditionals need to be set as "canCommit()" 10692336SN/A // so that commit can process them when they reach the 10702336SN/A // head of commit. 10712348SN/A // @todo: This is somewhat specific to Alpha. 10722292SN/A inst->setCanCommit(); 10732292SN/A instQueue.insertNonSpec(inst); 10742292SN/A add_to_iq = false; 10752292SN/A 10762292SN/A ++iewDispNonSpecInsts; 10772292SN/A } else { 10782292SN/A add_to_iq = true; 10792292SN/A } 10802292SN/A 10812292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10822292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10832326SN/A // Same as non-speculative stores. 10842292SN/A inst->setCanCommit(); 10852292SN/A instQueue.insertBarrier(inst); 10862292SN/A add_to_iq = false; 10872292SN/A } else if (inst->isNop()) { 10882292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10892292SN/A "skipping.\n", tid); 10902292SN/A 10912292SN/A inst->setIssued(); 10922292SN/A inst->setExecuted(); 10932292SN/A inst->setCanCommit(); 10942292SN/A 10952326SN/A instQueue.recordProducer(inst); 10962292SN/A 10972727Sktlim@umich.edu iewExecutedNop[tid]++; 10982301SN/A 10992292SN/A add_to_iq = false; 11002292SN/A } else if (inst->isExecuted()) { 11012292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11022292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11032292SN/A "skipping.\n"); 11042292SN/A 11052292SN/A inst->setIssued(); 11062292SN/A inst->setCanCommit(); 11072292SN/A 11082326SN/A instQueue.recordProducer(inst); 11092292SN/A 11102292SN/A add_to_iq = false; 11112292SN/A } else { 11122292SN/A add_to_iq = true; 11132292SN/A } 11144033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11154033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11164033Sktlim@umich.edu "encountered, skipping.\n", tid); 11174033Sktlim@umich.edu 11184033Sktlim@umich.edu // Same as non-speculative stores. 11194033Sktlim@umich.edu inst->setCanCommit(); 11204033Sktlim@umich.edu 11214033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11224033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11234033Sktlim@umich.edu 11244033Sktlim@umich.edu ++iewDispNonSpecInsts; 11254033Sktlim@umich.edu 11264033Sktlim@umich.edu add_to_iq = false; 11274033Sktlim@umich.edu } 11282292SN/A 11292292SN/A // If the instruction queue is not full, then add the 11302292SN/A // instruction. 11312292SN/A if (add_to_iq) { 11322292SN/A instQueue.insert(inst); 11332292SN/A } 11342292SN/A 11352292SN/A insts_to_dispatch.pop(); 11362292SN/A 11372292SN/A toRename->iewInfo[tid].dispatched++; 11382292SN/A 11392292SN/A ++iewDispatchedInsts; 11402292SN/A } 11412292SN/A 11422292SN/A if (!insts_to_dispatch.empty()) { 11432935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11442292SN/A block(tid); 11452292SN/A toRename->iewUnblock[tid] = false; 11462292SN/A } 11472292SN/A 11482292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11492292SN/A dispatchStatus[tid] = Running; 11502292SN/A 11512292SN/A updatedQueues = true; 11522292SN/A } 11532292SN/A 11542292SN/A dis_num_inst = 0; 11552292SN/A} 11562292SN/A 11572292SN/Atemplate <class Impl> 11582292SN/Avoid 11592292SN/ADefaultIEW<Impl>::printAvailableInsts() 11602292SN/A{ 11612292SN/A int inst = 0; 11622292SN/A 11632980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11642292SN/A 11652292SN/A while (fromIssue->insts[inst]) { 11662292SN/A 11672980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11682292SN/A 11697720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11702292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11712292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11722292SN/A 11732292SN/A inst++; 11742292SN/A 11752292SN/A } 11762292SN/A 11772980Sgblack@eecs.umich.edu std::cout << "\n"; 11782292SN/A} 11792292SN/A 11802292SN/Atemplate <class Impl> 11812292SN/Avoid 11822292SN/ADefaultIEW<Impl>::executeInsts() 11832292SN/A{ 11842292SN/A wbNumInst = 0; 11852292SN/A wbCycle = 0; 11862292SN/A 11876221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 11886221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 11892292SN/A 11903867Sbinkertn@umich.edu while (threads != end) { 11916221Snate@binkert.org ThreadID tid = *threads++; 11922292SN/A fetchRedirect[tid] = false; 11932292SN/A } 11942292SN/A 11952698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 11967599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 11972698Sktlim@umich.edu// printAvailableInsts(); 11981062SN/A 11991062SN/A // Execute/writeback any instructions that are available. 12002333SN/A int insts_to_execute = fromIssue->size; 12012292SN/A int inst_num = 0; 12022333SN/A for (; inst_num < insts_to_execute; 12032326SN/A ++inst_num) { 12041062SN/A 12052292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12061062SN/A 12072333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12081062SN/A 12097720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12107720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 12111062SN/A 12121062SN/A // Check if the instruction is squashed; if so then skip it 12131062SN/A if (inst->isSquashed()) { 12142292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 12151062SN/A 12161062SN/A // Consider this instruction executed so that commit can go 12171062SN/A // ahead and retire the instruction. 12181062SN/A inst->setExecuted(); 12191062SN/A 12202292SN/A // Not sure if I should set this here or just let commit try to 12212292SN/A // commit any squashed instructions. I like the latter a bit more. 12222292SN/A inst->setCanCommit(); 12231062SN/A 12241062SN/A ++iewExecSquashedInsts; 12251062SN/A 12262820Sktlim@umich.edu decrWb(inst->seqNum); 12271062SN/A continue; 12281062SN/A } 12291062SN/A 12302292SN/A Fault fault = NoFault; 12311062SN/A 12321062SN/A // Execute instruction. 12331062SN/A // Note that if the instruction faults, it will be handled 12341062SN/A // at the commit stage. 12357850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12362292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12371062SN/A "reference.\n"); 12381062SN/A 12391062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12401062SN/A if (inst->isLoad()) { 12412292SN/A // Loads will mark themselves as executed, and their writeback 12422292SN/A // event adds the instruction to the queue to commit 12432292SN/A fault = ldstQueue.executeLoad(inst); 12447944SGiacomo.Gabrielli@arm.com 12457944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12467944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12477944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12487944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12497944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12507944SGiacomo.Gabrielli@arm.com "load.\n"); 12517944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12527944SGiacomo.Gabrielli@arm.com continue; 12537944SGiacomo.Gabrielli@arm.com } 12547944SGiacomo.Gabrielli@arm.com 12557850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12568073SAli.Saidi@ARM.com inst->fault = NoFault; 12577850SMatt.Horsnell@arm.com } 12581062SN/A } else if (inst->isStore()) { 12592367SN/A fault = ldstQueue.executeStore(inst); 12601062SN/A 12617944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12627944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12637944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12647944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12657944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12667944SGiacomo.Gabrielli@arm.com "store.\n"); 12677944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12687944SGiacomo.Gabrielli@arm.com continue; 12697944SGiacomo.Gabrielli@arm.com } 12707944SGiacomo.Gabrielli@arm.com 12712292SN/A // If the store had a fault then it may not have a mem req 12727782Sminkyu.jeong@arm.com if (fault != NoFault || inst->readPredicate() == false || 12737782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 12747782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 12757782Sminkyu.jeong@arm.com // to commit without the instruction completing. 12762367SN/A // Send this instruction to commit, also make sure iew stage 12772367SN/A // realizes there is activity. 12782367SN/A inst->setExecuted(); 12792367SN/A instToCommit(inst); 12802367SN/A activityThisCycle(); 12812292SN/A } 12822326SN/A 12832326SN/A // Store conditionals will mark themselves as 12842326SN/A // executed, and their writeback event will add the 12852326SN/A // instruction to the queue to commit. 12861062SN/A } else { 12872292SN/A panic("Unexpected memory type!\n"); 12881062SN/A } 12891062SN/A 12901062SN/A } else { 12917847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 12927847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 12937847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 12947847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 12957847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 12967847Sminkyu.jeong@arm.com inst->execute(); 12977848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 12987848SAli.Saidi@ARM.com inst->forwardOldRegs(); 12997847Sminkyu.jeong@arm.com } 13001062SN/A 13012292SN/A inst->setExecuted(); 13022292SN/A 13032292SN/A instToCommit(inst); 13041062SN/A } 13051062SN/A 13062301SN/A updateExeInstStats(inst); 13071681SN/A 13082326SN/A // Check if branch prediction was correct, if not then we need 13092326SN/A // to tell commit to squash in flight instructions. Only 13102326SN/A // handle this if there hasn't already been something that 13112107SN/A // redirects fetch in this group of instructions. 13121681SN/A 13132292SN/A // This probably needs to prioritize the redirects if a different 13142292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13152292SN/A // instruction first, so the branch resolution order will be correct. 13166221Snate@binkert.org ThreadID tid = inst->threadNumber; 13171062SN/A 13183732Sktlim@umich.edu if (!fetchRedirect[tid] || 13197852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13203732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13211062SN/A 13227856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13237856SMatt.Horsnell@arm.com // that have not been executed. 13247856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13257856SMatt.Horsnell@arm.com 13267856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13272292SN/A fetchRedirect[tid] = true; 13281062SN/A 13292292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13306036Sksewell@umich.edu DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 13317720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 13327720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13337720Sgblack@eecs.umich.edu inst->pcState(), inst->nextInstAddr()); 13341062SN/A // If incorrect, then signal the ROB that it must be squashed. 13352292SN/A squashDueToBranch(inst, tid); 13361062SN/A 13373795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13381062SN/A predictedTakenIncorrect++; 13392292SN/A } else { 13402292SN/A predictedNotTakenIncorrect++; 13411062SN/A } 13422292SN/A } else if (ldstQueue.violation(tid)) { 13434033Sktlim@umich.edu assert(inst->isMemRef()); 13442326SN/A // If there was an ordering violation, then get the 13452326SN/A // DynInst that caused the violation. Note that this 13462292SN/A // clears the violation signal. 13472292SN/A DynInstPtr violator; 13482292SN/A violator = ldstQueue.getMemDepViolator(tid); 13491062SN/A 13507720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13517720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13527720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 13537720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->physEffAddr); 13547720Sgblack@eecs.umich.edu 13553732Sktlim@umich.edu fetchRedirect[tid] = true; 13563732Sktlim@umich.edu 13571062SN/A // Tell the instruction queue that a violation has occured. 13581062SN/A instQueue.violation(inst, violator); 13591062SN/A 13601062SN/A // Squash. 13612292SN/A squashDueToMemOrder(inst,tid); 13621062SN/A 13631062SN/A ++memOrderViolationEvents; 13642292SN/A } else if (ldstQueue.loadBlocked(tid) && 13652292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13662292SN/A fetchRedirect[tid] = true; 13672292SN/A 13682292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13697720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 13707720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 13712292SN/A 13722292SN/A squashDueToMemBlocked(inst, tid); 13731062SN/A } 13744033Sktlim@umich.edu } else { 13754033Sktlim@umich.edu // Reset any state associated with redirects that will not 13764033Sktlim@umich.edu // be used. 13774033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 13784033Sktlim@umich.edu assert(inst->isMemRef()); 13794033Sktlim@umich.edu 13804033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13814033Sktlim@umich.edu 13824033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13837720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 13847720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 13857720Sgblack@eecs.umich.edu inst->physEffAddr); 13864033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 13874033Sktlim@umich.edu "already squashing\n"); 13884033Sktlim@umich.edu 13894033Sktlim@umich.edu ++memOrderViolationEvents; 13904033Sktlim@umich.edu } 13914033Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 13924033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 13934033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 13947720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 13957720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 13964033Sktlim@umich.edu DPRINTF(IEW, "Blocked load will not be handled because " 13974033Sktlim@umich.edu "already squashing\n"); 13984033Sktlim@umich.edu 13994033Sktlim@umich.edu ldstQueue.setLoadBlockedHandled(tid); 14004033Sktlim@umich.edu } 14014033Sktlim@umich.edu 14021062SN/A } 14031062SN/A } 14042292SN/A 14052348SN/A // Update and record activity if we processed any instructions. 14062292SN/A if (inst_num) { 14072292SN/A if (exeStatus == Idle) { 14082292SN/A exeStatus = Running; 14092292SN/A } 14102292SN/A 14112292SN/A updatedQueues = true; 14122292SN/A 14132292SN/A cpu->activityThisCycle(); 14142292SN/A } 14152292SN/A 14162292SN/A // Need to reset this in case a writeback event needs to write into the 14172292SN/A // iew queue. That way the writeback event will write into the correct 14182292SN/A // spot in the queue. 14192292SN/A wbNumInst = 0; 14207852SMatt.Horsnell@arm.com 14212107SN/A} 14222107SN/A 14232292SN/Atemplate <class Impl> 14242107SN/Avoid 14252292SN/ADefaultIEW<Impl>::writebackInsts() 14262107SN/A{ 14272326SN/A // Loop through the head of the time buffer and wake any 14282326SN/A // dependents. These instructions are about to write back. Also 14292326SN/A // mark scoreboard that this instruction is finally complete. 14302326SN/A // Either have IEW have direct access to scoreboard, or have this 14312326SN/A // as part of backwards communication. 14323958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14332292SN/A toCommit->insts[inst_num]; inst_num++) { 14342107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14356221Snate@binkert.org ThreadID tid = inst->threadNumber; 14362107SN/A 14377720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14387720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14392107SN/A 14402301SN/A iewInstsToCommit[tid]++; 14412301SN/A 14422292SN/A // Some instructions will be sent to commit without having 14432292SN/A // executed because they need commit to handle them. 14442292SN/A // E.g. Uncached loads have not actually executed when they 14452292SN/A // are first sent to commit. Instead commit must tell the LSQ 14462292SN/A // when it's ready to execute the uncached load. 14472367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14482301SN/A int dependents = instQueue.wakeDependents(inst); 14492107SN/A 14502292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14512292SN/A //mark as Ready 14522292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14532292SN/A inst->renamedDestRegIdx(i)); 14542292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14552107SN/A } 14562301SN/A 14572348SN/A if (dependents) { 14582348SN/A producerInst[tid]++; 14592348SN/A consumerInst[tid]+= dependents; 14602348SN/A } 14612326SN/A writebackCount[tid]++; 14622107SN/A } 14632820Sktlim@umich.edu 14642820Sktlim@umich.edu decrWb(inst->seqNum); 14652107SN/A } 14661060SN/A} 14671060SN/A 14681681SN/Atemplate<class Impl> 14691060SN/Avoid 14702292SN/ADefaultIEW<Impl>::tick() 14711060SN/A{ 14722292SN/A wbNumInst = 0; 14732292SN/A wbCycle = 0; 14741060SN/A 14752292SN/A wroteToTimeBuffer = false; 14762292SN/A updatedQueues = false; 14771060SN/A 14782292SN/A sortInsts(); 14791060SN/A 14802326SN/A // Free function units marked as being freed this cycle. 14812326SN/A fuPool->processFreeUnits(); 14821062SN/A 14836221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 14846221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 14851060SN/A 14862326SN/A // Check stall and squash signals, dispatch any instructions. 14873867Sbinkertn@umich.edu while (threads != end) { 14886221Snate@binkert.org ThreadID tid = *threads++; 14891060SN/A 14902292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14911060SN/A 14922292SN/A checkSignalsAndUpdate(tid); 14932292SN/A dispatch(tid); 14941060SN/A } 14951060SN/A 14962292SN/A if (exeStatus != Squashing) { 14972292SN/A executeInsts(); 14981060SN/A 14992292SN/A writebackInsts(); 15002292SN/A 15012292SN/A // Have the instruction queue try to schedule any ready instructions. 15022292SN/A // (In actuality, this scheduling is for instructions that will 15032292SN/A // be executed next cycle.) 15042292SN/A instQueue.scheduleReadyInsts(); 15052292SN/A 15062292SN/A // Also should advance its own time buffers if the stage ran. 15072292SN/A // Not the best place for it, but this works (hopefully). 15082292SN/A issueToExecQueue.advance(); 15092292SN/A } 15102292SN/A 15112292SN/A bool broadcast_free_entries = false; 15122292SN/A 15132292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15142292SN/A exeStatus = Idle; 15152292SN/A updateLSQNextCycle = false; 15162292SN/A 15172292SN/A broadcast_free_entries = true; 15182292SN/A } 15192292SN/A 15202292SN/A // Writeback any stores using any leftover bandwidth. 15211681SN/A ldstQueue.writebackStores(); 15221681SN/A 15231061SN/A // Check the committed load/store signals to see if there's a load 15241061SN/A // or store to commit. Also check if it's being told to execute a 15251061SN/A // nonspeculative instruction. 15261681SN/A // This is pretty inefficient... 15272292SN/A 15283867Sbinkertn@umich.edu threads = activeThreads->begin(); 15293867Sbinkertn@umich.edu while (threads != end) { 15306221Snate@binkert.org ThreadID tid = (*threads++); 15312292SN/A 15322292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15332292SN/A 15342348SN/A // Update structures based on instructions committed. 15352292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15362292SN/A !fromCommit->commitInfo[tid].squash && 15372292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15382292SN/A 15392292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15402292SN/A 15412292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15422292SN/A 15432292SN/A updateLSQNextCycle = true; 15442292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15452292SN/A } 15462292SN/A 15472292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15482292SN/A 15492292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15502292SN/A if (fromCommit->commitInfo[tid].uncached) { 15512292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15524033Sktlim@umich.edu fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15532292SN/A } else { 15542292SN/A instQueue.scheduleNonSpec( 15552292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15562292SN/A } 15572292SN/A } 15582292SN/A 15592292SN/A if (broadcast_free_entries) { 15602292SN/A toFetch->iewInfo[tid].iqCount = 15612292SN/A instQueue.getCount(tid); 15622292SN/A toFetch->iewInfo[tid].ldstqCount = 15632292SN/A ldstQueue.getCount(tid); 15642292SN/A 15652292SN/A toRename->iewInfo[tid].usedIQ = true; 15662292SN/A toRename->iewInfo[tid].freeIQEntries = 15672292SN/A instQueue.numFreeEntries(); 15682292SN/A toRename->iewInfo[tid].usedLSQ = true; 15692292SN/A toRename->iewInfo[tid].freeLSQEntries = 15702292SN/A ldstQueue.numFreeEntries(tid); 15712292SN/A 15722292SN/A wroteToTimeBuffer = true; 15732292SN/A } 15742292SN/A 15752292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15762292SN/A tid, toRename->iewInfo[tid].dispatched); 15771061SN/A } 15781061SN/A 15792292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15802292SN/A "LSQ has %i free entries.\n", 15812292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15822292SN/A ldstQueue.numFreeEntries()); 15832292SN/A 15842292SN/A updateStatus(); 15852292SN/A 15862292SN/A if (wroteToTimeBuffer) { 15872292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15882292SN/A cpu->activityThisCycle(); 15891061SN/A } 15901060SN/A} 15911060SN/A 15922301SN/Atemplate <class Impl> 15931060SN/Avoid 15942301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 15951060SN/A{ 15966221Snate@binkert.org ThreadID tid = inst->threadNumber; 15971060SN/A 15982301SN/A // 15992301SN/A // Pick off the software prefetches 16002301SN/A // 16012301SN/A#ifdef TARGET_ALPHA 16022301SN/A if (inst->isDataPrefetch()) 16036221Snate@binkert.org iewExecutedSwp[tid]++; 16042301SN/A else 16052727Sktlim@umich.edu iewIewExecutedcutedInsts++; 16062301SN/A#else 16072669Sktlim@umich.edu iewExecutedInsts++; 16082301SN/A#endif 16091060SN/A 16102301SN/A // 16112301SN/A // Control operations 16122301SN/A // 16132301SN/A if (inst->isControl()) 16146221Snate@binkert.org iewExecutedBranches[tid]++; 16151060SN/A 16162301SN/A // 16172301SN/A // Memory operations 16182301SN/A // 16192301SN/A if (inst->isMemRef()) { 16206221Snate@binkert.org iewExecutedRefs[tid]++; 16211060SN/A 16222301SN/A if (inst->isLoad()) { 16236221Snate@binkert.org iewExecLoadInsts[tid]++; 16241060SN/A } 16251060SN/A } 16261060SN/A} 16277598Sminkyu.jeong@arm.com 16287598Sminkyu.jeong@arm.comtemplate <class Impl> 16297598Sminkyu.jeong@arm.comvoid 16307598Sminkyu.jeong@arm.comDefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 16317598Sminkyu.jeong@arm.com{ 16327598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16337598Sminkyu.jeong@arm.com 16347598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16357852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16367598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16377598Sminkyu.jeong@arm.com 16387598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16397598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16407598Sminkyu.jeong@arm.com 16417598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16427598Sminkyu.jeong@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16437720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 16447598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 16457720Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->nextInstAddr(), 16467720Sgblack@eecs.umich.edu inst->nextInstAddr()); 16477598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 16487598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 16497598Sminkyu.jeong@arm.com 16507598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 16517598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 16527598Sminkyu.jeong@arm.com } else { 16537598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 16547598Sminkyu.jeong@arm.com } 16557598Sminkyu.jeong@arm.com } 16567598Sminkyu.jeong@arm.com } 16577598Sminkyu.jeong@arm.com} 1658