iew_impl.hh revision 8073 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43// @todo: Fix the instantaneous communication among all the stages within
44// iew.  There's a clear delay between issue and execute, yet backwards
45// communication happens simultaneously.
46
47#include <queue>
48
49#include "cpu/timebuf.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/fu_pool.hh"
52#include "cpu/o3/iew.hh"
53#include "params/DerivO3CPU.hh"
54
55using namespace std;
56
57template<class Impl>
58DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
59    : issueToExecQueue(params->backComSize, params->forwardComSize),
60      cpu(_cpu),
61      instQueue(_cpu, this, params),
62      ldstQueue(_cpu, this, params),
63      fuPool(params->fuPool),
64      commitToIEWDelay(params->commitToIEWDelay),
65      renameToIEWDelay(params->renameToIEWDelay),
66      issueToExecuteDelay(params->issueToExecuteDelay),
67      dispatchWidth(params->dispatchWidth),
68      issueWidth(params->issueWidth),
69      wbOutstanding(0),
70      wbWidth(params->wbWidth),
71      numThreads(params->numThreads),
72      switchedOut(false)
73{
74    _status = Active;
75    exeStatus = Running;
76    wbStatus = Idle;
77
78    // Setup wire to read instructions coming from issue.
79    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
80
81    // Instruction queue needs the queue between issue and execute.
82    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
83
84    for (ThreadID tid = 0; tid < numThreads; tid++) {
85        dispatchStatus[tid] = Running;
86        stalls[tid].commit = false;
87        fetchRedirect[tid] = false;
88    }
89
90    wbMax = wbWidth * params->wbDepth;
91
92    updateLSQNextCycle = false;
93
94    ableToIssue = true;
95
96    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
97}
98
99template <class Impl>
100std::string
101DefaultIEW<Impl>::name() const
102{
103    return cpu->name() + ".iew";
104}
105
106template <class Impl>
107void
108DefaultIEW<Impl>::regStats()
109{
110    using namespace Stats;
111
112    instQueue.regStats();
113    ldstQueue.regStats();
114
115    iewIdleCycles
116        .name(name() + ".iewIdleCycles")
117        .desc("Number of cycles IEW is idle");
118
119    iewSquashCycles
120        .name(name() + ".iewSquashCycles")
121        .desc("Number of cycles IEW is squashing");
122
123    iewBlockCycles
124        .name(name() + ".iewBlockCycles")
125        .desc("Number of cycles IEW is blocking");
126
127    iewUnblockCycles
128        .name(name() + ".iewUnblockCycles")
129        .desc("Number of cycles IEW is unblocking");
130
131    iewDispatchedInsts
132        .name(name() + ".iewDispatchedInsts")
133        .desc("Number of instructions dispatched to IQ");
134
135    iewDispSquashedInsts
136        .name(name() + ".iewDispSquashedInsts")
137        .desc("Number of squashed instructions skipped by dispatch");
138
139    iewDispLoadInsts
140        .name(name() + ".iewDispLoadInsts")
141        .desc("Number of dispatched load instructions");
142
143    iewDispStoreInsts
144        .name(name() + ".iewDispStoreInsts")
145        .desc("Number of dispatched store instructions");
146
147    iewDispNonSpecInsts
148        .name(name() + ".iewDispNonSpecInsts")
149        .desc("Number of dispatched non-speculative instructions");
150
151    iewIQFullEvents
152        .name(name() + ".iewIQFullEvents")
153        .desc("Number of times the IQ has become full, causing a stall");
154
155    iewLSQFullEvents
156        .name(name() + ".iewLSQFullEvents")
157        .desc("Number of times the LSQ has become full, causing a stall");
158
159    memOrderViolationEvents
160        .name(name() + ".memOrderViolationEvents")
161        .desc("Number of memory order violations");
162
163    predictedTakenIncorrect
164        .name(name() + ".predictedTakenIncorrect")
165        .desc("Number of branches that were predicted taken incorrectly");
166
167    predictedNotTakenIncorrect
168        .name(name() + ".predictedNotTakenIncorrect")
169        .desc("Number of branches that were predicted not taken incorrectly");
170
171    branchMispredicts
172        .name(name() + ".branchMispredicts")
173        .desc("Number of branch mispredicts detected at execute");
174
175    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
176
177    iewExecutedInsts
178        .name(name() + ".iewExecutedInsts")
179        .desc("Number of executed instructions");
180
181    iewExecLoadInsts
182        .init(cpu->numThreads)
183        .name(name() + ".iewExecLoadInsts")
184        .desc("Number of load instructions executed")
185        .flags(total);
186
187    iewExecSquashedInsts
188        .name(name() + ".iewExecSquashedInsts")
189        .desc("Number of squashed instructions skipped in execute");
190
191    iewExecutedSwp
192        .init(cpu->numThreads)
193        .name(name() + ".EXEC:swp")
194        .desc("number of swp insts executed")
195        .flags(total);
196
197    iewExecutedNop
198        .init(cpu->numThreads)
199        .name(name() + ".EXEC:nop")
200        .desc("number of nop insts executed")
201        .flags(total);
202
203    iewExecutedRefs
204        .init(cpu->numThreads)
205        .name(name() + ".EXEC:refs")
206        .desc("number of memory reference insts executed")
207        .flags(total);
208
209    iewExecutedBranches
210        .init(cpu->numThreads)
211        .name(name() + ".EXEC:branches")
212        .desc("Number of branches executed")
213        .flags(total);
214
215    iewExecStoreInsts
216        .name(name() + ".EXEC:stores")
217        .desc("Number of stores executed")
218        .flags(total);
219    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
220
221    iewExecRate
222        .name(name() + ".EXEC:rate")
223        .desc("Inst execution rate")
224        .flags(total);
225
226    iewExecRate = iewExecutedInsts / cpu->numCycles;
227
228    iewInstsToCommit
229        .init(cpu->numThreads)
230        .name(name() + ".WB:sent")
231        .desc("cumulative count of insts sent to commit")
232        .flags(total);
233
234    writebackCount
235        .init(cpu->numThreads)
236        .name(name() + ".WB:count")
237        .desc("cumulative count of insts written-back")
238        .flags(total);
239
240    producerInst
241        .init(cpu->numThreads)
242        .name(name() + ".WB:producers")
243        .desc("num instructions producing a value")
244        .flags(total);
245
246    consumerInst
247        .init(cpu->numThreads)
248        .name(name() + ".WB:consumers")
249        .desc("num instructions consuming a value")
250        .flags(total);
251
252    wbPenalized
253        .init(cpu->numThreads)
254        .name(name() + ".WB:penalized")
255        .desc("number of instrctions required to write to 'other' IQ")
256        .flags(total);
257
258    wbPenalizedRate
259        .name(name() + ".WB:penalized_rate")
260        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
261        .flags(total);
262
263    wbPenalizedRate = wbPenalized / writebackCount;
264
265    wbFanout
266        .name(name() + ".WB:fanout")
267        .desc("average fanout of values written-back")
268        .flags(total);
269
270    wbFanout = producerInst / consumerInst;
271
272    wbRate
273        .name(name() + ".WB:rate")
274        .desc("insts written-back per cycle")
275        .flags(total);
276    wbRate = writebackCount / cpu->numCycles;
277}
278
279template<class Impl>
280void
281DefaultIEW<Impl>::initStage()
282{
283    for (ThreadID tid = 0; tid < numThreads; tid++) {
284        toRename->iewInfo[tid].usedIQ = true;
285        toRename->iewInfo[tid].freeIQEntries =
286            instQueue.numFreeEntries(tid);
287
288        toRename->iewInfo[tid].usedLSQ = true;
289        toRename->iewInfo[tid].freeLSQEntries =
290            ldstQueue.numFreeEntries(tid);
291    }
292
293    cpu->activateStage(O3CPU::IEWIdx);
294}
295
296template<class Impl>
297void
298DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
299{
300    timeBuffer = tb_ptr;
301
302    // Setup wire to read information from time buffer, from commit.
303    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
304
305    // Setup wire to write information back to previous stages.
306    toRename = timeBuffer->getWire(0);
307
308    toFetch = timeBuffer->getWire(0);
309
310    // Instruction queue also needs main time buffer.
311    instQueue.setTimeBuffer(tb_ptr);
312}
313
314template<class Impl>
315void
316DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
317{
318    renameQueue = rq_ptr;
319
320    // Setup wire to read information from rename queue.
321    fromRename = renameQueue->getWire(-renameToIEWDelay);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328    iewQueue = iq_ptr;
329
330    // Setup wire to write instructions to commit.
331    toCommit = iewQueue->getWire(0);
332}
333
334template<class Impl>
335void
336DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
337{
338    activeThreads = at_ptr;
339
340    ldstQueue.setActiveThreads(at_ptr);
341    instQueue.setActiveThreads(at_ptr);
342}
343
344template<class Impl>
345void
346DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
347{
348    scoreboard = sb_ptr;
349}
350
351template <class Impl>
352bool
353DefaultIEW<Impl>::drain()
354{
355    // IEW is ready to drain at any time.
356    cpu->signalDrained();
357    return true;
358}
359
360template <class Impl>
361void
362DefaultIEW<Impl>::resume()
363{
364}
365
366template <class Impl>
367void
368DefaultIEW<Impl>::switchOut()
369{
370    // Clear any state.
371    switchedOut = true;
372    assert(insts[0].empty());
373    assert(skidBuffer[0].empty());
374
375    instQueue.switchOut();
376    ldstQueue.switchOut();
377    fuPool->switchOut();
378
379    for (ThreadID tid = 0; tid < numThreads; tid++) {
380        while (!insts[tid].empty())
381            insts[tid].pop();
382        while (!skidBuffer[tid].empty())
383            skidBuffer[tid].pop();
384    }
385}
386
387template <class Impl>
388void
389DefaultIEW<Impl>::takeOverFrom()
390{
391    // Reset all state.
392    _status = Active;
393    exeStatus = Running;
394    wbStatus = Idle;
395    switchedOut = false;
396
397    instQueue.takeOverFrom();
398    ldstQueue.takeOverFrom();
399    fuPool->takeOverFrom();
400
401    initStage();
402    cpu->activityThisCycle();
403
404    for (ThreadID tid = 0; tid < numThreads; tid++) {
405        dispatchStatus[tid] = Running;
406        stalls[tid].commit = false;
407        fetchRedirect[tid] = false;
408    }
409
410    updateLSQNextCycle = false;
411
412    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
413        issueToExecQueue.advance();
414    }
415}
416
417template<class Impl>
418void
419DefaultIEW<Impl>::squash(ThreadID tid)
420{
421    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
422
423    // Tell the IQ to start squashing.
424    instQueue.squash(tid);
425
426    // Tell the LDSTQ to start squashing.
427    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
428    updatedQueues = true;
429
430    // Clear the skid buffer in case it has any data in it.
431    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
432            tid, fromCommit->commitInfo[tid].doneSeqNum);
433
434    while (!skidBuffer[tid].empty()) {
435        if (skidBuffer[tid].front()->isLoad() ||
436            skidBuffer[tid].front()->isStore() ) {
437            toRename->iewInfo[tid].dispatchedToLSQ++;
438        }
439
440        toRename->iewInfo[tid].dispatched++;
441
442        skidBuffer[tid].pop();
443    }
444
445    emptyRenameInsts(tid);
446}
447
448template<class Impl>
449void
450DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
451{
452    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
453            "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
454
455    if (toCommit->squash[tid] == false ||
456            inst->seqNum < toCommit->squashedSeqNum[tid]) {
457        toCommit->squash[tid] = true;
458        toCommit->squashedSeqNum[tid] = inst->seqNum;
459        toCommit->mispredPC[tid] = inst->instAddr();
460        toCommit->branchMispredict[tid] = true;
461        toCommit->branchTaken[tid] = inst->pcState().branching();
462
463        TheISA::PCState pc = inst->pcState();
464        TheISA::advancePC(pc, inst->staticInst);
465
466        toCommit->pc[tid] = pc;
467        toCommit->mispredictInst[tid] = inst;
468        toCommit->includeSquashInst[tid] = false;
469
470        wroteToTimeBuffer = true;
471    }
472
473}
474
475template<class Impl>
476void
477DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
478{
479    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
480            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
481
482    if (toCommit->squash[tid] == false ||
483            inst->seqNum < toCommit->squashedSeqNum[tid]) {
484        toCommit->squash[tid] = true;
485        toCommit->squashedSeqNum[tid] = inst->seqNum;
486        TheISA::PCState pc = inst->pcState();
487        TheISA::advancePC(pc, inst->staticInst);
488        toCommit->pc[tid] = pc;
489        toCommit->branchMispredict[tid] = false;
490
491        toCommit->includeSquashInst[tid] = false;
492
493        wroteToTimeBuffer = true;
494    }
495}
496
497template<class Impl>
498void
499DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
500{
501    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
502            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
503    if (toCommit->squash[tid] == false ||
504            inst->seqNum < toCommit->squashedSeqNum[tid]) {
505        toCommit->squash[tid] = true;
506
507        toCommit->squashedSeqNum[tid] = inst->seqNum;
508        toCommit->pc[tid] = inst->pcState();
509        toCommit->branchMispredict[tid] = false;
510
511        // Must include the broadcasted SN in the squash.
512        toCommit->includeSquashInst[tid] = true;
513
514        ldstQueue.setLoadBlockedHandled(tid);
515
516        wroteToTimeBuffer = true;
517    }
518}
519
520template<class Impl>
521void
522DefaultIEW<Impl>::block(ThreadID tid)
523{
524    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
525
526    if (dispatchStatus[tid] != Blocked &&
527        dispatchStatus[tid] != Unblocking) {
528        toRename->iewBlock[tid] = true;
529        wroteToTimeBuffer = true;
530    }
531
532    // Add the current inputs to the skid buffer so they can be
533    // reprocessed when this stage unblocks.
534    skidInsert(tid);
535
536    dispatchStatus[tid] = Blocked;
537}
538
539template<class Impl>
540void
541DefaultIEW<Impl>::unblock(ThreadID tid)
542{
543    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
544            "buffer %u.\n",tid, tid);
545
546    // If the skid bufffer is empty, signal back to previous stages to unblock.
547    // Also switch status to running.
548    if (skidBuffer[tid].empty()) {
549        toRename->iewUnblock[tid] = true;
550        wroteToTimeBuffer = true;
551        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
552        dispatchStatus[tid] = Running;
553    }
554}
555
556template<class Impl>
557void
558DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
559{
560    instQueue.wakeDependents(inst);
561}
562
563template<class Impl>
564void
565DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
566{
567    instQueue.rescheduleMemInst(inst);
568}
569
570template<class Impl>
571void
572DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
573{
574    instQueue.replayMemInst(inst);
575}
576
577template<class Impl>
578void
579DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
580{
581    // This function should not be called after writebackInsts in a
582    // single cycle.  That will cause problems with an instruction
583    // being added to the queue to commit without being processed by
584    // writebackInsts prior to being sent to commit.
585
586    // First check the time slot that this instruction will write
587    // to.  If there are free write ports at the time, then go ahead
588    // and write the instruction to that time.  If there are not,
589    // keep looking back to see where's the first time there's a
590    // free slot.
591    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
592        ++wbNumInst;
593        if (wbNumInst == wbWidth) {
594            ++wbCycle;
595            wbNumInst = 0;
596        }
597
598        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
599    }
600
601    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
602            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
603    // Add finished instruction to queue to commit.
604    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
605    (*iewQueue)[wbCycle].size++;
606}
607
608template <class Impl>
609unsigned
610DefaultIEW<Impl>::validInstsFromRename()
611{
612    unsigned inst_count = 0;
613
614    for (int i=0; i<fromRename->size; i++) {
615        if (!fromRename->insts[i]->isSquashed())
616            inst_count++;
617    }
618
619    return inst_count;
620}
621
622template<class Impl>
623void
624DefaultIEW<Impl>::skidInsert(ThreadID tid)
625{
626    DynInstPtr inst = NULL;
627
628    while (!insts[tid].empty()) {
629        inst = insts[tid].front();
630
631        insts[tid].pop();
632
633        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
634                "dispatch skidBuffer %i\n",tid, inst->seqNum,
635                inst->pcState(),tid);
636
637        skidBuffer[tid].push(inst);
638    }
639
640    assert(skidBuffer[tid].size() <= skidBufferMax &&
641           "Skidbuffer Exceeded Max Size");
642}
643
644template<class Impl>
645int
646DefaultIEW<Impl>::skidCount()
647{
648    int max=0;
649
650    list<ThreadID>::iterator threads = activeThreads->begin();
651    list<ThreadID>::iterator end = activeThreads->end();
652
653    while (threads != end) {
654        ThreadID tid = *threads++;
655        unsigned thread_count = skidBuffer[tid].size();
656        if (max < thread_count)
657            max = thread_count;
658    }
659
660    return max;
661}
662
663template<class Impl>
664bool
665DefaultIEW<Impl>::skidsEmpty()
666{
667    list<ThreadID>::iterator threads = activeThreads->begin();
668    list<ThreadID>::iterator end = activeThreads->end();
669
670    while (threads != end) {
671        ThreadID tid = *threads++;
672
673        if (!skidBuffer[tid].empty())
674            return false;
675    }
676
677    return true;
678}
679
680template <class Impl>
681void
682DefaultIEW<Impl>::updateStatus()
683{
684    bool any_unblocking = false;
685
686    list<ThreadID>::iterator threads = activeThreads->begin();
687    list<ThreadID>::iterator end = activeThreads->end();
688
689    while (threads != end) {
690        ThreadID tid = *threads++;
691
692        if (dispatchStatus[tid] == Unblocking) {
693            any_unblocking = true;
694            break;
695        }
696    }
697
698    // If there are no ready instructions waiting to be scheduled by the IQ,
699    // and there's no stores waiting to write back, and dispatch is not
700    // unblocking, then there is no internal activity for the IEW stage.
701    instQueue.intInstQueueReads++;
702    if (_status == Active && !instQueue.hasReadyInsts() &&
703        !ldstQueue.willWB() && !any_unblocking) {
704        DPRINTF(IEW, "IEW switching to idle\n");
705
706        deactivateStage();
707
708        _status = Inactive;
709    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
710                                       ldstQueue.willWB() ||
711                                       any_unblocking)) {
712        // Otherwise there is internal activity.  Set to active.
713        DPRINTF(IEW, "IEW switching to active\n");
714
715        activateStage();
716
717        _status = Active;
718    }
719}
720
721template <class Impl>
722void
723DefaultIEW<Impl>::resetEntries()
724{
725    instQueue.resetEntries();
726    ldstQueue.resetEntries();
727}
728
729template <class Impl>
730void
731DefaultIEW<Impl>::readStallSignals(ThreadID tid)
732{
733    if (fromCommit->commitBlock[tid]) {
734        stalls[tid].commit = true;
735    }
736
737    if (fromCommit->commitUnblock[tid]) {
738        assert(stalls[tid].commit);
739        stalls[tid].commit = false;
740    }
741}
742
743template <class Impl>
744bool
745DefaultIEW<Impl>::checkStall(ThreadID tid)
746{
747    bool ret_val(false);
748
749    if (stalls[tid].commit) {
750        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
751        ret_val = true;
752    } else if (instQueue.isFull(tid)) {
753        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
754        ret_val = true;
755    } else if (ldstQueue.isFull(tid)) {
756        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
757
758        if (ldstQueue.numLoads(tid) > 0 ) {
759
760            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
761                    tid,ldstQueue.getLoadHeadSeqNum(tid));
762        }
763
764        if (ldstQueue.numStores(tid) > 0) {
765
766            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
767                    tid,ldstQueue.getStoreHeadSeqNum(tid));
768        }
769
770        ret_val = true;
771    } else if (ldstQueue.isStalled(tid)) {
772        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
773        ret_val = true;
774    }
775
776    return ret_val;
777}
778
779template <class Impl>
780void
781DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
782{
783    // Check if there's a squash signal, squash if there is
784    // Check stall signals, block if there is.
785    // If status was Blocked
786    //     if so then go to unblocking
787    // If status was Squashing
788    //     check if squashing is not high.  Switch to running this cycle.
789
790    readStallSignals(tid);
791
792    if (fromCommit->commitInfo[tid].squash) {
793        squash(tid);
794
795        if (dispatchStatus[tid] == Blocked ||
796            dispatchStatus[tid] == Unblocking) {
797            toRename->iewUnblock[tid] = true;
798            wroteToTimeBuffer = true;
799        }
800
801        dispatchStatus[tid] = Squashing;
802        fetchRedirect[tid] = false;
803        return;
804    }
805
806    if (fromCommit->commitInfo[tid].robSquashing) {
807        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
808
809        dispatchStatus[tid] = Squashing;
810        emptyRenameInsts(tid);
811        wroteToTimeBuffer = true;
812        return;
813    }
814
815    if (checkStall(tid)) {
816        block(tid);
817        dispatchStatus[tid] = Blocked;
818        return;
819    }
820
821    if (dispatchStatus[tid] == Blocked) {
822        // Status from previous cycle was blocked, but there are no more stall
823        // conditions.  Switch over to unblocking.
824        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
825                tid);
826
827        dispatchStatus[tid] = Unblocking;
828
829        unblock(tid);
830
831        return;
832    }
833
834    if (dispatchStatus[tid] == Squashing) {
835        // Switch status to running if rename isn't being told to block or
836        // squash this cycle.
837        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
838                tid);
839
840        dispatchStatus[tid] = Running;
841
842        return;
843    }
844}
845
846template <class Impl>
847void
848DefaultIEW<Impl>::sortInsts()
849{
850    int insts_from_rename = fromRename->size;
851#ifdef DEBUG
852    for (ThreadID tid = 0; tid < numThreads; tid++)
853        assert(insts[tid].empty());
854#endif
855    for (int i = 0; i < insts_from_rename; ++i) {
856        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
857    }
858}
859
860template <class Impl>
861void
862DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
863{
864    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
865
866    while (!insts[tid].empty()) {
867
868        if (insts[tid].front()->isLoad() ||
869            insts[tid].front()->isStore() ) {
870            toRename->iewInfo[tid].dispatchedToLSQ++;
871        }
872
873        toRename->iewInfo[tid].dispatched++;
874
875        insts[tid].pop();
876    }
877}
878
879template <class Impl>
880void
881DefaultIEW<Impl>::wakeCPU()
882{
883    cpu->wakeCPU();
884}
885
886template <class Impl>
887void
888DefaultIEW<Impl>::activityThisCycle()
889{
890    DPRINTF(Activity, "Activity this cycle.\n");
891    cpu->activityThisCycle();
892}
893
894template <class Impl>
895inline void
896DefaultIEW<Impl>::activateStage()
897{
898    DPRINTF(Activity, "Activating stage.\n");
899    cpu->activateStage(O3CPU::IEWIdx);
900}
901
902template <class Impl>
903inline void
904DefaultIEW<Impl>::deactivateStage()
905{
906    DPRINTF(Activity, "Deactivating stage.\n");
907    cpu->deactivateStage(O3CPU::IEWIdx);
908}
909
910template<class Impl>
911void
912DefaultIEW<Impl>::dispatch(ThreadID tid)
913{
914    // If status is Running or idle,
915    //     call dispatchInsts()
916    // If status is Unblocking,
917    //     buffer any instructions coming from rename
918    //     continue trying to empty skid buffer
919    //     check if stall conditions have passed
920
921    if (dispatchStatus[tid] == Blocked) {
922        ++iewBlockCycles;
923
924    } else if (dispatchStatus[tid] == Squashing) {
925        ++iewSquashCycles;
926    }
927
928    // Dispatch should try to dispatch as many instructions as its bandwidth
929    // will allow, as long as it is not currently blocked.
930    if (dispatchStatus[tid] == Running ||
931        dispatchStatus[tid] == Idle) {
932        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
933                "dispatch.\n", tid);
934
935        dispatchInsts(tid);
936    } else if (dispatchStatus[tid] == Unblocking) {
937        // Make sure that the skid buffer has something in it if the
938        // status is unblocking.
939        assert(!skidsEmpty());
940
941        // If the status was unblocking, then instructions from the skid
942        // buffer were used.  Remove those instructions and handle
943        // the rest of unblocking.
944        dispatchInsts(tid);
945
946        ++iewUnblockCycles;
947
948        if (validInstsFromRename()) {
949            // Add the current inputs to the skid buffer so they can be
950            // reprocessed when this stage unblocks.
951            skidInsert(tid);
952        }
953
954        unblock(tid);
955    }
956}
957
958template <class Impl>
959void
960DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
961{
962    // Obtain instructions from skid buffer if unblocking, or queue from rename
963    // otherwise.
964    std::queue<DynInstPtr> &insts_to_dispatch =
965        dispatchStatus[tid] == Unblocking ?
966        skidBuffer[tid] : insts[tid];
967
968    int insts_to_add = insts_to_dispatch.size();
969
970    DynInstPtr inst;
971    bool add_to_iq = false;
972    int dis_num_inst = 0;
973
974    // Loop through the instructions, putting them in the instruction
975    // queue.
976    for ( ; dis_num_inst < insts_to_add &&
977              dis_num_inst < dispatchWidth;
978          ++dis_num_inst)
979    {
980        inst = insts_to_dispatch.front();
981
982        if (dispatchStatus[tid] == Unblocking) {
983            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
984                    "buffer\n", tid);
985        }
986
987        // Make sure there's a valid instruction there.
988        assert(inst);
989
990        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
991                "IQ.\n",
992                tid, inst->pcState(), inst->seqNum, inst->threadNumber);
993
994        // Be sure to mark these instructions as ready so that the
995        // commit stage can go ahead and execute them, and mark
996        // them as issued so the IQ doesn't reprocess them.
997
998        // Check for squashed instructions.
999        if (inst->isSquashed()) {
1000            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1001                    "not adding to IQ.\n", tid);
1002
1003            ++iewDispSquashedInsts;
1004
1005            insts_to_dispatch.pop();
1006
1007            //Tell Rename That An Instruction has been processed
1008            if (inst->isLoad() || inst->isStore()) {
1009                toRename->iewInfo[tid].dispatchedToLSQ++;
1010            }
1011            toRename->iewInfo[tid].dispatched++;
1012
1013            continue;
1014        }
1015
1016        // Check for full conditions.
1017        if (instQueue.isFull(tid)) {
1018            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1019
1020            // Call function to start blocking.
1021            block(tid);
1022
1023            // Set unblock to false. Special case where we are using
1024            // skidbuffer (unblocking) instructions but then we still
1025            // get full in the IQ.
1026            toRename->iewUnblock[tid] = false;
1027
1028            ++iewIQFullEvents;
1029            break;
1030        } else if (ldstQueue.isFull(tid)) {
1031            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1032
1033            // Call function to start blocking.
1034            block(tid);
1035
1036            // Set unblock to false. Special case where we are using
1037            // skidbuffer (unblocking) instructions but then we still
1038            // get full in the IQ.
1039            toRename->iewUnblock[tid] = false;
1040
1041            ++iewLSQFullEvents;
1042            break;
1043        }
1044
1045        // Otherwise issue the instruction just fine.
1046        if (inst->isLoad()) {
1047            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1048                    "encountered, adding to LSQ.\n", tid);
1049
1050            // Reserve a spot in the load store queue for this
1051            // memory access.
1052            ldstQueue.insertLoad(inst);
1053
1054            ++iewDispLoadInsts;
1055
1056            add_to_iq = true;
1057
1058            toRename->iewInfo[tid].dispatchedToLSQ++;
1059        } else if (inst->isStore()) {
1060            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1061                    "encountered, adding to LSQ.\n", tid);
1062
1063            ldstQueue.insertStore(inst);
1064
1065            ++iewDispStoreInsts;
1066
1067            if (inst->isStoreConditional()) {
1068                // Store conditionals need to be set as "canCommit()"
1069                // so that commit can process them when they reach the
1070                // head of commit.
1071                // @todo: This is somewhat specific to Alpha.
1072                inst->setCanCommit();
1073                instQueue.insertNonSpec(inst);
1074                add_to_iq = false;
1075
1076                ++iewDispNonSpecInsts;
1077            } else {
1078                add_to_iq = true;
1079            }
1080
1081            toRename->iewInfo[tid].dispatchedToLSQ++;
1082        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1083            // Same as non-speculative stores.
1084            inst->setCanCommit();
1085            instQueue.insertBarrier(inst);
1086            add_to_iq = false;
1087        } else if (inst->isNop()) {
1088            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1089                    "skipping.\n", tid);
1090
1091            inst->setIssued();
1092            inst->setExecuted();
1093            inst->setCanCommit();
1094
1095            instQueue.recordProducer(inst);
1096
1097            iewExecutedNop[tid]++;
1098
1099            add_to_iq = false;
1100        } else if (inst->isExecuted()) {
1101            assert(0 && "Instruction shouldn't be executed.\n");
1102            DPRINTF(IEW, "Issue: Executed branch encountered, "
1103                    "skipping.\n");
1104
1105            inst->setIssued();
1106            inst->setCanCommit();
1107
1108            instQueue.recordProducer(inst);
1109
1110            add_to_iq = false;
1111        } else {
1112            add_to_iq = true;
1113        }
1114        if (inst->isNonSpeculative()) {
1115            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1116                    "encountered, skipping.\n", tid);
1117
1118            // Same as non-speculative stores.
1119            inst->setCanCommit();
1120
1121            // Specifically insert it as nonspeculative.
1122            instQueue.insertNonSpec(inst);
1123
1124            ++iewDispNonSpecInsts;
1125
1126            add_to_iq = false;
1127        }
1128
1129        // If the instruction queue is not full, then add the
1130        // instruction.
1131        if (add_to_iq) {
1132            instQueue.insert(inst);
1133        }
1134
1135        insts_to_dispatch.pop();
1136
1137        toRename->iewInfo[tid].dispatched++;
1138
1139        ++iewDispatchedInsts;
1140    }
1141
1142    if (!insts_to_dispatch.empty()) {
1143        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1144        block(tid);
1145        toRename->iewUnblock[tid] = false;
1146    }
1147
1148    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1149        dispatchStatus[tid] = Running;
1150
1151        updatedQueues = true;
1152    }
1153
1154    dis_num_inst = 0;
1155}
1156
1157template <class Impl>
1158void
1159DefaultIEW<Impl>::printAvailableInsts()
1160{
1161    int inst = 0;
1162
1163    std::cout << "Available Instructions: ";
1164
1165    while (fromIssue->insts[inst]) {
1166
1167        if (inst%3==0) std::cout << "\n\t";
1168
1169        std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1170             << " TN: " << fromIssue->insts[inst]->threadNumber
1171             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1172
1173        inst++;
1174
1175    }
1176
1177    std::cout << "\n";
1178}
1179
1180template <class Impl>
1181void
1182DefaultIEW<Impl>::executeInsts()
1183{
1184    wbNumInst = 0;
1185    wbCycle = 0;
1186
1187    list<ThreadID>::iterator threads = activeThreads->begin();
1188    list<ThreadID>::iterator end = activeThreads->end();
1189
1190    while (threads != end) {
1191        ThreadID tid = *threads++;
1192        fetchRedirect[tid] = false;
1193    }
1194
1195    // Uncomment this if you want to see all available instructions.
1196    // @todo This doesn't actually work anymore, we should fix it.
1197//    printAvailableInsts();
1198
1199    // Execute/writeback any instructions that are available.
1200    int insts_to_execute = fromIssue->size;
1201    int inst_num = 0;
1202    for (; inst_num < insts_to_execute;
1203          ++inst_num) {
1204
1205        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1206
1207        DynInstPtr inst = instQueue.getInstToExecute();
1208
1209        DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1210                inst->pcState(), inst->threadNumber,inst->seqNum);
1211
1212        // Check if the instruction is squashed; if so then skip it
1213        if (inst->isSquashed()) {
1214            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1215
1216            // Consider this instruction executed so that commit can go
1217            // ahead and retire the instruction.
1218            inst->setExecuted();
1219
1220            // Not sure if I should set this here or just let commit try to
1221            // commit any squashed instructions.  I like the latter a bit more.
1222            inst->setCanCommit();
1223
1224            ++iewExecSquashedInsts;
1225
1226            decrWb(inst->seqNum);
1227            continue;
1228        }
1229
1230        Fault fault = NoFault;
1231
1232        // Execute instruction.
1233        // Note that if the instruction faults, it will be handled
1234        // at the commit stage.
1235        if (inst->isMemRef()) {
1236            DPRINTF(IEW, "Execute: Calculating address for memory "
1237                    "reference.\n");
1238
1239            // Tell the LDSTQ to execute this instruction (if it is a load).
1240            if (inst->isLoad()) {
1241                // Loads will mark themselves as executed, and their writeback
1242                // event adds the instruction to the queue to commit
1243                fault = ldstQueue.executeLoad(inst);
1244
1245                if (inst->isTranslationDelayed() &&
1246                    fault == NoFault) {
1247                    // A hw page table walk is currently going on; the
1248                    // instruction must be deferred.
1249                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1250                            "load.\n");
1251                    instQueue.deferMemInst(inst);
1252                    continue;
1253                }
1254
1255                if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1256                    inst->fault = NoFault;
1257                }
1258            } else if (inst->isStore()) {
1259                fault = ldstQueue.executeStore(inst);
1260
1261                if (inst->isTranslationDelayed() &&
1262                    fault == NoFault) {
1263                    // A hw page table walk is currently going on; the
1264                    // instruction must be deferred.
1265                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1266                            "store.\n");
1267                    instQueue.deferMemInst(inst);
1268                    continue;
1269                }
1270
1271                // If the store had a fault then it may not have a mem req
1272                if (fault != NoFault || inst->readPredicate() == false ||
1273                        !inst->isStoreConditional()) {
1274                    // If the instruction faulted, then we need to send it along
1275                    // to commit without the instruction completing.
1276                    // Send this instruction to commit, also make sure iew stage
1277                    // realizes there is activity.
1278                    inst->setExecuted();
1279                    instToCommit(inst);
1280                    activityThisCycle();
1281                }
1282
1283                // Store conditionals will mark themselves as
1284                // executed, and their writeback event will add the
1285                // instruction to the queue to commit.
1286            } else {
1287                panic("Unexpected memory type!\n");
1288            }
1289
1290        } else {
1291            // If the instruction has already faulted, then skip executing it.
1292            // Such case can happen when it faulted during ITLB translation.
1293            // If we execute the instruction (even if it's a nop) the fault
1294            // will be replaced and we will lose it.
1295            if (inst->getFault() == NoFault) {
1296                inst->execute();
1297                if (inst->readPredicate() == false)
1298                    inst->forwardOldRegs();
1299            }
1300
1301            inst->setExecuted();
1302
1303            instToCommit(inst);
1304        }
1305
1306        updateExeInstStats(inst);
1307
1308        // Check if branch prediction was correct, if not then we need
1309        // to tell commit to squash in flight instructions.  Only
1310        // handle this if there hasn't already been something that
1311        // redirects fetch in this group of instructions.
1312
1313        // This probably needs to prioritize the redirects if a different
1314        // scheduler is used.  Currently the scheduler schedules the oldest
1315        // instruction first, so the branch resolution order will be correct.
1316        ThreadID tid = inst->threadNumber;
1317
1318        if (!fetchRedirect[tid] ||
1319            !toCommit->squash[tid] ||
1320            toCommit->squashedSeqNum[tid] > inst->seqNum) {
1321
1322            // Prevent testing for misprediction on load instructions,
1323            // that have not been executed.
1324            bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1325
1326            if (inst->mispredicted() && !loadNotExecuted) {
1327                fetchRedirect[tid] = true;
1328
1329                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1330                DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1331                        inst->predInstAddr(), inst->predNextInstAddr());
1332                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1333                        inst->pcState(), inst->nextInstAddr());
1334                // If incorrect, then signal the ROB that it must be squashed.
1335                squashDueToBranch(inst, tid);
1336
1337                if (inst->readPredTaken()) {
1338                    predictedTakenIncorrect++;
1339                } else {
1340                    predictedNotTakenIncorrect++;
1341                }
1342            } else if (ldstQueue.violation(tid)) {
1343                assert(inst->isMemRef());
1344                // If there was an ordering violation, then get the
1345                // DynInst that caused the violation.  Note that this
1346                // clears the violation signal.
1347                DynInstPtr violator;
1348                violator = ldstQueue.getMemDepViolator(tid);
1349
1350                DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1351                        "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1352                        violator->pcState(), violator->seqNum,
1353                        inst->pcState(), inst->seqNum, inst->physEffAddr);
1354
1355                fetchRedirect[tid] = true;
1356
1357                // Tell the instruction queue that a violation has occured.
1358                instQueue.violation(inst, violator);
1359
1360                // Squash.
1361                squashDueToMemOrder(inst,tid);
1362
1363                ++memOrderViolationEvents;
1364            } else if (ldstQueue.loadBlocked(tid) &&
1365                       !ldstQueue.isLoadBlockedHandled(tid)) {
1366                fetchRedirect[tid] = true;
1367
1368                DPRINTF(IEW, "Load operation couldn't execute because the "
1369                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1370                        inst->pcState(), inst->seqNum);
1371
1372                squashDueToMemBlocked(inst, tid);
1373            }
1374        } else {
1375            // Reset any state associated with redirects that will not
1376            // be used.
1377            if (ldstQueue.violation(tid)) {
1378                assert(inst->isMemRef());
1379
1380                DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1381
1382                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1383                        "%s, inst PC: %s.  Addr is: %#x.\n",
1384                        violator->pcState(), inst->pcState(),
1385                        inst->physEffAddr);
1386                DPRINTF(IEW, "Violation will not be handled because "
1387                        "already squashing\n");
1388
1389                ++memOrderViolationEvents;
1390            }
1391            if (ldstQueue.loadBlocked(tid) &&
1392                !ldstQueue.isLoadBlockedHandled(tid)) {
1393                DPRINTF(IEW, "Load operation couldn't execute because the "
1394                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1395                        inst->pcState(), inst->seqNum);
1396                DPRINTF(IEW, "Blocked load will not be handled because "
1397                        "already squashing\n");
1398
1399                ldstQueue.setLoadBlockedHandled(tid);
1400            }
1401
1402        }
1403    }
1404
1405    // Update and record activity if we processed any instructions.
1406    if (inst_num) {
1407        if (exeStatus == Idle) {
1408            exeStatus = Running;
1409        }
1410
1411        updatedQueues = true;
1412
1413        cpu->activityThisCycle();
1414    }
1415
1416    // Need to reset this in case a writeback event needs to write into the
1417    // iew queue.  That way the writeback event will write into the correct
1418    // spot in the queue.
1419    wbNumInst = 0;
1420
1421}
1422
1423template <class Impl>
1424void
1425DefaultIEW<Impl>::writebackInsts()
1426{
1427    // Loop through the head of the time buffer and wake any
1428    // dependents.  These instructions are about to write back.  Also
1429    // mark scoreboard that this instruction is finally complete.
1430    // Either have IEW have direct access to scoreboard, or have this
1431    // as part of backwards communication.
1432    for (int inst_num = 0; inst_num < wbWidth &&
1433             toCommit->insts[inst_num]; inst_num++) {
1434        DynInstPtr inst = toCommit->insts[inst_num];
1435        ThreadID tid = inst->threadNumber;
1436
1437        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1438                inst->seqNum, inst->pcState());
1439
1440        iewInstsToCommit[tid]++;
1441
1442        // Some instructions will be sent to commit without having
1443        // executed because they need commit to handle them.
1444        // E.g. Uncached loads have not actually executed when they
1445        // are first sent to commit.  Instead commit must tell the LSQ
1446        // when it's ready to execute the uncached load.
1447        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1448            int dependents = instQueue.wakeDependents(inst);
1449
1450            for (int i = 0; i < inst->numDestRegs(); i++) {
1451                //mark as Ready
1452                DPRINTF(IEW,"Setting Destination Register %i\n",
1453                        inst->renamedDestRegIdx(i));
1454                scoreboard->setReg(inst->renamedDestRegIdx(i));
1455            }
1456
1457            if (dependents) {
1458                producerInst[tid]++;
1459                consumerInst[tid]+= dependents;
1460            }
1461            writebackCount[tid]++;
1462        }
1463
1464        decrWb(inst->seqNum);
1465    }
1466}
1467
1468template<class Impl>
1469void
1470DefaultIEW<Impl>::tick()
1471{
1472    wbNumInst = 0;
1473    wbCycle = 0;
1474
1475    wroteToTimeBuffer = false;
1476    updatedQueues = false;
1477
1478    sortInsts();
1479
1480    // Free function units marked as being freed this cycle.
1481    fuPool->processFreeUnits();
1482
1483    list<ThreadID>::iterator threads = activeThreads->begin();
1484    list<ThreadID>::iterator end = activeThreads->end();
1485
1486    // Check stall and squash signals, dispatch any instructions.
1487    while (threads != end) {
1488        ThreadID tid = *threads++;
1489
1490        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1491
1492        checkSignalsAndUpdate(tid);
1493        dispatch(tid);
1494    }
1495
1496    if (exeStatus != Squashing) {
1497        executeInsts();
1498
1499        writebackInsts();
1500
1501        // Have the instruction queue try to schedule any ready instructions.
1502        // (In actuality, this scheduling is for instructions that will
1503        // be executed next cycle.)
1504        instQueue.scheduleReadyInsts();
1505
1506        // Also should advance its own time buffers if the stage ran.
1507        // Not the best place for it, but this works (hopefully).
1508        issueToExecQueue.advance();
1509    }
1510
1511    bool broadcast_free_entries = false;
1512
1513    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1514        exeStatus = Idle;
1515        updateLSQNextCycle = false;
1516
1517        broadcast_free_entries = true;
1518    }
1519
1520    // Writeback any stores using any leftover bandwidth.
1521    ldstQueue.writebackStores();
1522
1523    // Check the committed load/store signals to see if there's a load
1524    // or store to commit.  Also check if it's being told to execute a
1525    // nonspeculative instruction.
1526    // This is pretty inefficient...
1527
1528    threads = activeThreads->begin();
1529    while (threads != end) {
1530        ThreadID tid = (*threads++);
1531
1532        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1533
1534        // Update structures based on instructions committed.
1535        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1536            !fromCommit->commitInfo[tid].squash &&
1537            !fromCommit->commitInfo[tid].robSquashing) {
1538
1539            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1540
1541            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1542
1543            updateLSQNextCycle = true;
1544            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1545        }
1546
1547        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1548
1549            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1550            if (fromCommit->commitInfo[tid].uncached) {
1551                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1552                fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1553            } else {
1554                instQueue.scheduleNonSpec(
1555                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1556            }
1557        }
1558
1559        if (broadcast_free_entries) {
1560            toFetch->iewInfo[tid].iqCount =
1561                instQueue.getCount(tid);
1562            toFetch->iewInfo[tid].ldstqCount =
1563                ldstQueue.getCount(tid);
1564
1565            toRename->iewInfo[tid].usedIQ = true;
1566            toRename->iewInfo[tid].freeIQEntries =
1567                instQueue.numFreeEntries();
1568            toRename->iewInfo[tid].usedLSQ = true;
1569            toRename->iewInfo[tid].freeLSQEntries =
1570                ldstQueue.numFreeEntries(tid);
1571
1572            wroteToTimeBuffer = true;
1573        }
1574
1575        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1576                tid, toRename->iewInfo[tid].dispatched);
1577    }
1578
1579    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1580            "LSQ has %i free entries.\n",
1581            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1582            ldstQueue.numFreeEntries());
1583
1584    updateStatus();
1585
1586    if (wroteToTimeBuffer) {
1587        DPRINTF(Activity, "Activity this cycle.\n");
1588        cpu->activityThisCycle();
1589    }
1590}
1591
1592template <class Impl>
1593void
1594DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1595{
1596    ThreadID tid = inst->threadNumber;
1597
1598    //
1599    //  Pick off the software prefetches
1600    //
1601#ifdef TARGET_ALPHA
1602    if (inst->isDataPrefetch())
1603        iewExecutedSwp[tid]++;
1604    else
1605        iewIewExecutedcutedInsts++;
1606#else
1607    iewExecutedInsts++;
1608#endif
1609
1610    //
1611    //  Control operations
1612    //
1613    if (inst->isControl())
1614        iewExecutedBranches[tid]++;
1615
1616    //
1617    //  Memory operations
1618    //
1619    if (inst->isMemRef()) {
1620        iewExecutedRefs[tid]++;
1621
1622        if (inst->isLoad()) {
1623            iewExecLoadInsts[tid]++;
1624        }
1625    }
1626}
1627
1628template <class Impl>
1629void
1630DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1631{
1632    ThreadID tid = inst->threadNumber;
1633
1634    if (!fetchRedirect[tid] ||
1635        !toCommit->squash[tid] ||
1636        toCommit->squashedSeqNum[tid] > inst->seqNum) {
1637
1638        if (inst->mispredicted()) {
1639            fetchRedirect[tid] = true;
1640
1641            DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1642            DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1643                    inst->predInstAddr(), inst->predNextInstAddr());
1644            DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1645                    " NPC: %#x.\n", inst->nextInstAddr(),
1646                    inst->nextInstAddr());
1647            // If incorrect, then signal the ROB that it must be squashed.
1648            squashDueToBranch(inst, tid);
1649
1650            if (inst->readPredTaken()) {
1651                predictedTakenIncorrect++;
1652            } else {
1653                predictedNotTakenIncorrect++;
1654            }
1655        }
1656    }
1657}
1658