iew_impl.hh revision 6658
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311060SN/A// @todo: Fix the instantaneous communication among all the stages within 321060SN/A// iew. There's a clear delay between issue and execute, yet backwards 331689SN/A// communication happens simultaneously. 341060SN/A 351060SN/A#include <queue> 361060SN/A 371060SN/A#include "base/timebuf.hh" 386658Snate@binkert.org#include "config/the_isa.hh" 392292SN/A#include "cpu/o3/fu_pool.hh" 401717SN/A#include "cpu/o3/iew.hh" 415529Snate@binkert.org#include "params/DerivO3CPU.hh" 421060SN/A 436221Snate@binkert.orgusing namespace std; 446221Snate@binkert.org 451681SN/Atemplate<class Impl> 465529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 472873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 484329Sktlim@umich.edu cpu(_cpu), 494329Sktlim@umich.edu instQueue(_cpu, this, params), 504329Sktlim@umich.edu ldstQueue(_cpu, this, params), 512292SN/A fuPool(params->fuPool), 522292SN/A commitToIEWDelay(params->commitToIEWDelay), 532292SN/A renameToIEWDelay(params->renameToIEWDelay), 542292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 552820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 562292SN/A issueWidth(params->issueWidth), 572820Sktlim@umich.edu wbOutstanding(0), 582820Sktlim@umich.edu wbWidth(params->wbWidth), 595529Snate@binkert.org numThreads(params->numThreads), 602307SN/A switchedOut(false) 611060SN/A{ 622292SN/A _status = Active; 632292SN/A exeStatus = Running; 642292SN/A wbStatus = Idle; 651060SN/A 661060SN/A // Setup wire to read instructions coming from issue. 671060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 681060SN/A 691060SN/A // Instruction queue needs the queue between issue and execute. 701060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 711681SN/A 726221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 736221Snate@binkert.org dispatchStatus[tid] = Running; 746221Snate@binkert.org stalls[tid].commit = false; 756221Snate@binkert.org fetchRedirect[tid] = false; 762292SN/A } 772292SN/A 782820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 792820Sktlim@umich.edu 802292SN/A updateLSQNextCycle = false; 812292SN/A 822820Sktlim@umich.edu ableToIssue = true; 832820Sktlim@umich.edu 842292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 852292SN/A} 862292SN/A 872292SN/Atemplate <class Impl> 882292SN/Astd::string 892292SN/ADefaultIEW<Impl>::name() const 902292SN/A{ 912292SN/A return cpu->name() + ".iew"; 921060SN/A} 931060SN/A 941681SN/Atemplate <class Impl> 951062SN/Avoid 962292SN/ADefaultIEW<Impl>::regStats() 971062SN/A{ 982301SN/A using namespace Stats; 992301SN/A 1001062SN/A instQueue.regStats(); 1012727Sktlim@umich.edu ldstQueue.regStats(); 1021062SN/A 1031062SN/A iewIdleCycles 1041062SN/A .name(name() + ".iewIdleCycles") 1051062SN/A .desc("Number of cycles IEW is idle"); 1061062SN/A 1071062SN/A iewSquashCycles 1081062SN/A .name(name() + ".iewSquashCycles") 1091062SN/A .desc("Number of cycles IEW is squashing"); 1101062SN/A 1111062SN/A iewBlockCycles 1121062SN/A .name(name() + ".iewBlockCycles") 1131062SN/A .desc("Number of cycles IEW is blocking"); 1141062SN/A 1151062SN/A iewUnblockCycles 1161062SN/A .name(name() + ".iewUnblockCycles") 1171062SN/A .desc("Number of cycles IEW is unblocking"); 1181062SN/A 1191062SN/A iewDispatchedInsts 1201062SN/A .name(name() + ".iewDispatchedInsts") 1211062SN/A .desc("Number of instructions dispatched to IQ"); 1221062SN/A 1231062SN/A iewDispSquashedInsts 1241062SN/A .name(name() + ".iewDispSquashedInsts") 1251062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1261062SN/A 1271062SN/A iewDispLoadInsts 1281062SN/A .name(name() + ".iewDispLoadInsts") 1291062SN/A .desc("Number of dispatched load instructions"); 1301062SN/A 1311062SN/A iewDispStoreInsts 1321062SN/A .name(name() + ".iewDispStoreInsts") 1331062SN/A .desc("Number of dispatched store instructions"); 1341062SN/A 1351062SN/A iewDispNonSpecInsts 1361062SN/A .name(name() + ".iewDispNonSpecInsts") 1371062SN/A .desc("Number of dispatched non-speculative instructions"); 1381062SN/A 1391062SN/A iewIQFullEvents 1401062SN/A .name(name() + ".iewIQFullEvents") 1411062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1421062SN/A 1432292SN/A iewLSQFullEvents 1442292SN/A .name(name() + ".iewLSQFullEvents") 1452292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1462292SN/A 1471062SN/A memOrderViolationEvents 1481062SN/A .name(name() + ".memOrderViolationEvents") 1491062SN/A .desc("Number of memory order violations"); 1501062SN/A 1511062SN/A predictedTakenIncorrect 1521062SN/A .name(name() + ".predictedTakenIncorrect") 1531062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1542292SN/A 1552292SN/A predictedNotTakenIncorrect 1562292SN/A .name(name() + ".predictedNotTakenIncorrect") 1572292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1582292SN/A 1592292SN/A branchMispredicts 1602292SN/A .name(name() + ".branchMispredicts") 1612292SN/A .desc("Number of branch mispredicts detected at execute"); 1622292SN/A 1632292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1642301SN/A 1652727Sktlim@umich.edu iewExecutedInsts 1662353SN/A .name(name() + ".iewExecutedInsts") 1672727Sktlim@umich.edu .desc("Number of executed instructions"); 1682727Sktlim@umich.edu 1692727Sktlim@umich.edu iewExecLoadInsts 1706221Snate@binkert.org .init(cpu->numThreads) 1712353SN/A .name(name() + ".iewExecLoadInsts") 1722727Sktlim@umich.edu .desc("Number of load instructions executed") 1732727Sktlim@umich.edu .flags(total); 1742727Sktlim@umich.edu 1752727Sktlim@umich.edu iewExecSquashedInsts 1762353SN/A .name(name() + ".iewExecSquashedInsts") 1772727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1782727Sktlim@umich.edu 1792727Sktlim@umich.edu iewExecutedSwp 1806221Snate@binkert.org .init(cpu->numThreads) 1812301SN/A .name(name() + ".EXEC:swp") 1822301SN/A .desc("number of swp insts executed") 1832727Sktlim@umich.edu .flags(total); 1842301SN/A 1852727Sktlim@umich.edu iewExecutedNop 1866221Snate@binkert.org .init(cpu->numThreads) 1872301SN/A .name(name() + ".EXEC:nop") 1882301SN/A .desc("number of nop insts executed") 1892727Sktlim@umich.edu .flags(total); 1902301SN/A 1912727Sktlim@umich.edu iewExecutedRefs 1926221Snate@binkert.org .init(cpu->numThreads) 1932301SN/A .name(name() + ".EXEC:refs") 1942301SN/A .desc("number of memory reference insts executed") 1952727Sktlim@umich.edu .flags(total); 1962301SN/A 1972727Sktlim@umich.edu iewExecutedBranches 1986221Snate@binkert.org .init(cpu->numThreads) 1992301SN/A .name(name() + ".EXEC:branches") 2002301SN/A .desc("Number of branches executed") 2012727Sktlim@umich.edu .flags(total); 2022301SN/A 2032301SN/A iewExecStoreInsts 2042301SN/A .name(name() + ".EXEC:stores") 2052301SN/A .desc("Number of stores executed") 2062727Sktlim@umich.edu .flags(total); 2072727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2082727Sktlim@umich.edu 2092727Sktlim@umich.edu iewExecRate 2102727Sktlim@umich.edu .name(name() + ".EXEC:rate") 2112727Sktlim@umich.edu .desc("Inst execution rate") 2122727Sktlim@umich.edu .flags(total); 2132727Sktlim@umich.edu 2142727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2152301SN/A 2162301SN/A iewInstsToCommit 2176221Snate@binkert.org .init(cpu->numThreads) 2182301SN/A .name(name() + ".WB:sent") 2192301SN/A .desc("cumulative count of insts sent to commit") 2202727Sktlim@umich.edu .flags(total); 2212301SN/A 2222326SN/A writebackCount 2236221Snate@binkert.org .init(cpu->numThreads) 2242301SN/A .name(name() + ".WB:count") 2252301SN/A .desc("cumulative count of insts written-back") 2262727Sktlim@umich.edu .flags(total); 2272301SN/A 2282326SN/A producerInst 2296221Snate@binkert.org .init(cpu->numThreads) 2302301SN/A .name(name() + ".WB:producers") 2312301SN/A .desc("num instructions producing a value") 2322727Sktlim@umich.edu .flags(total); 2332301SN/A 2342326SN/A consumerInst 2356221Snate@binkert.org .init(cpu->numThreads) 2362301SN/A .name(name() + ".WB:consumers") 2372301SN/A .desc("num instructions consuming a value") 2382727Sktlim@umich.edu .flags(total); 2392301SN/A 2402326SN/A wbPenalized 2416221Snate@binkert.org .init(cpu->numThreads) 2422301SN/A .name(name() + ".WB:penalized") 2432301SN/A .desc("number of instrctions required to write to 'other' IQ") 2442727Sktlim@umich.edu .flags(total); 2452301SN/A 2462326SN/A wbPenalizedRate 2472301SN/A .name(name() + ".WB:penalized_rate") 2482301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2492727Sktlim@umich.edu .flags(total); 2502301SN/A 2512326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2522301SN/A 2532326SN/A wbFanout 2542301SN/A .name(name() + ".WB:fanout") 2552301SN/A .desc("average fanout of values written-back") 2562727Sktlim@umich.edu .flags(total); 2572301SN/A 2582326SN/A wbFanout = producerInst / consumerInst; 2592301SN/A 2602326SN/A wbRate 2612301SN/A .name(name() + ".WB:rate") 2622301SN/A .desc("insts written-back per cycle") 2632727Sktlim@umich.edu .flags(total); 2642326SN/A wbRate = writebackCount / cpu->numCycles; 2651062SN/A} 2661062SN/A 2671681SN/Atemplate<class Impl> 2681060SN/Avoid 2692292SN/ADefaultIEW<Impl>::initStage() 2701060SN/A{ 2716221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2722292SN/A toRename->iewInfo[tid].usedIQ = true; 2732292SN/A toRename->iewInfo[tid].freeIQEntries = 2742292SN/A instQueue.numFreeEntries(tid); 2752292SN/A 2762292SN/A toRename->iewInfo[tid].usedLSQ = true; 2772292SN/A toRename->iewInfo[tid].freeLSQEntries = 2782292SN/A ldstQueue.numFreeEntries(tid); 2792292SN/A } 2802292SN/A 2812733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 2821060SN/A} 2831060SN/A 2841681SN/Atemplate<class Impl> 2851060SN/Avoid 2862292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2871060SN/A{ 2881060SN/A timeBuffer = tb_ptr; 2891060SN/A 2901060SN/A // Setup wire to read information from time buffer, from commit. 2911060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 2921060SN/A 2931060SN/A // Setup wire to write information back to previous stages. 2941060SN/A toRename = timeBuffer->getWire(0); 2951060SN/A 2962292SN/A toFetch = timeBuffer->getWire(0); 2972292SN/A 2981060SN/A // Instruction queue also needs main time buffer. 2991060SN/A instQueue.setTimeBuffer(tb_ptr); 3001060SN/A} 3011060SN/A 3021681SN/Atemplate<class Impl> 3031060SN/Avoid 3042292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3051060SN/A{ 3061060SN/A renameQueue = rq_ptr; 3071060SN/A 3081060SN/A // Setup wire to read information from rename queue. 3091060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3101060SN/A} 3111060SN/A 3121681SN/Atemplate<class Impl> 3131060SN/Avoid 3142292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3151060SN/A{ 3161060SN/A iewQueue = iq_ptr; 3171060SN/A 3181060SN/A // Setup wire to write instructions to commit. 3191060SN/A toCommit = iewQueue->getWire(0); 3201060SN/A} 3211060SN/A 3221681SN/Atemplate<class Impl> 3231060SN/Avoid 3246221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3251060SN/A{ 3262292SN/A activeThreads = at_ptr; 3272292SN/A 3282292SN/A ldstQueue.setActiveThreads(at_ptr); 3292292SN/A instQueue.setActiveThreads(at_ptr); 3301060SN/A} 3311060SN/A 3321681SN/Atemplate<class Impl> 3331060SN/Avoid 3342292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3351060SN/A{ 3362292SN/A scoreboard = sb_ptr; 3371060SN/A} 3381060SN/A 3392307SN/Atemplate <class Impl> 3402863Sktlim@umich.edubool 3412843Sktlim@umich.eduDefaultIEW<Impl>::drain() 3422307SN/A{ 3432843Sktlim@umich.edu // IEW is ready to drain at any time. 3442843Sktlim@umich.edu cpu->signalDrained(); 3452863Sktlim@umich.edu return true; 3461681SN/A} 3471681SN/A 3482316SN/Atemplate <class Impl> 3491681SN/Avoid 3502843Sktlim@umich.eduDefaultIEW<Impl>::resume() 3512843Sktlim@umich.edu{ 3522843Sktlim@umich.edu} 3532843Sktlim@umich.edu 3542843Sktlim@umich.edutemplate <class Impl> 3552843Sktlim@umich.eduvoid 3562843Sktlim@umich.eduDefaultIEW<Impl>::switchOut() 3571681SN/A{ 3582348SN/A // Clear any state. 3592307SN/A switchedOut = true; 3602367SN/A assert(insts[0].empty()); 3612367SN/A assert(skidBuffer[0].empty()); 3621681SN/A 3632307SN/A instQueue.switchOut(); 3642307SN/A ldstQueue.switchOut(); 3652307SN/A fuPool->switchOut(); 3662307SN/A 3676221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3686221Snate@binkert.org while (!insts[tid].empty()) 3696221Snate@binkert.org insts[tid].pop(); 3706221Snate@binkert.org while (!skidBuffer[tid].empty()) 3716221Snate@binkert.org skidBuffer[tid].pop(); 3722307SN/A } 3731681SN/A} 3741681SN/A 3752307SN/Atemplate <class Impl> 3761681SN/Avoid 3772307SN/ADefaultIEW<Impl>::takeOverFrom() 3781060SN/A{ 3792348SN/A // Reset all state. 3802307SN/A _status = Active; 3812307SN/A exeStatus = Running; 3822307SN/A wbStatus = Idle; 3832307SN/A switchedOut = false; 3841060SN/A 3852307SN/A instQueue.takeOverFrom(); 3862307SN/A ldstQueue.takeOverFrom(); 3872307SN/A fuPool->takeOverFrom(); 3881060SN/A 3892307SN/A initStage(); 3902307SN/A cpu->activityThisCycle(); 3911060SN/A 3926221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3936221Snate@binkert.org dispatchStatus[tid] = Running; 3946221Snate@binkert.org stalls[tid].commit = false; 3956221Snate@binkert.org fetchRedirect[tid] = false; 3962307SN/A } 3971060SN/A 3982307SN/A updateLSQNextCycle = false; 3992307SN/A 4002873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4012307SN/A issueToExecQueue.advance(); 4021060SN/A } 4031060SN/A} 4041060SN/A 4051681SN/Atemplate<class Impl> 4061060SN/Avoid 4076221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4082107SN/A{ 4096221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4102107SN/A 4112292SN/A // Tell the IQ to start squashing. 4122292SN/A instQueue.squash(tid); 4132107SN/A 4142292SN/A // Tell the LDSTQ to start squashing. 4152326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4162292SN/A updatedQueues = true; 4172107SN/A 4182292SN/A // Clear the skid buffer in case it has any data in it. 4192935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4204632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4212935Sksewell@umich.edu 4222292SN/A while (!skidBuffer[tid].empty()) { 4232292SN/A if (skidBuffer[tid].front()->isLoad() || 4242292SN/A skidBuffer[tid].front()->isStore() ) { 4252292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4262292SN/A } 4272107SN/A 4282292SN/A toRename->iewInfo[tid].dispatched++; 4292107SN/A 4302292SN/A skidBuffer[tid].pop(); 4312292SN/A } 4322107SN/A 4332702Sktlim@umich.edu emptyRenameInsts(tid); 4342107SN/A} 4352107SN/A 4362107SN/Atemplate<class Impl> 4372107SN/Avoid 4386221Snate@binkert.orgDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4392292SN/A{ 4402292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 4412292SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4422292SN/A 4432292SN/A toCommit->squash[tid] = true; 4442292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4452292SN/A toCommit->mispredPC[tid] = inst->readPC(); 4462292SN/A toCommit->branchMispredict[tid] = true; 4472935Sksewell@umich.edu 4484632Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 4493969Sgblack@eecs.umich.edu int instSize = sizeof(TheISA::MachInst); 4504632Sgblack@eecs.umich.edu toCommit->branchTaken[tid] = 4513795Sgblack@eecs.umich.edu !(inst->readNextPC() + instSize == inst->readNextNPC() && 4523795Sgblack@eecs.umich.edu (inst->readNextPC() == inst->readPC() + instSize || 4533795Sgblack@eecs.umich.edu inst->readNextPC() == inst->readPC() + 2 * instSize)); 4543093Sksewell@umich.edu#else 4553093Sksewell@umich.edu toCommit->branchTaken[tid] = inst->readNextPC() != 4563093Sksewell@umich.edu (inst->readPC() + sizeof(TheISA::MachInst)); 4574632Sgblack@eecs.umich.edu#endif 4583093Sksewell@umich.edu toCommit->nextPC[tid] = inst->readNextPC(); 4594632Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextNPC(); 4604636Sgblack@eecs.umich.edu toCommit->nextMicroPC[tid] = inst->readNextMicroPC(); 4612292SN/A 4622292SN/A toCommit->includeSquashInst[tid] = false; 4632292SN/A 4642292SN/A wroteToTimeBuffer = true; 4652292SN/A} 4662292SN/A 4672292SN/Atemplate<class Impl> 4682292SN/Avoid 4696221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 4702292SN/A{ 4712292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4722292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4732292SN/A 4742292SN/A toCommit->squash[tid] = true; 4752292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4762292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 4773795Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextNPC(); 4783732Sktlim@umich.edu toCommit->branchMispredict[tid] = false; 4792292SN/A 4802292SN/A toCommit->includeSquashInst[tid] = false; 4812292SN/A 4822292SN/A wroteToTimeBuffer = true; 4832292SN/A} 4842292SN/A 4852292SN/Atemplate<class Impl> 4862292SN/Avoid 4876221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 4882292SN/A{ 4892292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 4902292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4912292SN/A 4922292SN/A toCommit->squash[tid] = true; 4932292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4942292SN/A toCommit->nextPC[tid] = inst->readPC(); 4953958Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextPC(); 4963732Sktlim@umich.edu toCommit->branchMispredict[tid] = false; 4972292SN/A 4982348SN/A // Must include the broadcasted SN in the squash. 4992292SN/A toCommit->includeSquashInst[tid] = true; 5002292SN/A 5012292SN/A ldstQueue.setLoadBlockedHandled(tid); 5022292SN/A 5032292SN/A wroteToTimeBuffer = true; 5042292SN/A} 5052292SN/A 5062292SN/Atemplate<class Impl> 5072292SN/Avoid 5086221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5092292SN/A{ 5102292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5112292SN/A 5122292SN/A if (dispatchStatus[tid] != Blocked && 5132292SN/A dispatchStatus[tid] != Unblocking) { 5142292SN/A toRename->iewBlock[tid] = true; 5152292SN/A wroteToTimeBuffer = true; 5162292SN/A } 5172292SN/A 5182292SN/A // Add the current inputs to the skid buffer so they can be 5192292SN/A // reprocessed when this stage unblocks. 5202292SN/A skidInsert(tid); 5212292SN/A 5222292SN/A dispatchStatus[tid] = Blocked; 5232292SN/A} 5242292SN/A 5252292SN/Atemplate<class Impl> 5262292SN/Avoid 5276221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5282292SN/A{ 5292292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5302292SN/A "buffer %u.\n",tid, tid); 5312292SN/A 5322292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5332292SN/A // Also switch status to running. 5342292SN/A if (skidBuffer[tid].empty()) { 5352292SN/A toRename->iewUnblock[tid] = true; 5362292SN/A wroteToTimeBuffer = true; 5372292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5382292SN/A dispatchStatus[tid] = Running; 5392292SN/A } 5402292SN/A} 5412292SN/A 5422292SN/Atemplate<class Impl> 5432292SN/Avoid 5442292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5451060SN/A{ 5461681SN/A instQueue.wakeDependents(inst); 5471060SN/A} 5481060SN/A 5492292SN/Atemplate<class Impl> 5502292SN/Avoid 5512292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5522292SN/A{ 5532292SN/A instQueue.rescheduleMemInst(inst); 5542292SN/A} 5551681SN/A 5561681SN/Atemplate<class Impl> 5571060SN/Avoid 5582292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5591060SN/A{ 5602292SN/A instQueue.replayMemInst(inst); 5612292SN/A} 5621060SN/A 5632292SN/Atemplate<class Impl> 5642292SN/Avoid 5652292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5662292SN/A{ 5673221Sktlim@umich.edu // This function should not be called after writebackInsts in a 5683221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 5693221Sktlim@umich.edu // being added to the queue to commit without being processed by 5703221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 5713221Sktlim@umich.edu 5722292SN/A // First check the time slot that this instruction will write 5732292SN/A // to. If there are free write ports at the time, then go ahead 5742292SN/A // and write the instruction to that time. If there are not, 5752292SN/A // keep looking back to see where's the first time there's a 5762326SN/A // free slot. 5772292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5782292SN/A ++wbNumInst; 5792820Sktlim@umich.edu if (wbNumInst == wbWidth) { 5802292SN/A ++wbCycle; 5812292SN/A wbNumInst = 0; 5822292SN/A } 5832292SN/A 5842353SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 5852292SN/A } 5862292SN/A 5872353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 5882353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 5892292SN/A // Add finished instruction to queue to commit. 5902292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 5912292SN/A (*iewQueue)[wbCycle].size++; 5922292SN/A} 5932292SN/A 5942292SN/Atemplate <class Impl> 5952292SN/Aunsigned 5962292SN/ADefaultIEW<Impl>::validInstsFromRename() 5972292SN/A{ 5982292SN/A unsigned inst_count = 0; 5992292SN/A 6002292SN/A for (int i=0; i<fromRename->size; i++) { 6012731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6022292SN/A inst_count++; 6032292SN/A } 6042292SN/A 6052292SN/A return inst_count; 6062292SN/A} 6072292SN/A 6082292SN/Atemplate<class Impl> 6092292SN/Avoid 6106221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6112292SN/A{ 6122292SN/A DynInstPtr inst = NULL; 6132292SN/A 6142292SN/A while (!insts[tid].empty()) { 6152292SN/A inst = insts[tid].front(); 6162292SN/A 6172292SN/A insts[tid].pop(); 6182292SN/A 6192292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6202292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6212292SN/A inst->readPC(),tid); 6222292SN/A 6232292SN/A skidBuffer[tid].push(inst); 6242292SN/A } 6252292SN/A 6262292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6272292SN/A "Skidbuffer Exceeded Max Size"); 6282292SN/A} 6292292SN/A 6302292SN/Atemplate<class Impl> 6312292SN/Aint 6322292SN/ADefaultIEW<Impl>::skidCount() 6332292SN/A{ 6342292SN/A int max=0; 6352292SN/A 6366221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6376221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6382292SN/A 6393867Sbinkertn@umich.edu while (threads != end) { 6406221Snate@binkert.org ThreadID tid = *threads++; 6413867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6422292SN/A if (max < thread_count) 6432292SN/A max = thread_count; 6442292SN/A } 6452292SN/A 6462292SN/A return max; 6472292SN/A} 6482292SN/A 6492292SN/Atemplate<class Impl> 6502292SN/Abool 6512292SN/ADefaultIEW<Impl>::skidsEmpty() 6522292SN/A{ 6536221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6546221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6552292SN/A 6563867Sbinkertn@umich.edu while (threads != end) { 6576221Snate@binkert.org ThreadID tid = *threads++; 6583867Sbinkertn@umich.edu 6593867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 6602292SN/A return false; 6612292SN/A } 6622292SN/A 6632292SN/A return true; 6641062SN/A} 6651062SN/A 6661681SN/Atemplate <class Impl> 6671062SN/Avoid 6682292SN/ADefaultIEW<Impl>::updateStatus() 6691062SN/A{ 6702292SN/A bool any_unblocking = false; 6711062SN/A 6726221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6736221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6741062SN/A 6753867Sbinkertn@umich.edu while (threads != end) { 6766221Snate@binkert.org ThreadID tid = *threads++; 6771062SN/A 6782292SN/A if (dispatchStatus[tid] == Unblocking) { 6792292SN/A any_unblocking = true; 6802292SN/A break; 6812292SN/A } 6822292SN/A } 6831062SN/A 6842292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 6852292SN/A // and there's no stores waiting to write back, and dispatch is not 6862292SN/A // unblocking, then there is no internal activity for the IEW stage. 6872292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 6882292SN/A !ldstQueue.willWB() && !any_unblocking) { 6892292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 6901062SN/A 6912292SN/A deactivateStage(); 6921062SN/A 6932292SN/A _status = Inactive; 6942292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 6952292SN/A ldstQueue.willWB() || 6962292SN/A any_unblocking)) { 6972292SN/A // Otherwise there is internal activity. Set to active. 6982292SN/A DPRINTF(IEW, "IEW switching to active\n"); 6991062SN/A 7002292SN/A activateStage(); 7011062SN/A 7022292SN/A _status = Active; 7031062SN/A } 7041062SN/A} 7051062SN/A 7061681SN/Atemplate <class Impl> 7071062SN/Avoid 7082292SN/ADefaultIEW<Impl>::resetEntries() 7091062SN/A{ 7102292SN/A instQueue.resetEntries(); 7112292SN/A ldstQueue.resetEntries(); 7122292SN/A} 7131062SN/A 7142292SN/Atemplate <class Impl> 7152292SN/Avoid 7166221Snate@binkert.orgDefaultIEW<Impl>::readStallSignals(ThreadID tid) 7172292SN/A{ 7182292SN/A if (fromCommit->commitBlock[tid]) { 7192292SN/A stalls[tid].commit = true; 7202292SN/A } 7211062SN/A 7222292SN/A if (fromCommit->commitUnblock[tid]) { 7232292SN/A assert(stalls[tid].commit); 7242292SN/A stalls[tid].commit = false; 7252292SN/A } 7262292SN/A} 7272292SN/A 7282292SN/Atemplate <class Impl> 7292292SN/Abool 7306221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7312292SN/A{ 7322292SN/A bool ret_val(false); 7332292SN/A 7342292SN/A if (stalls[tid].commit) { 7352292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7362292SN/A ret_val = true; 7372292SN/A } else if (instQueue.isFull(tid)) { 7382292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7392292SN/A ret_val = true; 7402292SN/A } else if (ldstQueue.isFull(tid)) { 7412292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7422292SN/A 7432292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7442292SN/A 7452292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7462292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7472292SN/A } 7482292SN/A 7492292SN/A if (ldstQueue.numStores(tid) > 0) { 7502292SN/A 7512292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7522292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7532292SN/A } 7542292SN/A 7552292SN/A ret_val = true; 7562292SN/A } else if (ldstQueue.isStalled(tid)) { 7572292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7582292SN/A ret_val = true; 7592292SN/A } 7602292SN/A 7612292SN/A return ret_val; 7622292SN/A} 7632292SN/A 7642292SN/Atemplate <class Impl> 7652292SN/Avoid 7666221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7672292SN/A{ 7682292SN/A // Check if there's a squash signal, squash if there is 7692292SN/A // Check stall signals, block if there is. 7702292SN/A // If status was Blocked 7712292SN/A // if so then go to unblocking 7722292SN/A // If status was Squashing 7732292SN/A // check if squashing is not high. Switch to running this cycle. 7742292SN/A 7752292SN/A readStallSignals(tid); 7762292SN/A 7772292SN/A if (fromCommit->commitInfo[tid].squash) { 7782292SN/A squash(tid); 7792292SN/A 7802292SN/A if (dispatchStatus[tid] == Blocked || 7812292SN/A dispatchStatus[tid] == Unblocking) { 7822292SN/A toRename->iewUnblock[tid] = true; 7832292SN/A wroteToTimeBuffer = true; 7842292SN/A } 7852292SN/A 7862292SN/A dispatchStatus[tid] = Squashing; 7872292SN/A 7882292SN/A fetchRedirect[tid] = false; 7892292SN/A return; 7902292SN/A } 7912292SN/A 7922292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7932702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 7942292SN/A 7952292SN/A dispatchStatus[tid] = Squashing; 7962292SN/A 7972702Sktlim@umich.edu emptyRenameInsts(tid); 7982702Sktlim@umich.edu wroteToTimeBuffer = true; 7992292SN/A return; 8002292SN/A } 8012292SN/A 8022292SN/A if (checkStall(tid)) { 8032292SN/A block(tid); 8042292SN/A dispatchStatus[tid] = Blocked; 8052292SN/A return; 8062292SN/A } 8072292SN/A 8082292SN/A if (dispatchStatus[tid] == Blocked) { 8092292SN/A // Status from previous cycle was blocked, but there are no more stall 8102292SN/A // conditions. Switch over to unblocking. 8112292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8122292SN/A tid); 8132292SN/A 8142292SN/A dispatchStatus[tid] = Unblocking; 8152292SN/A 8162292SN/A unblock(tid); 8172292SN/A 8182292SN/A return; 8192292SN/A } 8202292SN/A 8212292SN/A if (dispatchStatus[tid] == Squashing) { 8222292SN/A // Switch status to running if rename isn't being told to block or 8232292SN/A // squash this cycle. 8242292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8252292SN/A tid); 8262292SN/A 8272292SN/A dispatchStatus[tid] = Running; 8282292SN/A 8292292SN/A return; 8302292SN/A } 8312292SN/A} 8322292SN/A 8332292SN/Atemplate <class Impl> 8342292SN/Avoid 8352292SN/ADefaultIEW<Impl>::sortInsts() 8362292SN/A{ 8372292SN/A int insts_from_rename = fromRename->size; 8382326SN/A#ifdef DEBUG 8396221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8406221Snate@binkert.org assert(insts[tid].empty()); 8412326SN/A#endif 8422292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8432292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8442292SN/A } 8452292SN/A} 8462292SN/A 8472292SN/Atemplate <class Impl> 8482292SN/Avoid 8496221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8502702Sktlim@umich.edu{ 8514632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8522935Sksewell@umich.edu 8532702Sktlim@umich.edu while (!insts[tid].empty()) { 8542935Sksewell@umich.edu 8552702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8562702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8572702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8582702Sktlim@umich.edu } 8592702Sktlim@umich.edu 8602702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8612702Sktlim@umich.edu 8622702Sktlim@umich.edu insts[tid].pop(); 8632702Sktlim@umich.edu } 8642702Sktlim@umich.edu} 8652702Sktlim@umich.edu 8662702Sktlim@umich.edutemplate <class Impl> 8672702Sktlim@umich.eduvoid 8682292SN/ADefaultIEW<Impl>::wakeCPU() 8692292SN/A{ 8702292SN/A cpu->wakeCPU(); 8712292SN/A} 8722292SN/A 8732292SN/Atemplate <class Impl> 8742292SN/Avoid 8752292SN/ADefaultIEW<Impl>::activityThisCycle() 8762292SN/A{ 8772292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8782292SN/A cpu->activityThisCycle(); 8792292SN/A} 8802292SN/A 8812292SN/Atemplate <class Impl> 8822292SN/Ainline void 8832292SN/ADefaultIEW<Impl>::activateStage() 8842292SN/A{ 8852292SN/A DPRINTF(Activity, "Activating stage.\n"); 8862733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 8872292SN/A} 8882292SN/A 8892292SN/Atemplate <class Impl> 8902292SN/Ainline void 8912292SN/ADefaultIEW<Impl>::deactivateStage() 8922292SN/A{ 8932292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8942733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 8952292SN/A} 8962292SN/A 8972292SN/Atemplate<class Impl> 8982292SN/Avoid 8996221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9002292SN/A{ 9012292SN/A // If status is Running or idle, 9022292SN/A // call dispatchInsts() 9032292SN/A // If status is Unblocking, 9042292SN/A // buffer any instructions coming from rename 9052292SN/A // continue trying to empty skid buffer 9062292SN/A // check if stall conditions have passed 9072292SN/A 9082292SN/A if (dispatchStatus[tid] == Blocked) { 9092292SN/A ++iewBlockCycles; 9102292SN/A 9112292SN/A } else if (dispatchStatus[tid] == Squashing) { 9122292SN/A ++iewSquashCycles; 9132292SN/A } 9142292SN/A 9152292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9162292SN/A // will allow, as long as it is not currently blocked. 9172292SN/A if (dispatchStatus[tid] == Running || 9182292SN/A dispatchStatus[tid] == Idle) { 9192292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9202292SN/A "dispatch.\n", tid); 9212292SN/A 9222292SN/A dispatchInsts(tid); 9232292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9242292SN/A // Make sure that the skid buffer has something in it if the 9252292SN/A // status is unblocking. 9262292SN/A assert(!skidsEmpty()); 9272292SN/A 9282292SN/A // If the status was unblocking, then instructions from the skid 9292292SN/A // buffer were used. Remove those instructions and handle 9302292SN/A // the rest of unblocking. 9312292SN/A dispatchInsts(tid); 9322292SN/A 9332292SN/A ++iewUnblockCycles; 9342292SN/A 9355215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9362292SN/A // Add the current inputs to the skid buffer so they can be 9372292SN/A // reprocessed when this stage unblocks. 9382292SN/A skidInsert(tid); 9392292SN/A } 9402292SN/A 9412292SN/A unblock(tid); 9422292SN/A } 9432292SN/A} 9442292SN/A 9452292SN/Atemplate <class Impl> 9462292SN/Avoid 9476221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9482292SN/A{ 9492292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9502292SN/A // otherwise. 9512292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9522292SN/A dispatchStatus[tid] == Unblocking ? 9532292SN/A skidBuffer[tid] : insts[tid]; 9542292SN/A 9552292SN/A int insts_to_add = insts_to_dispatch.size(); 9562292SN/A 9572292SN/A DynInstPtr inst; 9582292SN/A bool add_to_iq = false; 9592292SN/A int dis_num_inst = 0; 9602292SN/A 9612292SN/A // Loop through the instructions, putting them in the instruction 9622292SN/A // queue. 9632292SN/A for ( ; dis_num_inst < insts_to_add && 9642820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9652292SN/A ++dis_num_inst) 9662292SN/A { 9672292SN/A inst = insts_to_dispatch.front(); 9682292SN/A 9692292SN/A if (dispatchStatus[tid] == Unblocking) { 9702292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9712292SN/A "buffer\n", tid); 9722292SN/A } 9732292SN/A 9742292SN/A // Make sure there's a valid instruction there. 9752292SN/A assert(inst); 9762292SN/A 9772292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 9782292SN/A "IQ.\n", 9792292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 9802292SN/A 9812292SN/A // Be sure to mark these instructions as ready so that the 9822292SN/A // commit stage can go ahead and execute them, and mark 9832292SN/A // them as issued so the IQ doesn't reprocess them. 9842292SN/A 9852292SN/A // Check for squashed instructions. 9862292SN/A if (inst->isSquashed()) { 9872292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9882292SN/A "not adding to IQ.\n", tid); 9892292SN/A 9902292SN/A ++iewDispSquashedInsts; 9912292SN/A 9922292SN/A insts_to_dispatch.pop(); 9932292SN/A 9942292SN/A //Tell Rename That An Instruction has been processed 9952292SN/A if (inst->isLoad() || inst->isStore()) { 9962292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 9972292SN/A } 9982292SN/A toRename->iewInfo[tid].dispatched++; 9992292SN/A 10002292SN/A continue; 10012292SN/A } 10022292SN/A 10032292SN/A // Check for full conditions. 10042292SN/A if (instQueue.isFull(tid)) { 10052292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10062292SN/A 10072292SN/A // Call function to start blocking. 10082292SN/A block(tid); 10092292SN/A 10102292SN/A // Set unblock to false. Special case where we are using 10112292SN/A // skidbuffer (unblocking) instructions but then we still 10122292SN/A // get full in the IQ. 10132292SN/A toRename->iewUnblock[tid] = false; 10142292SN/A 10152292SN/A ++iewIQFullEvents; 10162292SN/A break; 10172292SN/A } else if (ldstQueue.isFull(tid)) { 10182292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10192292SN/A 10202292SN/A // Call function to start blocking. 10212292SN/A block(tid); 10222292SN/A 10232292SN/A // Set unblock to false. Special case where we are using 10242292SN/A // skidbuffer (unblocking) instructions but then we still 10252292SN/A // get full in the IQ. 10262292SN/A toRename->iewUnblock[tid] = false; 10272292SN/A 10282292SN/A ++iewLSQFullEvents; 10292292SN/A break; 10302292SN/A } 10312292SN/A 10322292SN/A // Otherwise issue the instruction just fine. 10332292SN/A if (inst->isLoad()) { 10342292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10352292SN/A "encountered, adding to LSQ.\n", tid); 10362292SN/A 10372292SN/A // Reserve a spot in the load store queue for this 10382292SN/A // memory access. 10392292SN/A ldstQueue.insertLoad(inst); 10402292SN/A 10412292SN/A ++iewDispLoadInsts; 10422292SN/A 10432292SN/A add_to_iq = true; 10442292SN/A 10452292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10462292SN/A } else if (inst->isStore()) { 10472292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10482292SN/A "encountered, adding to LSQ.\n", tid); 10492292SN/A 10502292SN/A ldstQueue.insertStore(inst); 10512292SN/A 10522292SN/A ++iewDispStoreInsts; 10532292SN/A 10542336SN/A if (inst->isStoreConditional()) { 10552336SN/A // Store conditionals need to be set as "canCommit()" 10562336SN/A // so that commit can process them when they reach the 10572336SN/A // head of commit. 10582348SN/A // @todo: This is somewhat specific to Alpha. 10592292SN/A inst->setCanCommit(); 10602292SN/A instQueue.insertNonSpec(inst); 10612292SN/A add_to_iq = false; 10622292SN/A 10632292SN/A ++iewDispNonSpecInsts; 10642292SN/A } else { 10652292SN/A add_to_iq = true; 10662292SN/A } 10672292SN/A 10682292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10692292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10702326SN/A // Same as non-speculative stores. 10712292SN/A inst->setCanCommit(); 10722292SN/A instQueue.insertBarrier(inst); 10732292SN/A add_to_iq = false; 10742292SN/A } else if (inst->isNop()) { 10752292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10762292SN/A "skipping.\n", tid); 10772292SN/A 10782292SN/A inst->setIssued(); 10792292SN/A inst->setExecuted(); 10802292SN/A inst->setCanCommit(); 10812292SN/A 10822326SN/A instQueue.recordProducer(inst); 10832292SN/A 10842727Sktlim@umich.edu iewExecutedNop[tid]++; 10852301SN/A 10862292SN/A add_to_iq = false; 10872292SN/A } else if (inst->isExecuted()) { 10882292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 10892292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 10902292SN/A "skipping.\n"); 10912292SN/A 10922292SN/A inst->setIssued(); 10932292SN/A inst->setCanCommit(); 10942292SN/A 10952326SN/A instQueue.recordProducer(inst); 10962292SN/A 10972292SN/A add_to_iq = false; 10982292SN/A } else { 10992292SN/A add_to_iq = true; 11002292SN/A } 11014033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11024033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11034033Sktlim@umich.edu "encountered, skipping.\n", tid); 11044033Sktlim@umich.edu 11054033Sktlim@umich.edu // Same as non-speculative stores. 11064033Sktlim@umich.edu inst->setCanCommit(); 11074033Sktlim@umich.edu 11084033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11094033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11104033Sktlim@umich.edu 11114033Sktlim@umich.edu ++iewDispNonSpecInsts; 11124033Sktlim@umich.edu 11134033Sktlim@umich.edu add_to_iq = false; 11144033Sktlim@umich.edu } 11152292SN/A 11162292SN/A // If the instruction queue is not full, then add the 11172292SN/A // instruction. 11182292SN/A if (add_to_iq) { 11192292SN/A instQueue.insert(inst); 11202292SN/A } 11212292SN/A 11222292SN/A insts_to_dispatch.pop(); 11232292SN/A 11242292SN/A toRename->iewInfo[tid].dispatched++; 11252292SN/A 11262292SN/A ++iewDispatchedInsts; 11272292SN/A } 11282292SN/A 11292292SN/A if (!insts_to_dispatch.empty()) { 11302935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11312292SN/A block(tid); 11322292SN/A toRename->iewUnblock[tid] = false; 11332292SN/A } 11342292SN/A 11352292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11362292SN/A dispatchStatus[tid] = Running; 11372292SN/A 11382292SN/A updatedQueues = true; 11392292SN/A } 11402292SN/A 11412292SN/A dis_num_inst = 0; 11422292SN/A} 11432292SN/A 11442292SN/Atemplate <class Impl> 11452292SN/Avoid 11462292SN/ADefaultIEW<Impl>::printAvailableInsts() 11472292SN/A{ 11482292SN/A int inst = 0; 11492292SN/A 11502980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11512292SN/A 11522292SN/A while (fromIssue->insts[inst]) { 11532292SN/A 11542980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11552292SN/A 11562980Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->readPC() 11572292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11582292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11592292SN/A 11602292SN/A inst++; 11612292SN/A 11622292SN/A } 11632292SN/A 11642980Sgblack@eecs.umich.edu std::cout << "\n"; 11652292SN/A} 11662292SN/A 11672292SN/Atemplate <class Impl> 11682292SN/Avoid 11692292SN/ADefaultIEW<Impl>::executeInsts() 11702292SN/A{ 11712292SN/A wbNumInst = 0; 11722292SN/A wbCycle = 0; 11732292SN/A 11746221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 11756221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 11762292SN/A 11773867Sbinkertn@umich.edu while (threads != end) { 11786221Snate@binkert.org ThreadID tid = *threads++; 11792292SN/A fetchRedirect[tid] = false; 11802292SN/A } 11812292SN/A 11822698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 11832698Sktlim@umich.edu// printAvailableInsts(); 11841062SN/A 11851062SN/A // Execute/writeback any instructions that are available. 11862333SN/A int insts_to_execute = fromIssue->size; 11872292SN/A int inst_num = 0; 11882333SN/A for (; inst_num < insts_to_execute; 11892326SN/A ++inst_num) { 11901062SN/A 11912292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 11921062SN/A 11932333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 11941062SN/A 11952292SN/A DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 11962292SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 11971062SN/A 11981062SN/A // Check if the instruction is squashed; if so then skip it 11991062SN/A if (inst->isSquashed()) { 12002292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 12011062SN/A 12021062SN/A // Consider this instruction executed so that commit can go 12031062SN/A // ahead and retire the instruction. 12041062SN/A inst->setExecuted(); 12051062SN/A 12062292SN/A // Not sure if I should set this here or just let commit try to 12072292SN/A // commit any squashed instructions. I like the latter a bit more. 12082292SN/A inst->setCanCommit(); 12091062SN/A 12101062SN/A ++iewExecSquashedInsts; 12111062SN/A 12122820Sktlim@umich.edu decrWb(inst->seqNum); 12131062SN/A continue; 12141062SN/A } 12151062SN/A 12162292SN/A Fault fault = NoFault; 12171062SN/A 12181062SN/A // Execute instruction. 12191062SN/A // Note that if the instruction faults, it will be handled 12201062SN/A // at the commit stage. 12212292SN/A if (inst->isMemRef() && 12222292SN/A (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12232292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12241062SN/A "reference.\n"); 12251062SN/A 12261062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12271062SN/A if (inst->isLoad()) { 12282292SN/A // Loads will mark themselves as executed, and their writeback 12292292SN/A // event adds the instruction to the queue to commit 12302292SN/A fault = ldstQueue.executeLoad(inst); 12311062SN/A } else if (inst->isStore()) { 12322367SN/A fault = ldstQueue.executeStore(inst); 12331062SN/A 12342292SN/A // If the store had a fault then it may not have a mem req 12352367SN/A if (!inst->isStoreConditional() && fault == NoFault) { 12362292SN/A inst->setExecuted(); 12372292SN/A 12382292SN/A instToCommit(inst); 12392367SN/A } else if (fault != NoFault) { 12402367SN/A // If the instruction faulted, then we need to send it along to commit 12412367SN/A // without the instruction completing. 12423732Sktlim@umich.edu DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n", 12433732Sktlim@umich.edu fault->name(), inst->seqNum); 12442367SN/A 12452367SN/A // Send this instruction to commit, also make sure iew stage 12462367SN/A // realizes there is activity. 12472367SN/A inst->setExecuted(); 12482367SN/A 12492367SN/A instToCommit(inst); 12502367SN/A activityThisCycle(); 12512292SN/A } 12522326SN/A 12532326SN/A // Store conditionals will mark themselves as 12542326SN/A // executed, and their writeback event will add the 12552326SN/A // instruction to the queue to commit. 12561062SN/A } else { 12572292SN/A panic("Unexpected memory type!\n"); 12581062SN/A } 12591062SN/A 12601062SN/A } else { 12611062SN/A inst->execute(); 12621062SN/A 12632292SN/A inst->setExecuted(); 12642292SN/A 12652292SN/A instToCommit(inst); 12661062SN/A } 12671062SN/A 12682301SN/A updateExeInstStats(inst); 12691681SN/A 12702326SN/A // Check if branch prediction was correct, if not then we need 12712326SN/A // to tell commit to squash in flight instructions. Only 12722326SN/A // handle this if there hasn't already been something that 12732107SN/A // redirects fetch in this group of instructions. 12741681SN/A 12752292SN/A // This probably needs to prioritize the redirects if a different 12762292SN/A // scheduler is used. Currently the scheduler schedules the oldest 12772292SN/A // instruction first, so the branch resolution order will be correct. 12786221Snate@binkert.org ThreadID tid = inst->threadNumber; 12791062SN/A 12803732Sktlim@umich.edu if (!fetchRedirect[tid] || 12813732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 12821062SN/A 12831062SN/A if (inst->mispredicted()) { 12842292SN/A fetchRedirect[tid] = true; 12851062SN/A 12862292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 12876036Sksewell@umich.edu DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 12883969Sgblack@eecs.umich.edu inst->readPredPC(), inst->readPredNPC()); 12893969Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 12903969Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->readNextPC(), 12913969Sgblack@eecs.umich.edu inst->readNextNPC()); 12921062SN/A // If incorrect, then signal the ROB that it must be squashed. 12932292SN/A squashDueToBranch(inst, tid); 12941062SN/A 12953795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 12961062SN/A predictedTakenIncorrect++; 12972292SN/A } else { 12982292SN/A predictedNotTakenIncorrect++; 12991062SN/A } 13002292SN/A } else if (ldstQueue.violation(tid)) { 13014033Sktlim@umich.edu assert(inst->isMemRef()); 13022326SN/A // If there was an ordering violation, then get the 13032326SN/A // DynInst that caused the violation. Note that this 13042292SN/A // clears the violation signal. 13052292SN/A DynInstPtr violator; 13062292SN/A violator = ldstQueue.getMemDepViolator(tid); 13071062SN/A 13082292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13091062SN/A "%#x, inst PC: %#x. Addr is: %#x.\n", 13101062SN/A violator->readPC(), inst->readPC(), inst->physEffAddr); 13111062SN/A 13123732Sktlim@umich.edu // Ensure the violating instruction is older than 13133732Sktlim@umich.edu // current squash 13144033Sktlim@umich.edu/* if (fetchRedirect[tid] && 13154033Sktlim@umich.edu violator->seqNum >= toCommit->squashedSeqNum[tid] + 1) 13163732Sktlim@umich.edu continue; 13174033Sktlim@umich.edu*/ 13183732Sktlim@umich.edu fetchRedirect[tid] = true; 13193732Sktlim@umich.edu 13201062SN/A // Tell the instruction queue that a violation has occured. 13211062SN/A instQueue.violation(inst, violator); 13221062SN/A 13231062SN/A // Squash. 13242292SN/A squashDueToMemOrder(inst,tid); 13251062SN/A 13261062SN/A ++memOrderViolationEvents; 13272292SN/A } else if (ldstQueue.loadBlocked(tid) && 13282292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13292292SN/A fetchRedirect[tid] = true; 13302292SN/A 13312292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13322292SN/A "memory system is blocked. PC: %#x [sn:%lli]\n", 13332292SN/A inst->readPC(), inst->seqNum); 13342292SN/A 13352292SN/A squashDueToMemBlocked(inst, tid); 13361062SN/A } 13374033Sktlim@umich.edu } else { 13384033Sktlim@umich.edu // Reset any state associated with redirects that will not 13394033Sktlim@umich.edu // be used. 13404033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 13414033Sktlim@umich.edu assert(inst->isMemRef()); 13424033Sktlim@umich.edu 13434033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13444033Sktlim@umich.edu 13454033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13464033Sktlim@umich.edu "%#x, inst PC: %#x. Addr is: %#x.\n", 13474033Sktlim@umich.edu violator->readPC(), inst->readPC(), inst->physEffAddr); 13484033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 13494033Sktlim@umich.edu "already squashing\n"); 13504033Sktlim@umich.edu 13514033Sktlim@umich.edu ++memOrderViolationEvents; 13524033Sktlim@umich.edu } 13534033Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 13544033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 13554033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 13564033Sktlim@umich.edu "memory system is blocked. PC: %#x [sn:%lli]\n", 13574033Sktlim@umich.edu inst->readPC(), inst->seqNum); 13584033Sktlim@umich.edu DPRINTF(IEW, "Blocked load will not be handled because " 13594033Sktlim@umich.edu "already squashing\n"); 13604033Sktlim@umich.edu 13614033Sktlim@umich.edu ldstQueue.setLoadBlockedHandled(tid); 13624033Sktlim@umich.edu } 13634033Sktlim@umich.edu 13641062SN/A } 13651062SN/A } 13662292SN/A 13672348SN/A // Update and record activity if we processed any instructions. 13682292SN/A if (inst_num) { 13692292SN/A if (exeStatus == Idle) { 13702292SN/A exeStatus = Running; 13712292SN/A } 13722292SN/A 13732292SN/A updatedQueues = true; 13742292SN/A 13752292SN/A cpu->activityThisCycle(); 13762292SN/A } 13772292SN/A 13782292SN/A // Need to reset this in case a writeback event needs to write into the 13792292SN/A // iew queue. That way the writeback event will write into the correct 13802292SN/A // spot in the queue. 13812292SN/A wbNumInst = 0; 13822107SN/A} 13832107SN/A 13842292SN/Atemplate <class Impl> 13852107SN/Avoid 13862292SN/ADefaultIEW<Impl>::writebackInsts() 13872107SN/A{ 13882326SN/A // Loop through the head of the time buffer and wake any 13892326SN/A // dependents. These instructions are about to write back. Also 13902326SN/A // mark scoreboard that this instruction is finally complete. 13912326SN/A // Either have IEW have direct access to scoreboard, or have this 13922326SN/A // as part of backwards communication. 13933958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 13942292SN/A toCommit->insts[inst_num]; inst_num++) { 13952107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 13966221Snate@binkert.org ThreadID tid = inst->threadNumber; 13972107SN/A 13982698Sktlim@umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 13992698Sktlim@umich.edu inst->seqNum, inst->readPC()); 14002107SN/A 14012301SN/A iewInstsToCommit[tid]++; 14022301SN/A 14032292SN/A // Some instructions will be sent to commit without having 14042292SN/A // executed because they need commit to handle them. 14052292SN/A // E.g. Uncached loads have not actually executed when they 14062292SN/A // are first sent to commit. Instead commit must tell the LSQ 14072292SN/A // when it's ready to execute the uncached load. 14082367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14092301SN/A int dependents = instQueue.wakeDependents(inst); 14102107SN/A 14112292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14122292SN/A //mark as Ready 14132292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14142292SN/A inst->renamedDestRegIdx(i)); 14152292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14162107SN/A } 14172301SN/A 14182348SN/A if (dependents) { 14192348SN/A producerInst[tid]++; 14202348SN/A consumerInst[tid]+= dependents; 14212348SN/A } 14222326SN/A writebackCount[tid]++; 14232107SN/A } 14242820Sktlim@umich.edu 14252820Sktlim@umich.edu decrWb(inst->seqNum); 14262107SN/A } 14271060SN/A} 14281060SN/A 14291681SN/Atemplate<class Impl> 14301060SN/Avoid 14312292SN/ADefaultIEW<Impl>::tick() 14321060SN/A{ 14332292SN/A wbNumInst = 0; 14342292SN/A wbCycle = 0; 14351060SN/A 14362292SN/A wroteToTimeBuffer = false; 14372292SN/A updatedQueues = false; 14381060SN/A 14392292SN/A sortInsts(); 14401060SN/A 14412326SN/A // Free function units marked as being freed this cycle. 14422326SN/A fuPool->processFreeUnits(); 14431062SN/A 14446221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 14456221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 14461060SN/A 14472326SN/A // Check stall and squash signals, dispatch any instructions. 14483867Sbinkertn@umich.edu while (threads != end) { 14496221Snate@binkert.org ThreadID tid = *threads++; 14501060SN/A 14512292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14521060SN/A 14532292SN/A checkSignalsAndUpdate(tid); 14542292SN/A dispatch(tid); 14551060SN/A } 14561060SN/A 14572292SN/A if (exeStatus != Squashing) { 14582292SN/A executeInsts(); 14591060SN/A 14602292SN/A writebackInsts(); 14612292SN/A 14622292SN/A // Have the instruction queue try to schedule any ready instructions. 14632292SN/A // (In actuality, this scheduling is for instructions that will 14642292SN/A // be executed next cycle.) 14652292SN/A instQueue.scheduleReadyInsts(); 14662292SN/A 14672292SN/A // Also should advance its own time buffers if the stage ran. 14682292SN/A // Not the best place for it, but this works (hopefully). 14692292SN/A issueToExecQueue.advance(); 14702292SN/A } 14712292SN/A 14722292SN/A bool broadcast_free_entries = false; 14732292SN/A 14742292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14752292SN/A exeStatus = Idle; 14762292SN/A updateLSQNextCycle = false; 14772292SN/A 14782292SN/A broadcast_free_entries = true; 14792292SN/A } 14802292SN/A 14812292SN/A // Writeback any stores using any leftover bandwidth. 14821681SN/A ldstQueue.writebackStores(); 14831681SN/A 14841061SN/A // Check the committed load/store signals to see if there's a load 14851061SN/A // or store to commit. Also check if it's being told to execute a 14861061SN/A // nonspeculative instruction. 14871681SN/A // This is pretty inefficient... 14882292SN/A 14893867Sbinkertn@umich.edu threads = activeThreads->begin(); 14903867Sbinkertn@umich.edu while (threads != end) { 14916221Snate@binkert.org ThreadID tid = (*threads++); 14922292SN/A 14932292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 14942292SN/A 14952348SN/A // Update structures based on instructions committed. 14962292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 14972292SN/A !fromCommit->commitInfo[tid].squash && 14982292SN/A !fromCommit->commitInfo[tid].robSquashing) { 14992292SN/A 15002292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15012292SN/A 15022292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15032292SN/A 15042292SN/A updateLSQNextCycle = true; 15052292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15062292SN/A } 15072292SN/A 15082292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15092292SN/A 15102292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15112292SN/A if (fromCommit->commitInfo[tid].uncached) { 15122292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15134033Sktlim@umich.edu fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15142292SN/A } else { 15152292SN/A instQueue.scheduleNonSpec( 15162292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15172292SN/A } 15182292SN/A } 15192292SN/A 15202292SN/A if (broadcast_free_entries) { 15212292SN/A toFetch->iewInfo[tid].iqCount = 15222292SN/A instQueue.getCount(tid); 15232292SN/A toFetch->iewInfo[tid].ldstqCount = 15242292SN/A ldstQueue.getCount(tid); 15252292SN/A 15262292SN/A toRename->iewInfo[tid].usedIQ = true; 15272292SN/A toRename->iewInfo[tid].freeIQEntries = 15282292SN/A instQueue.numFreeEntries(); 15292292SN/A toRename->iewInfo[tid].usedLSQ = true; 15302292SN/A toRename->iewInfo[tid].freeLSQEntries = 15312292SN/A ldstQueue.numFreeEntries(tid); 15322292SN/A 15332292SN/A wroteToTimeBuffer = true; 15342292SN/A } 15352292SN/A 15362292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15372292SN/A tid, toRename->iewInfo[tid].dispatched); 15381061SN/A } 15391061SN/A 15402292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15412292SN/A "LSQ has %i free entries.\n", 15422292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15432292SN/A ldstQueue.numFreeEntries()); 15442292SN/A 15452292SN/A updateStatus(); 15462292SN/A 15472292SN/A if (wroteToTimeBuffer) { 15482292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15492292SN/A cpu->activityThisCycle(); 15501061SN/A } 15511060SN/A} 15521060SN/A 15532301SN/Atemplate <class Impl> 15541060SN/Avoid 15552301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 15561060SN/A{ 15576221Snate@binkert.org ThreadID tid = inst->threadNumber; 15581060SN/A 15592301SN/A // 15602301SN/A // Pick off the software prefetches 15612301SN/A // 15622301SN/A#ifdef TARGET_ALPHA 15632301SN/A if (inst->isDataPrefetch()) 15646221Snate@binkert.org iewExecutedSwp[tid]++; 15652301SN/A else 15662727Sktlim@umich.edu iewIewExecutedcutedInsts++; 15672301SN/A#else 15682669Sktlim@umich.edu iewExecutedInsts++; 15692301SN/A#endif 15701060SN/A 15712301SN/A // 15722301SN/A // Control operations 15732301SN/A // 15742301SN/A if (inst->isControl()) 15756221Snate@binkert.org iewExecutedBranches[tid]++; 15761060SN/A 15772301SN/A // 15782301SN/A // Memory operations 15792301SN/A // 15802301SN/A if (inst->isMemRef()) { 15816221Snate@binkert.org iewExecutedRefs[tid]++; 15821060SN/A 15832301SN/A if (inst->isLoad()) { 15846221Snate@binkert.org iewExecLoadInsts[tid]++; 15851060SN/A } 15861060SN/A } 15871060SN/A} 1588