iew_impl.hh revision 6658
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31// @todo: Fix the instantaneous communication among all the stages within 32// iew. There's a clear delay between issue and execute, yet backwards 33// communication happens simultaneously. 34 35#include <queue> 36 37#include "base/timebuf.hh" 38#include "config/the_isa.hh" 39#include "cpu/o3/fu_pool.hh" 40#include "cpu/o3/iew.hh" 41#include "params/DerivO3CPU.hh" 42 43using namespace std; 44 45template<class Impl> 46DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 47 : issueToExecQueue(params->backComSize, params->forwardComSize), 48 cpu(_cpu), 49 instQueue(_cpu, this, params), 50 ldstQueue(_cpu, this, params), 51 fuPool(params->fuPool), 52 commitToIEWDelay(params->commitToIEWDelay), 53 renameToIEWDelay(params->renameToIEWDelay), 54 issueToExecuteDelay(params->issueToExecuteDelay), 55 dispatchWidth(params->dispatchWidth), 56 issueWidth(params->issueWidth), 57 wbOutstanding(0), 58 wbWidth(params->wbWidth), 59 numThreads(params->numThreads), 60 switchedOut(false) 61{ 62 _status = Active; 63 exeStatus = Running; 64 wbStatus = Idle; 65 66 // Setup wire to read instructions coming from issue. 67 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 68 69 // Instruction queue needs the queue between issue and execute. 70 instQueue.setIssueToExecuteQueue(&issueToExecQueue); 71 72 for (ThreadID tid = 0; tid < numThreads; tid++) { 73 dispatchStatus[tid] = Running; 74 stalls[tid].commit = false; 75 fetchRedirect[tid] = false; 76 } 77 78 wbMax = wbWidth * params->wbDepth; 79 80 updateLSQNextCycle = false; 81 82 ableToIssue = true; 83 84 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 85} 86 87template <class Impl> 88std::string 89DefaultIEW<Impl>::name() const 90{ 91 return cpu->name() + ".iew"; 92} 93 94template <class Impl> 95void 96DefaultIEW<Impl>::regStats() 97{ 98 using namespace Stats; 99 100 instQueue.regStats(); 101 ldstQueue.regStats(); 102 103 iewIdleCycles 104 .name(name() + ".iewIdleCycles") 105 .desc("Number of cycles IEW is idle"); 106 107 iewSquashCycles 108 .name(name() + ".iewSquashCycles") 109 .desc("Number of cycles IEW is squashing"); 110 111 iewBlockCycles 112 .name(name() + ".iewBlockCycles") 113 .desc("Number of cycles IEW is blocking"); 114 115 iewUnblockCycles 116 .name(name() + ".iewUnblockCycles") 117 .desc("Number of cycles IEW is unblocking"); 118 119 iewDispatchedInsts 120 .name(name() + ".iewDispatchedInsts") 121 .desc("Number of instructions dispatched to IQ"); 122 123 iewDispSquashedInsts 124 .name(name() + ".iewDispSquashedInsts") 125 .desc("Number of squashed instructions skipped by dispatch"); 126 127 iewDispLoadInsts 128 .name(name() + ".iewDispLoadInsts") 129 .desc("Number of dispatched load instructions"); 130 131 iewDispStoreInsts 132 .name(name() + ".iewDispStoreInsts") 133 .desc("Number of dispatched store instructions"); 134 135 iewDispNonSpecInsts 136 .name(name() + ".iewDispNonSpecInsts") 137 .desc("Number of dispatched non-speculative instructions"); 138 139 iewIQFullEvents 140 .name(name() + ".iewIQFullEvents") 141 .desc("Number of times the IQ has become full, causing a stall"); 142 143 iewLSQFullEvents 144 .name(name() + ".iewLSQFullEvents") 145 .desc("Number of times the LSQ has become full, causing a stall"); 146 147 memOrderViolationEvents 148 .name(name() + ".memOrderViolationEvents") 149 .desc("Number of memory order violations"); 150 151 predictedTakenIncorrect 152 .name(name() + ".predictedTakenIncorrect") 153 .desc("Number of branches that were predicted taken incorrectly"); 154 155 predictedNotTakenIncorrect 156 .name(name() + ".predictedNotTakenIncorrect") 157 .desc("Number of branches that were predicted not taken incorrectly"); 158 159 branchMispredicts 160 .name(name() + ".branchMispredicts") 161 .desc("Number of branch mispredicts detected at execute"); 162 163 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 164 165 iewExecutedInsts 166 .name(name() + ".iewExecutedInsts") 167 .desc("Number of executed instructions"); 168 169 iewExecLoadInsts 170 .init(cpu->numThreads) 171 .name(name() + ".iewExecLoadInsts") 172 .desc("Number of load instructions executed") 173 .flags(total); 174 175 iewExecSquashedInsts 176 .name(name() + ".iewExecSquashedInsts") 177 .desc("Number of squashed instructions skipped in execute"); 178 179 iewExecutedSwp 180 .init(cpu->numThreads) 181 .name(name() + ".EXEC:swp") 182 .desc("number of swp insts executed") 183 .flags(total); 184 185 iewExecutedNop 186 .init(cpu->numThreads) 187 .name(name() + ".EXEC:nop") 188 .desc("number of nop insts executed") 189 .flags(total); 190 191 iewExecutedRefs 192 .init(cpu->numThreads) 193 .name(name() + ".EXEC:refs") 194 .desc("number of memory reference insts executed") 195 .flags(total); 196 197 iewExecutedBranches 198 .init(cpu->numThreads) 199 .name(name() + ".EXEC:branches") 200 .desc("Number of branches executed") 201 .flags(total); 202 203 iewExecStoreInsts 204 .name(name() + ".EXEC:stores") 205 .desc("Number of stores executed") 206 .flags(total); 207 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 208 209 iewExecRate 210 .name(name() + ".EXEC:rate") 211 .desc("Inst execution rate") 212 .flags(total); 213 214 iewExecRate = iewExecutedInsts / cpu->numCycles; 215 216 iewInstsToCommit 217 .init(cpu->numThreads) 218 .name(name() + ".WB:sent") 219 .desc("cumulative count of insts sent to commit") 220 .flags(total); 221 222 writebackCount 223 .init(cpu->numThreads) 224 .name(name() + ".WB:count") 225 .desc("cumulative count of insts written-back") 226 .flags(total); 227 228 producerInst 229 .init(cpu->numThreads) 230 .name(name() + ".WB:producers") 231 .desc("num instructions producing a value") 232 .flags(total); 233 234 consumerInst 235 .init(cpu->numThreads) 236 .name(name() + ".WB:consumers") 237 .desc("num instructions consuming a value") 238 .flags(total); 239 240 wbPenalized 241 .init(cpu->numThreads) 242 .name(name() + ".WB:penalized") 243 .desc("number of instrctions required to write to 'other' IQ") 244 .flags(total); 245 246 wbPenalizedRate 247 .name(name() + ".WB:penalized_rate") 248 .desc ("fraction of instructions written-back that wrote to 'other' IQ") 249 .flags(total); 250 251 wbPenalizedRate = wbPenalized / writebackCount; 252 253 wbFanout 254 .name(name() + ".WB:fanout") 255 .desc("average fanout of values written-back") 256 .flags(total); 257 258 wbFanout = producerInst / consumerInst; 259 260 wbRate 261 .name(name() + ".WB:rate") 262 .desc("insts written-back per cycle") 263 .flags(total); 264 wbRate = writebackCount / cpu->numCycles; 265} 266 267template<class Impl> 268void 269DefaultIEW<Impl>::initStage() 270{ 271 for (ThreadID tid = 0; tid < numThreads; tid++) { 272 toRename->iewInfo[tid].usedIQ = true; 273 toRename->iewInfo[tid].freeIQEntries = 274 instQueue.numFreeEntries(tid); 275 276 toRename->iewInfo[tid].usedLSQ = true; 277 toRename->iewInfo[tid].freeLSQEntries = 278 ldstQueue.numFreeEntries(tid); 279 } 280 281 cpu->activateStage(O3CPU::IEWIdx); 282} 283 284template<class Impl> 285void 286DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 287{ 288 timeBuffer = tb_ptr; 289 290 // Setup wire to read information from time buffer, from commit. 291 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 292 293 // Setup wire to write information back to previous stages. 294 toRename = timeBuffer->getWire(0); 295 296 toFetch = timeBuffer->getWire(0); 297 298 // Instruction queue also needs main time buffer. 299 instQueue.setTimeBuffer(tb_ptr); 300} 301 302template<class Impl> 303void 304DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 305{ 306 renameQueue = rq_ptr; 307 308 // Setup wire to read information from rename queue. 309 fromRename = renameQueue->getWire(-renameToIEWDelay); 310} 311 312template<class Impl> 313void 314DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 315{ 316 iewQueue = iq_ptr; 317 318 // Setup wire to write instructions to commit. 319 toCommit = iewQueue->getWire(0); 320} 321 322template<class Impl> 323void 324DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 325{ 326 activeThreads = at_ptr; 327 328 ldstQueue.setActiveThreads(at_ptr); 329 instQueue.setActiveThreads(at_ptr); 330} 331 332template<class Impl> 333void 334DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 335{ 336 scoreboard = sb_ptr; 337} 338 339template <class Impl> 340bool 341DefaultIEW<Impl>::drain() 342{ 343 // IEW is ready to drain at any time. 344 cpu->signalDrained(); 345 return true; 346} 347 348template <class Impl> 349void 350DefaultIEW<Impl>::resume() 351{ 352} 353 354template <class Impl> 355void 356DefaultIEW<Impl>::switchOut() 357{ 358 // Clear any state. 359 switchedOut = true; 360 assert(insts[0].empty()); 361 assert(skidBuffer[0].empty()); 362 363 instQueue.switchOut(); 364 ldstQueue.switchOut(); 365 fuPool->switchOut(); 366 367 for (ThreadID tid = 0; tid < numThreads; tid++) { 368 while (!insts[tid].empty()) 369 insts[tid].pop(); 370 while (!skidBuffer[tid].empty()) 371 skidBuffer[tid].pop(); 372 } 373} 374 375template <class Impl> 376void 377DefaultIEW<Impl>::takeOverFrom() 378{ 379 // Reset all state. 380 _status = Active; 381 exeStatus = Running; 382 wbStatus = Idle; 383 switchedOut = false; 384 385 instQueue.takeOverFrom(); 386 ldstQueue.takeOverFrom(); 387 fuPool->takeOverFrom(); 388 389 initStage(); 390 cpu->activityThisCycle(); 391 392 for (ThreadID tid = 0; tid < numThreads; tid++) { 393 dispatchStatus[tid] = Running; 394 stalls[tid].commit = false; 395 fetchRedirect[tid] = false; 396 } 397 398 updateLSQNextCycle = false; 399 400 for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 401 issueToExecQueue.advance(); 402 } 403} 404 405template<class Impl> 406void 407DefaultIEW<Impl>::squash(ThreadID tid) 408{ 409 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 410 411 // Tell the IQ to start squashing. 412 instQueue.squash(tid); 413 414 // Tell the LDSTQ to start squashing. 415 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 416 updatedQueues = true; 417 418 // Clear the skid buffer in case it has any data in it. 419 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 420 tid, fromCommit->commitInfo[tid].doneSeqNum); 421 422 while (!skidBuffer[tid].empty()) { 423 if (skidBuffer[tid].front()->isLoad() || 424 skidBuffer[tid].front()->isStore() ) { 425 toRename->iewInfo[tid].dispatchedToLSQ++; 426 } 427 428 toRename->iewInfo[tid].dispatched++; 429 430 skidBuffer[tid].pop(); 431 } 432 433 emptyRenameInsts(tid); 434} 435 436template<class Impl> 437void 438DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 439{ 440 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 441 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 442 443 toCommit->squash[tid] = true; 444 toCommit->squashedSeqNum[tid] = inst->seqNum; 445 toCommit->mispredPC[tid] = inst->readPC(); 446 toCommit->branchMispredict[tid] = true; 447 448#if ISA_HAS_DELAY_SLOT 449 int instSize = sizeof(TheISA::MachInst); 450 toCommit->branchTaken[tid] = 451 !(inst->readNextPC() + instSize == inst->readNextNPC() && 452 (inst->readNextPC() == inst->readPC() + instSize || 453 inst->readNextPC() == inst->readPC() + 2 * instSize)); 454#else 455 toCommit->branchTaken[tid] = inst->readNextPC() != 456 (inst->readPC() + sizeof(TheISA::MachInst)); 457#endif 458 toCommit->nextPC[tid] = inst->readNextPC(); 459 toCommit->nextNPC[tid] = inst->readNextNPC(); 460 toCommit->nextMicroPC[tid] = inst->readNextMicroPC(); 461 462 toCommit->includeSquashInst[tid] = false; 463 464 wroteToTimeBuffer = true; 465} 466 467template<class Impl> 468void 469DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 470{ 471 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 472 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 473 474 toCommit->squash[tid] = true; 475 toCommit->squashedSeqNum[tid] = inst->seqNum; 476 toCommit->nextPC[tid] = inst->readNextPC(); 477 toCommit->nextNPC[tid] = inst->readNextNPC(); 478 toCommit->branchMispredict[tid] = false; 479 480 toCommit->includeSquashInst[tid] = false; 481 482 wroteToTimeBuffer = true; 483} 484 485template<class Impl> 486void 487DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 488{ 489 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 490 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 491 492 toCommit->squash[tid] = true; 493 toCommit->squashedSeqNum[tid] = inst->seqNum; 494 toCommit->nextPC[tid] = inst->readPC(); 495 toCommit->nextNPC[tid] = inst->readNextPC(); 496 toCommit->branchMispredict[tid] = false; 497 498 // Must include the broadcasted SN in the squash. 499 toCommit->includeSquashInst[tid] = true; 500 501 ldstQueue.setLoadBlockedHandled(tid); 502 503 wroteToTimeBuffer = true; 504} 505 506template<class Impl> 507void 508DefaultIEW<Impl>::block(ThreadID tid) 509{ 510 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 511 512 if (dispatchStatus[tid] != Blocked && 513 dispatchStatus[tid] != Unblocking) { 514 toRename->iewBlock[tid] = true; 515 wroteToTimeBuffer = true; 516 } 517 518 // Add the current inputs to the skid buffer so they can be 519 // reprocessed when this stage unblocks. 520 skidInsert(tid); 521 522 dispatchStatus[tid] = Blocked; 523} 524 525template<class Impl> 526void 527DefaultIEW<Impl>::unblock(ThreadID tid) 528{ 529 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 530 "buffer %u.\n",tid, tid); 531 532 // If the skid bufffer is empty, signal back to previous stages to unblock. 533 // Also switch status to running. 534 if (skidBuffer[tid].empty()) { 535 toRename->iewUnblock[tid] = true; 536 wroteToTimeBuffer = true; 537 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 538 dispatchStatus[tid] = Running; 539 } 540} 541 542template<class Impl> 543void 544DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 545{ 546 instQueue.wakeDependents(inst); 547} 548 549template<class Impl> 550void 551DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 552{ 553 instQueue.rescheduleMemInst(inst); 554} 555 556template<class Impl> 557void 558DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 559{ 560 instQueue.replayMemInst(inst); 561} 562 563template<class Impl> 564void 565DefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 566{ 567 // This function should not be called after writebackInsts in a 568 // single cycle. That will cause problems with an instruction 569 // being added to the queue to commit without being processed by 570 // writebackInsts prior to being sent to commit. 571 572 // First check the time slot that this instruction will write 573 // to. If there are free write ports at the time, then go ahead 574 // and write the instruction to that time. If there are not, 575 // keep looking back to see where's the first time there's a 576 // free slot. 577 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 578 ++wbNumInst; 579 if (wbNumInst == wbWidth) { 580 ++wbCycle; 581 wbNumInst = 0; 582 } 583 584 assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 585 } 586 587 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 588 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 589 // Add finished instruction to queue to commit. 590 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 591 (*iewQueue)[wbCycle].size++; 592} 593 594template <class Impl> 595unsigned 596DefaultIEW<Impl>::validInstsFromRename() 597{ 598 unsigned inst_count = 0; 599 600 for (int i=0; i<fromRename->size; i++) { 601 if (!fromRename->insts[i]->isSquashed()) 602 inst_count++; 603 } 604 605 return inst_count; 606} 607 608template<class Impl> 609void 610DefaultIEW<Impl>::skidInsert(ThreadID tid) 611{ 612 DynInstPtr inst = NULL; 613 614 while (!insts[tid].empty()) { 615 inst = insts[tid].front(); 616 617 insts[tid].pop(); 618 619 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 620 "dispatch skidBuffer %i\n",tid, inst->seqNum, 621 inst->readPC(),tid); 622 623 skidBuffer[tid].push(inst); 624 } 625 626 assert(skidBuffer[tid].size() <= skidBufferMax && 627 "Skidbuffer Exceeded Max Size"); 628} 629 630template<class Impl> 631int 632DefaultIEW<Impl>::skidCount() 633{ 634 int max=0; 635 636 list<ThreadID>::iterator threads = activeThreads->begin(); 637 list<ThreadID>::iterator end = activeThreads->end(); 638 639 while (threads != end) { 640 ThreadID tid = *threads++; 641 unsigned thread_count = skidBuffer[tid].size(); 642 if (max < thread_count) 643 max = thread_count; 644 } 645 646 return max; 647} 648 649template<class Impl> 650bool 651DefaultIEW<Impl>::skidsEmpty() 652{ 653 list<ThreadID>::iterator threads = activeThreads->begin(); 654 list<ThreadID>::iterator end = activeThreads->end(); 655 656 while (threads != end) { 657 ThreadID tid = *threads++; 658 659 if (!skidBuffer[tid].empty()) 660 return false; 661 } 662 663 return true; 664} 665 666template <class Impl> 667void 668DefaultIEW<Impl>::updateStatus() 669{ 670 bool any_unblocking = false; 671 672 list<ThreadID>::iterator threads = activeThreads->begin(); 673 list<ThreadID>::iterator end = activeThreads->end(); 674 675 while (threads != end) { 676 ThreadID tid = *threads++; 677 678 if (dispatchStatus[tid] == Unblocking) { 679 any_unblocking = true; 680 break; 681 } 682 } 683 684 // If there are no ready instructions waiting to be scheduled by the IQ, 685 // and there's no stores waiting to write back, and dispatch is not 686 // unblocking, then there is no internal activity for the IEW stage. 687 if (_status == Active && !instQueue.hasReadyInsts() && 688 !ldstQueue.willWB() && !any_unblocking) { 689 DPRINTF(IEW, "IEW switching to idle\n"); 690 691 deactivateStage(); 692 693 _status = Inactive; 694 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 695 ldstQueue.willWB() || 696 any_unblocking)) { 697 // Otherwise there is internal activity. Set to active. 698 DPRINTF(IEW, "IEW switching to active\n"); 699 700 activateStage(); 701 702 _status = Active; 703 } 704} 705 706template <class Impl> 707void 708DefaultIEW<Impl>::resetEntries() 709{ 710 instQueue.resetEntries(); 711 ldstQueue.resetEntries(); 712} 713 714template <class Impl> 715void 716DefaultIEW<Impl>::readStallSignals(ThreadID tid) 717{ 718 if (fromCommit->commitBlock[tid]) { 719 stalls[tid].commit = true; 720 } 721 722 if (fromCommit->commitUnblock[tid]) { 723 assert(stalls[tid].commit); 724 stalls[tid].commit = false; 725 } 726} 727 728template <class Impl> 729bool 730DefaultIEW<Impl>::checkStall(ThreadID tid) 731{ 732 bool ret_val(false); 733 734 if (stalls[tid].commit) { 735 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 736 ret_val = true; 737 } else if (instQueue.isFull(tid)) { 738 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 739 ret_val = true; 740 } else if (ldstQueue.isFull(tid)) { 741 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 742 743 if (ldstQueue.numLoads(tid) > 0 ) { 744 745 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 746 tid,ldstQueue.getLoadHeadSeqNum(tid)); 747 } 748 749 if (ldstQueue.numStores(tid) > 0) { 750 751 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 752 tid,ldstQueue.getStoreHeadSeqNum(tid)); 753 } 754 755 ret_val = true; 756 } else if (ldstQueue.isStalled(tid)) { 757 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 758 ret_val = true; 759 } 760 761 return ret_val; 762} 763 764template <class Impl> 765void 766DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 767{ 768 // Check if there's a squash signal, squash if there is 769 // Check stall signals, block if there is. 770 // If status was Blocked 771 // if so then go to unblocking 772 // If status was Squashing 773 // check if squashing is not high. Switch to running this cycle. 774 775 readStallSignals(tid); 776 777 if (fromCommit->commitInfo[tid].squash) { 778 squash(tid); 779 780 if (dispatchStatus[tid] == Blocked || 781 dispatchStatus[tid] == Unblocking) { 782 toRename->iewUnblock[tid] = true; 783 wroteToTimeBuffer = true; 784 } 785 786 dispatchStatus[tid] = Squashing; 787 788 fetchRedirect[tid] = false; 789 return; 790 } 791 792 if (fromCommit->commitInfo[tid].robSquashing) { 793 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 794 795 dispatchStatus[tid] = Squashing; 796 797 emptyRenameInsts(tid); 798 wroteToTimeBuffer = true; 799 return; 800 } 801 802 if (checkStall(tid)) { 803 block(tid); 804 dispatchStatus[tid] = Blocked; 805 return; 806 } 807 808 if (dispatchStatus[tid] == Blocked) { 809 // Status from previous cycle was blocked, but there are no more stall 810 // conditions. Switch over to unblocking. 811 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 812 tid); 813 814 dispatchStatus[tid] = Unblocking; 815 816 unblock(tid); 817 818 return; 819 } 820 821 if (dispatchStatus[tid] == Squashing) { 822 // Switch status to running if rename isn't being told to block or 823 // squash this cycle. 824 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 825 tid); 826 827 dispatchStatus[tid] = Running; 828 829 return; 830 } 831} 832 833template <class Impl> 834void 835DefaultIEW<Impl>::sortInsts() 836{ 837 int insts_from_rename = fromRename->size; 838#ifdef DEBUG 839 for (ThreadID tid = 0; tid < numThreads; tid++) 840 assert(insts[tid].empty()); 841#endif 842 for (int i = 0; i < insts_from_rename; ++i) { 843 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 844 } 845} 846 847template <class Impl> 848void 849DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 850{ 851 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 852 853 while (!insts[tid].empty()) { 854 855 if (insts[tid].front()->isLoad() || 856 insts[tid].front()->isStore() ) { 857 toRename->iewInfo[tid].dispatchedToLSQ++; 858 } 859 860 toRename->iewInfo[tid].dispatched++; 861 862 insts[tid].pop(); 863 } 864} 865 866template <class Impl> 867void 868DefaultIEW<Impl>::wakeCPU() 869{ 870 cpu->wakeCPU(); 871} 872 873template <class Impl> 874void 875DefaultIEW<Impl>::activityThisCycle() 876{ 877 DPRINTF(Activity, "Activity this cycle.\n"); 878 cpu->activityThisCycle(); 879} 880 881template <class Impl> 882inline void 883DefaultIEW<Impl>::activateStage() 884{ 885 DPRINTF(Activity, "Activating stage.\n"); 886 cpu->activateStage(O3CPU::IEWIdx); 887} 888 889template <class Impl> 890inline void 891DefaultIEW<Impl>::deactivateStage() 892{ 893 DPRINTF(Activity, "Deactivating stage.\n"); 894 cpu->deactivateStage(O3CPU::IEWIdx); 895} 896 897template<class Impl> 898void 899DefaultIEW<Impl>::dispatch(ThreadID tid) 900{ 901 // If status is Running or idle, 902 // call dispatchInsts() 903 // If status is Unblocking, 904 // buffer any instructions coming from rename 905 // continue trying to empty skid buffer 906 // check if stall conditions have passed 907 908 if (dispatchStatus[tid] == Blocked) { 909 ++iewBlockCycles; 910 911 } else if (dispatchStatus[tid] == Squashing) { 912 ++iewSquashCycles; 913 } 914 915 // Dispatch should try to dispatch as many instructions as its bandwidth 916 // will allow, as long as it is not currently blocked. 917 if (dispatchStatus[tid] == Running || 918 dispatchStatus[tid] == Idle) { 919 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 920 "dispatch.\n", tid); 921 922 dispatchInsts(tid); 923 } else if (dispatchStatus[tid] == Unblocking) { 924 // Make sure that the skid buffer has something in it if the 925 // status is unblocking. 926 assert(!skidsEmpty()); 927 928 // If the status was unblocking, then instructions from the skid 929 // buffer were used. Remove those instructions and handle 930 // the rest of unblocking. 931 dispatchInsts(tid); 932 933 ++iewUnblockCycles; 934 935 if (validInstsFromRename()) { 936 // Add the current inputs to the skid buffer so they can be 937 // reprocessed when this stage unblocks. 938 skidInsert(tid); 939 } 940 941 unblock(tid); 942 } 943} 944 945template <class Impl> 946void 947DefaultIEW<Impl>::dispatchInsts(ThreadID tid) 948{ 949 // Obtain instructions from skid buffer if unblocking, or queue from rename 950 // otherwise. 951 std::queue<DynInstPtr> &insts_to_dispatch = 952 dispatchStatus[tid] == Unblocking ? 953 skidBuffer[tid] : insts[tid]; 954 955 int insts_to_add = insts_to_dispatch.size(); 956 957 DynInstPtr inst; 958 bool add_to_iq = false; 959 int dis_num_inst = 0; 960 961 // Loop through the instructions, putting them in the instruction 962 // queue. 963 for ( ; dis_num_inst < insts_to_add && 964 dis_num_inst < dispatchWidth; 965 ++dis_num_inst) 966 { 967 inst = insts_to_dispatch.front(); 968 969 if (dispatchStatus[tid] == Unblocking) { 970 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 971 "buffer\n", tid); 972 } 973 974 // Make sure there's a valid instruction there. 975 assert(inst); 976 977 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 978 "IQ.\n", 979 tid, inst->readPC(), inst->seqNum, inst->threadNumber); 980 981 // Be sure to mark these instructions as ready so that the 982 // commit stage can go ahead and execute them, and mark 983 // them as issued so the IQ doesn't reprocess them. 984 985 // Check for squashed instructions. 986 if (inst->isSquashed()) { 987 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 988 "not adding to IQ.\n", tid); 989 990 ++iewDispSquashedInsts; 991 992 insts_to_dispatch.pop(); 993 994 //Tell Rename That An Instruction has been processed 995 if (inst->isLoad() || inst->isStore()) { 996 toRename->iewInfo[tid].dispatchedToLSQ++; 997 } 998 toRename->iewInfo[tid].dispatched++; 999 1000 continue; 1001 } 1002 1003 // Check for full conditions. 1004 if (instQueue.isFull(tid)) { 1005 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 1006 1007 // Call function to start blocking. 1008 block(tid); 1009 1010 // Set unblock to false. Special case where we are using 1011 // skidbuffer (unblocking) instructions but then we still 1012 // get full in the IQ. 1013 toRename->iewUnblock[tid] = false; 1014 1015 ++iewIQFullEvents; 1016 break; 1017 } else if (ldstQueue.isFull(tid)) { 1018 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 1019 1020 // Call function to start blocking. 1021 block(tid); 1022 1023 // Set unblock to false. Special case where we are using 1024 // skidbuffer (unblocking) instructions but then we still 1025 // get full in the IQ. 1026 toRename->iewUnblock[tid] = false; 1027 1028 ++iewLSQFullEvents; 1029 break; 1030 } 1031 1032 // Otherwise issue the instruction just fine. 1033 if (inst->isLoad()) { 1034 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1035 "encountered, adding to LSQ.\n", tid); 1036 1037 // Reserve a spot in the load store queue for this 1038 // memory access. 1039 ldstQueue.insertLoad(inst); 1040 1041 ++iewDispLoadInsts; 1042 1043 add_to_iq = true; 1044 1045 toRename->iewInfo[tid].dispatchedToLSQ++; 1046 } else if (inst->isStore()) { 1047 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1048 "encountered, adding to LSQ.\n", tid); 1049 1050 ldstQueue.insertStore(inst); 1051 1052 ++iewDispStoreInsts; 1053 1054 if (inst->isStoreConditional()) { 1055 // Store conditionals need to be set as "canCommit()" 1056 // so that commit can process them when they reach the 1057 // head of commit. 1058 // @todo: This is somewhat specific to Alpha. 1059 inst->setCanCommit(); 1060 instQueue.insertNonSpec(inst); 1061 add_to_iq = false; 1062 1063 ++iewDispNonSpecInsts; 1064 } else { 1065 add_to_iq = true; 1066 } 1067 1068 toRename->iewInfo[tid].dispatchedToLSQ++; 1069 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1070 // Same as non-speculative stores. 1071 inst->setCanCommit(); 1072 instQueue.insertBarrier(inst); 1073 add_to_iq = false; 1074 } else if (inst->isNop()) { 1075 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1076 "skipping.\n", tid); 1077 1078 inst->setIssued(); 1079 inst->setExecuted(); 1080 inst->setCanCommit(); 1081 1082 instQueue.recordProducer(inst); 1083 1084 iewExecutedNop[tid]++; 1085 1086 add_to_iq = false; 1087 } else if (inst->isExecuted()) { 1088 assert(0 && "Instruction shouldn't be executed.\n"); 1089 DPRINTF(IEW, "Issue: Executed branch encountered, " 1090 "skipping.\n"); 1091 1092 inst->setIssued(); 1093 inst->setCanCommit(); 1094 1095 instQueue.recordProducer(inst); 1096 1097 add_to_iq = false; 1098 } else { 1099 add_to_iq = true; 1100 } 1101 if (inst->isNonSpeculative()) { 1102 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1103 "encountered, skipping.\n", tid); 1104 1105 // Same as non-speculative stores. 1106 inst->setCanCommit(); 1107 1108 // Specifically insert it as nonspeculative. 1109 instQueue.insertNonSpec(inst); 1110 1111 ++iewDispNonSpecInsts; 1112 1113 add_to_iq = false; 1114 } 1115 1116 // If the instruction queue is not full, then add the 1117 // instruction. 1118 if (add_to_iq) { 1119 instQueue.insert(inst); 1120 } 1121 1122 insts_to_dispatch.pop(); 1123 1124 toRename->iewInfo[tid].dispatched++; 1125 1126 ++iewDispatchedInsts; 1127 } 1128 1129 if (!insts_to_dispatch.empty()) { 1130 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 1131 block(tid); 1132 toRename->iewUnblock[tid] = false; 1133 } 1134 1135 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1136 dispatchStatus[tid] = Running; 1137 1138 updatedQueues = true; 1139 } 1140 1141 dis_num_inst = 0; 1142} 1143 1144template <class Impl> 1145void 1146DefaultIEW<Impl>::printAvailableInsts() 1147{ 1148 int inst = 0; 1149 1150 std::cout << "Available Instructions: "; 1151 1152 while (fromIssue->insts[inst]) { 1153 1154 if (inst%3==0) std::cout << "\n\t"; 1155 1156 std::cout << "PC: " << fromIssue->insts[inst]->readPC() 1157 << " TN: " << fromIssue->insts[inst]->threadNumber 1158 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1159 1160 inst++; 1161 1162 } 1163 1164 std::cout << "\n"; 1165} 1166 1167template <class Impl> 1168void 1169DefaultIEW<Impl>::executeInsts() 1170{ 1171 wbNumInst = 0; 1172 wbCycle = 0; 1173 1174 list<ThreadID>::iterator threads = activeThreads->begin(); 1175 list<ThreadID>::iterator end = activeThreads->end(); 1176 1177 while (threads != end) { 1178 ThreadID tid = *threads++; 1179 fetchRedirect[tid] = false; 1180 } 1181 1182 // Uncomment this if you want to see all available instructions. 1183// printAvailableInsts(); 1184 1185 // Execute/writeback any instructions that are available. 1186 int insts_to_execute = fromIssue->size; 1187 int inst_num = 0; 1188 for (; inst_num < insts_to_execute; 1189 ++inst_num) { 1190 1191 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1192 1193 DynInstPtr inst = instQueue.getInstToExecute(); 1194 1195 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 1196 inst->readPC(), inst->threadNumber,inst->seqNum); 1197 1198 // Check if the instruction is squashed; if so then skip it 1199 if (inst->isSquashed()) { 1200 DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 1201 1202 // Consider this instruction executed so that commit can go 1203 // ahead and retire the instruction. 1204 inst->setExecuted(); 1205 1206 // Not sure if I should set this here or just let commit try to 1207 // commit any squashed instructions. I like the latter a bit more. 1208 inst->setCanCommit(); 1209 1210 ++iewExecSquashedInsts; 1211 1212 decrWb(inst->seqNum); 1213 continue; 1214 } 1215 1216 Fault fault = NoFault; 1217 1218 // Execute instruction. 1219 // Note that if the instruction faults, it will be handled 1220 // at the commit stage. 1221 if (inst->isMemRef() && 1222 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 1223 DPRINTF(IEW, "Execute: Calculating address for memory " 1224 "reference.\n"); 1225 1226 // Tell the LDSTQ to execute this instruction (if it is a load). 1227 if (inst->isLoad()) { 1228 // Loads will mark themselves as executed, and their writeback 1229 // event adds the instruction to the queue to commit 1230 fault = ldstQueue.executeLoad(inst); 1231 } else if (inst->isStore()) { 1232 fault = ldstQueue.executeStore(inst); 1233 1234 // If the store had a fault then it may not have a mem req 1235 if (!inst->isStoreConditional() && fault == NoFault) { 1236 inst->setExecuted(); 1237 1238 instToCommit(inst); 1239 } else if (fault != NoFault) { 1240 // If the instruction faulted, then we need to send it along to commit 1241 // without the instruction completing. 1242 DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n", 1243 fault->name(), inst->seqNum); 1244 1245 // Send this instruction to commit, also make sure iew stage 1246 // realizes there is activity. 1247 inst->setExecuted(); 1248 1249 instToCommit(inst); 1250 activityThisCycle(); 1251 } 1252 1253 // Store conditionals will mark themselves as 1254 // executed, and their writeback event will add the 1255 // instruction to the queue to commit. 1256 } else { 1257 panic("Unexpected memory type!\n"); 1258 } 1259 1260 } else { 1261 inst->execute(); 1262 1263 inst->setExecuted(); 1264 1265 instToCommit(inst); 1266 } 1267 1268 updateExeInstStats(inst); 1269 1270 // Check if branch prediction was correct, if not then we need 1271 // to tell commit to squash in flight instructions. Only 1272 // handle this if there hasn't already been something that 1273 // redirects fetch in this group of instructions. 1274 1275 // This probably needs to prioritize the redirects if a different 1276 // scheduler is used. Currently the scheduler schedules the oldest 1277 // instruction first, so the branch resolution order will be correct. 1278 ThreadID tid = inst->threadNumber; 1279 1280 if (!fetchRedirect[tid] || 1281 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1282 1283 if (inst->mispredicted()) { 1284 fetchRedirect[tid] = true; 1285 1286 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1287 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1288 inst->readPredPC(), inst->readPredNPC()); 1289 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1290 " NPC: %#x.\n", inst->readNextPC(), 1291 inst->readNextNPC()); 1292 // If incorrect, then signal the ROB that it must be squashed. 1293 squashDueToBranch(inst, tid); 1294 1295 if (inst->readPredTaken()) { 1296 predictedTakenIncorrect++; 1297 } else { 1298 predictedNotTakenIncorrect++; 1299 } 1300 } else if (ldstQueue.violation(tid)) { 1301 assert(inst->isMemRef()); 1302 // If there was an ordering violation, then get the 1303 // DynInst that caused the violation. Note that this 1304 // clears the violation signal. 1305 DynInstPtr violator; 1306 violator = ldstQueue.getMemDepViolator(tid); 1307 1308 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1309 "%#x, inst PC: %#x. Addr is: %#x.\n", 1310 violator->readPC(), inst->readPC(), inst->physEffAddr); 1311 1312 // Ensure the violating instruction is older than 1313 // current squash 1314/* if (fetchRedirect[tid] && 1315 violator->seqNum >= toCommit->squashedSeqNum[tid] + 1) 1316 continue; 1317*/ 1318 fetchRedirect[tid] = true; 1319 1320 // Tell the instruction queue that a violation has occured. 1321 instQueue.violation(inst, violator); 1322 1323 // Squash. 1324 squashDueToMemOrder(inst,tid); 1325 1326 ++memOrderViolationEvents; 1327 } else if (ldstQueue.loadBlocked(tid) && 1328 !ldstQueue.isLoadBlockedHandled(tid)) { 1329 fetchRedirect[tid] = true; 1330 1331 DPRINTF(IEW, "Load operation couldn't execute because the " 1332 "memory system is blocked. PC: %#x [sn:%lli]\n", 1333 inst->readPC(), inst->seqNum); 1334 1335 squashDueToMemBlocked(inst, tid); 1336 } 1337 } else { 1338 // Reset any state associated with redirects that will not 1339 // be used. 1340 if (ldstQueue.violation(tid)) { 1341 assert(inst->isMemRef()); 1342 1343 DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 1344 1345 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1346 "%#x, inst PC: %#x. Addr is: %#x.\n", 1347 violator->readPC(), inst->readPC(), inst->physEffAddr); 1348 DPRINTF(IEW, "Violation will not be handled because " 1349 "already squashing\n"); 1350 1351 ++memOrderViolationEvents; 1352 } 1353 if (ldstQueue.loadBlocked(tid) && 1354 !ldstQueue.isLoadBlockedHandled(tid)) { 1355 DPRINTF(IEW, "Load operation couldn't execute because the " 1356 "memory system is blocked. PC: %#x [sn:%lli]\n", 1357 inst->readPC(), inst->seqNum); 1358 DPRINTF(IEW, "Blocked load will not be handled because " 1359 "already squashing\n"); 1360 1361 ldstQueue.setLoadBlockedHandled(tid); 1362 } 1363 1364 } 1365 } 1366 1367 // Update and record activity if we processed any instructions. 1368 if (inst_num) { 1369 if (exeStatus == Idle) { 1370 exeStatus = Running; 1371 } 1372 1373 updatedQueues = true; 1374 1375 cpu->activityThisCycle(); 1376 } 1377 1378 // Need to reset this in case a writeback event needs to write into the 1379 // iew queue. That way the writeback event will write into the correct 1380 // spot in the queue. 1381 wbNumInst = 0; 1382} 1383 1384template <class Impl> 1385void 1386DefaultIEW<Impl>::writebackInsts() 1387{ 1388 // Loop through the head of the time buffer and wake any 1389 // dependents. These instructions are about to write back. Also 1390 // mark scoreboard that this instruction is finally complete. 1391 // Either have IEW have direct access to scoreboard, or have this 1392 // as part of backwards communication. 1393 for (int inst_num = 0; inst_num < wbWidth && 1394 toCommit->insts[inst_num]; inst_num++) { 1395 DynInstPtr inst = toCommit->insts[inst_num]; 1396 ThreadID tid = inst->threadNumber; 1397 1398 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 1399 inst->seqNum, inst->readPC()); 1400 1401 iewInstsToCommit[tid]++; 1402 1403 // Some instructions will be sent to commit without having 1404 // executed because they need commit to handle them. 1405 // E.g. Uncached loads have not actually executed when they 1406 // are first sent to commit. Instead commit must tell the LSQ 1407 // when it's ready to execute the uncached load. 1408 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1409 int dependents = instQueue.wakeDependents(inst); 1410 1411 for (int i = 0; i < inst->numDestRegs(); i++) { 1412 //mark as Ready 1413 DPRINTF(IEW,"Setting Destination Register %i\n", 1414 inst->renamedDestRegIdx(i)); 1415 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1416 } 1417 1418 if (dependents) { 1419 producerInst[tid]++; 1420 consumerInst[tid]+= dependents; 1421 } 1422 writebackCount[tid]++; 1423 } 1424 1425 decrWb(inst->seqNum); 1426 } 1427} 1428 1429template<class Impl> 1430void 1431DefaultIEW<Impl>::tick() 1432{ 1433 wbNumInst = 0; 1434 wbCycle = 0; 1435 1436 wroteToTimeBuffer = false; 1437 updatedQueues = false; 1438 1439 sortInsts(); 1440 1441 // Free function units marked as being freed this cycle. 1442 fuPool->processFreeUnits(); 1443 1444 list<ThreadID>::iterator threads = activeThreads->begin(); 1445 list<ThreadID>::iterator end = activeThreads->end(); 1446 1447 // Check stall and squash signals, dispatch any instructions. 1448 while (threads != end) { 1449 ThreadID tid = *threads++; 1450 1451 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1452 1453 checkSignalsAndUpdate(tid); 1454 dispatch(tid); 1455 } 1456 1457 if (exeStatus != Squashing) { 1458 executeInsts(); 1459 1460 writebackInsts(); 1461 1462 // Have the instruction queue try to schedule any ready instructions. 1463 // (In actuality, this scheduling is for instructions that will 1464 // be executed next cycle.) 1465 instQueue.scheduleReadyInsts(); 1466 1467 // Also should advance its own time buffers if the stage ran. 1468 // Not the best place for it, but this works (hopefully). 1469 issueToExecQueue.advance(); 1470 } 1471 1472 bool broadcast_free_entries = false; 1473 1474 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1475 exeStatus = Idle; 1476 updateLSQNextCycle = false; 1477 1478 broadcast_free_entries = true; 1479 } 1480 1481 // Writeback any stores using any leftover bandwidth. 1482 ldstQueue.writebackStores(); 1483 1484 // Check the committed load/store signals to see if there's a load 1485 // or store to commit. Also check if it's being told to execute a 1486 // nonspeculative instruction. 1487 // This is pretty inefficient... 1488 1489 threads = activeThreads->begin(); 1490 while (threads != end) { 1491 ThreadID tid = (*threads++); 1492 1493 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1494 1495 // Update structures based on instructions committed. 1496 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1497 !fromCommit->commitInfo[tid].squash && 1498 !fromCommit->commitInfo[tid].robSquashing) { 1499 1500 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1501 1502 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1503 1504 updateLSQNextCycle = true; 1505 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1506 } 1507 1508 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1509 1510 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1511 if (fromCommit->commitInfo[tid].uncached) { 1512 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1513 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 1514 } else { 1515 instQueue.scheduleNonSpec( 1516 fromCommit->commitInfo[tid].nonSpecSeqNum); 1517 } 1518 } 1519 1520 if (broadcast_free_entries) { 1521 toFetch->iewInfo[tid].iqCount = 1522 instQueue.getCount(tid); 1523 toFetch->iewInfo[tid].ldstqCount = 1524 ldstQueue.getCount(tid); 1525 1526 toRename->iewInfo[tid].usedIQ = true; 1527 toRename->iewInfo[tid].freeIQEntries = 1528 instQueue.numFreeEntries(); 1529 toRename->iewInfo[tid].usedLSQ = true; 1530 toRename->iewInfo[tid].freeLSQEntries = 1531 ldstQueue.numFreeEntries(tid); 1532 1533 wroteToTimeBuffer = true; 1534 } 1535 1536 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1537 tid, toRename->iewInfo[tid].dispatched); 1538 } 1539 1540 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1541 "LSQ has %i free entries.\n", 1542 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1543 ldstQueue.numFreeEntries()); 1544 1545 updateStatus(); 1546 1547 if (wroteToTimeBuffer) { 1548 DPRINTF(Activity, "Activity this cycle.\n"); 1549 cpu->activityThisCycle(); 1550 } 1551} 1552 1553template <class Impl> 1554void 1555DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1556{ 1557 ThreadID tid = inst->threadNumber; 1558 1559 // 1560 // Pick off the software prefetches 1561 // 1562#ifdef TARGET_ALPHA 1563 if (inst->isDataPrefetch()) 1564 iewExecutedSwp[tid]++; 1565 else 1566 iewIewExecutedcutedInsts++; 1567#else 1568 iewExecutedInsts++; 1569#endif 1570 1571 // 1572 // Control operations 1573 // 1574 if (inst->isControl()) 1575 iewExecutedBranches[tid]++; 1576 1577 // 1578 // Memory operations 1579 // 1580 if (inst->isMemRef()) { 1581 iewExecutedRefs[tid]++; 1582 1583 if (inst->isLoad()) { 1584 iewExecLoadInsts[tid]++; 1585 } 1586 } 1587} 1588