iew.hh revision 1060 
1//Todo: Update with statuses.  Create constructor.  Fix up time buffer stuff.
2//Will also need a signal heading back at least one stage to rename to say
3//how many empty skid buffer entries there are.  Perhaps further back even.
4//Need to handle delaying writes to the writeback bus if it's full at the
5//given time.  Squash properly.  Load store queue.
6
7#ifndef __SIMPLE_IEW_HH__
8#define __SIMPLE_IEW_HH__
9
10// To include: time buffer, structs, queue,
11#include <queue>
12
13#include "base/timebuf.hh"
14#include "cpu/beta_cpu/comm.hh"
15
16//Can IEW even stall?  Space should be available/allocated already...maybe
17//if there's not enough write ports on the ROB or waiting for CDB
18//arbitration.
19template<class Impl, class IQ>
20class SimpleIEW
21{
22  private:
23    //Typedefs from Impl
24    typedef typename Impl::ISA ISA;
25    typedef typename Impl::DynInst DynInst;
26    typedef typename Impl::FullCPU FullCPU;
27    typedef typename Impl::Params Params;
28
29    typedef typename Impl::CPUPol::RenameMap RenameMap;
30
31    typedef typename Impl::TimeStruct TimeStruct;
32    typedef typename Impl::IEWStruct IEWStruct;
33    typedef typename Impl::RenameStruct RenameStruct;
34    typedef typename Impl::IssueStruct IssueStruct;
35
36  public:
37    enum Status {
38        Running,
39        Blocked,
40        Idle,
41        Squashing,
42        Unblocking
43    };
44
45  private:
46    Status _status;
47    Status _issueStatus;
48    Status _exeStatus;
49    Status _wbStatus;
50
51  public:
52    void squash();
53
54    void squash(DynInst *inst);
55
56    void block();
57
58    inline void unblock();
59
60  public:
61    SimpleIEW(Params &params);
62
63    void setCPU(FullCPU *cpu_ptr);
64
65    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
66
67    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
68
69    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
70
71    void setRenameMap(RenameMap *rm_ptr);
72
73    void wakeDependents(DynInst *inst);
74
75    void tick();
76
77    void iew();
78
79  private:
80    //Interfaces to objects inside and outside of IEW.
81    /** Time buffer interface. */
82    TimeBuffer<TimeStruct> *timeBuffer;
83
84    /** Wire to get commit's output from backwards time buffer. */
85    typename TimeBuffer<TimeStruct>::wire fromCommit;
86
87    /** Wire to write information heading to previous stages. */
88    typename TimeBuffer<TimeStruct>::wire toRename;
89
90    /** Rename instruction queue interface. */
91    TimeBuffer<RenameStruct> *renameQueue;
92
93    /** Wire to get rename's output from rename queue. */
94    typename TimeBuffer<RenameStruct>::wire fromRename;
95
96    /** Issue stage queue. */
97    TimeBuffer<IssueStruct> issueToExecQueue;
98
99    /** Wire to read information from the issue stage time queue. */
100    typename TimeBuffer<IssueStruct>::wire fromIssue;
101
102    /**
103     * IEW stage time buffer.  Holds ROB indices of instructions that
104     * can be marked as completed.
105     */
106    TimeBuffer<IEWStruct> *iewQueue;
107
108    /** Wire to write infromation heading to commit. */
109    typename TimeBuffer<IEWStruct>::wire toCommit;
110
111    //Will need internal queue to hold onto instructions coming from
112    //the rename stage in case of a stall.
113    /** Skid buffer between rename and IEW. */
114    queue<RenameStruct> skidBuffer;
115
116    /** Instruction queue. */
117    IQ instQueue;
118
119    /** Pointer to rename map.  Might not want this stage to directly
120     *  access this though...
121     */
122    RenameMap *renameMap;
123
124    /** CPU interface. */
125    FullCPU *cpu;
126
127  private:
128    /** Commit to IEW delay, in ticks. */
129    unsigned commitToIEWDelay;
130
131    /** Rename to IEW delay, in ticks. */
132    unsigned renameToIEWDelay;
133
134    /**
135     * Issue to execute delay, in ticks.  What this actually represents is
136     * the amount of time it takes for an instruction to wake up, be
137     * scheduled, and sent to a FU for execution.
138     */
139    unsigned issueToExecuteDelay;
140
141    /** Width of issue's read path, in instructions.  The read path is both
142     *  the skid buffer and the rename instruction queue.
143     *  Note to self: is this really different than issueWidth?
144     */
145    unsigned issueReadWidth;
146
147    /** Width of issue, in instructions. */
148    unsigned issueWidth;
149
150    /** Width of execute, in instructions.  Might make more sense to break
151     *  down into FP vs int.
152     */
153    unsigned executeWidth;
154
155    /** Number of cycles stage has been squashing.  Used so that the stage
156     *  knows when it can start unblocking, which is when the previous stage
157     *  has received the stall signal and clears up its outputs.
158     */
159    unsigned cyclesSquashing;
160
161    //Will implement later
162    //Load queue interface (probably one and the same)
163    //Store queue interface
164};
165
166#endif
167