iew.hh revision 1060
17322Sgblack@eecs.umich.edu//Todo: Update with statuses. Create constructor. Fix up time buffer stuff. 27322Sgblack@eecs.umich.edu//Will also need a signal heading back at least one stage to rename to say 37322Sgblack@eecs.umich.edu//how many empty skid buffer entries there are. Perhaps further back even. 47322Sgblack@eecs.umich.edu//Need to handle delaying writes to the writeback bus if it's full at the 57322Sgblack@eecs.umich.edu//given time. Squash properly. Load store queue. 67322Sgblack@eecs.umich.edu 77322Sgblack@eecs.umich.edu#ifndef __SIMPLE_IEW_HH__ 87322Sgblack@eecs.umich.edu#define __SIMPLE_IEW_HH__ 97322Sgblack@eecs.umich.edu 107322Sgblack@eecs.umich.edu// To include: time buffer, structs, queue, 117322Sgblack@eecs.umich.edu#include <queue> 127322Sgblack@eecs.umich.edu 137322Sgblack@eecs.umich.edu#include "base/timebuf.hh" 147322Sgblack@eecs.umich.edu#include "cpu/beta_cpu/comm.hh" 157322Sgblack@eecs.umich.edu 167322Sgblack@eecs.umich.edu//Can IEW even stall? Space should be available/allocated already...maybe 177322Sgblack@eecs.umich.edu//if there's not enough write ports on the ROB or waiting for CDB 187322Sgblack@eecs.umich.edu//arbitration. 197322Sgblack@eecs.umich.edutemplate<class Impl, class IQ> 207322Sgblack@eecs.umich.educlass SimpleIEW 217322Sgblack@eecs.umich.edu{ 227322Sgblack@eecs.umich.edu private: 237322Sgblack@eecs.umich.edu //Typedefs from Impl 247322Sgblack@eecs.umich.edu typedef typename Impl::ISA ISA; 257322Sgblack@eecs.umich.edu typedef typename Impl::DynInst DynInst; 267322Sgblack@eecs.umich.edu typedef typename Impl::FullCPU FullCPU; 277322Sgblack@eecs.umich.edu typedef typename Impl::Params Params; 287322Sgblack@eecs.umich.edu 297322Sgblack@eecs.umich.edu typedef typename Impl::CPUPol::RenameMap RenameMap; 307322Sgblack@eecs.umich.edu 317322Sgblack@eecs.umich.edu typedef typename Impl::TimeStruct TimeStruct; 327322Sgblack@eecs.umich.edu typedef typename Impl::IEWStruct IEWStruct; 337322Sgblack@eecs.umich.edu typedef typename Impl::RenameStruct RenameStruct; 347322Sgblack@eecs.umich.edu typedef typename Impl::IssueStruct IssueStruct; 357322Sgblack@eecs.umich.edu 367322Sgblack@eecs.umich.edu public: 377322Sgblack@eecs.umich.edu enum Status { 387322Sgblack@eecs.umich.edu Running, 397322Sgblack@eecs.umich.edu Blocked, 407376Sgblack@eecs.umich.edu Idle, 417376Sgblack@eecs.umich.edu Squashing, 427376Sgblack@eecs.umich.edu Unblocking 437376Sgblack@eecs.umich.edu }; 447376Sgblack@eecs.umich.edu 457376Sgblack@eecs.umich.edu private: 467376Sgblack@eecs.umich.edu Status _status; 477376Sgblack@eecs.umich.edu Status _issueStatus; 487376Sgblack@eecs.umich.edu Status _exeStatus; 497376Sgblack@eecs.umich.edu Status _wbStatus; 507376Sgblack@eecs.umich.edu 517376Sgblack@eecs.umich.edu public: 527376Sgblack@eecs.umich.edu void squash(); 537376Sgblack@eecs.umich.edu 547376Sgblack@eecs.umich.edu void squash(DynInst *inst); 557376Sgblack@eecs.umich.edu 567376Sgblack@eecs.umich.edu void block(); 577376Sgblack@eecs.umich.edu 587376Sgblack@eecs.umich.edu inline void unblock(); 597376Sgblack@eecs.umich.edu 607376Sgblack@eecs.umich.edu public: 617376Sgblack@eecs.umich.edu SimpleIEW(Params ¶ms); 627376Sgblack@eecs.umich.edu 637376Sgblack@eecs.umich.edu void setCPU(FullCPU *cpu_ptr); 647376Sgblack@eecs.umich.edu 657376Sgblack@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edu void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 687376Sgblack@eecs.umich.edu 697376Sgblack@eecs.umich.edu void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 707376Sgblack@eecs.umich.edu 717376Sgblack@eecs.umich.edu void setRenameMap(RenameMap *rm_ptr); 727376Sgblack@eecs.umich.edu 737376Sgblack@eecs.umich.edu void wakeDependents(DynInst *inst); 747376Sgblack@eecs.umich.edu 757376Sgblack@eecs.umich.edu void tick(); 767376Sgblack@eecs.umich.edu 777376Sgblack@eecs.umich.edu void iew(); 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edu private: 807376Sgblack@eecs.umich.edu //Interfaces to objects inside and outside of IEW. 817376Sgblack@eecs.umich.edu /** Time buffer interface. */ 827376Sgblack@eecs.umich.edu TimeBuffer<TimeStruct> *timeBuffer; 837376Sgblack@eecs.umich.edu 847376Sgblack@eecs.umich.edu /** Wire to get commit's output from backwards time buffer. */ 857376Sgblack@eecs.umich.edu typename TimeBuffer<TimeStruct>::wire fromCommit; 867376Sgblack@eecs.umich.edu 877376Sgblack@eecs.umich.edu /** Wire to write information heading to previous stages. */ 887376Sgblack@eecs.umich.edu typename TimeBuffer<TimeStruct>::wire toRename; 897376Sgblack@eecs.umich.edu 907376Sgblack@eecs.umich.edu /** Rename instruction queue interface. */ 917376Sgblack@eecs.umich.edu TimeBuffer<RenameStruct> *renameQueue; 927376Sgblack@eecs.umich.edu 937376Sgblack@eecs.umich.edu /** Wire to get rename's output from rename queue. */ 947376Sgblack@eecs.umich.edu typename TimeBuffer<RenameStruct>::wire fromRename; 957376Sgblack@eecs.umich.edu 967376Sgblack@eecs.umich.edu /** Issue stage queue. */ 977376Sgblack@eecs.umich.edu TimeBuffer<IssueStruct> issueToExecQueue; 987376Sgblack@eecs.umich.edu 997376Sgblack@eecs.umich.edu /** Wire to read information from the issue stage time queue. */ 1007376Sgblack@eecs.umich.edu typename TimeBuffer<IssueStruct>::wire fromIssue; 1017376Sgblack@eecs.umich.edu 1027376Sgblack@eecs.umich.edu /** 1037376Sgblack@eecs.umich.edu * IEW stage time buffer. Holds ROB indices of instructions that 1047376Sgblack@eecs.umich.edu * can be marked as completed. 1057376Sgblack@eecs.umich.edu */ 1067376Sgblack@eecs.umich.edu TimeBuffer<IEWStruct> *iewQueue; 1077376Sgblack@eecs.umich.edu 1087376Sgblack@eecs.umich.edu /** Wire to write infromation heading to commit. */ 1097376Sgblack@eecs.umich.edu typename TimeBuffer<IEWStruct>::wire toCommit; 1107376Sgblack@eecs.umich.edu 1117376Sgblack@eecs.umich.edu //Will need internal queue to hold onto instructions coming from 1127376Sgblack@eecs.umich.edu //the rename stage in case of a stall. 1137376Sgblack@eecs.umich.edu /** Skid buffer between rename and IEW. */ 1147376Sgblack@eecs.umich.edu queue<RenameStruct> skidBuffer; 1157376Sgblack@eecs.umich.edu 1167376Sgblack@eecs.umich.edu /** Instruction queue. */ 1177376Sgblack@eecs.umich.edu IQ instQueue; 1187376Sgblack@eecs.umich.edu 1197376Sgblack@eecs.umich.edu /** Pointer to rename map. Might not want this stage to directly 1207376Sgblack@eecs.umich.edu * access this though... 1217376Sgblack@eecs.umich.edu */ 1227376Sgblack@eecs.umich.edu RenameMap *renameMap; 1237376Sgblack@eecs.umich.edu 1247376Sgblack@eecs.umich.edu /** CPU interface. */ 1257376Sgblack@eecs.umich.edu FullCPU *cpu; 1267376Sgblack@eecs.umich.edu 1277376Sgblack@eecs.umich.edu private: 1287376Sgblack@eecs.umich.edu /** Commit to IEW delay, in ticks. */ 1297376Sgblack@eecs.umich.edu unsigned commitToIEWDelay; 1307376Sgblack@eecs.umich.edu 1317376Sgblack@eecs.umich.edu /** Rename to IEW delay, in ticks. */ 1327376Sgblack@eecs.umich.edu unsigned renameToIEWDelay; 1337376Sgblack@eecs.umich.edu 1347376Sgblack@eecs.umich.edu /** 1357376Sgblack@eecs.umich.edu * Issue to execute delay, in ticks. What this actually represents is 1367376Sgblack@eecs.umich.edu * the amount of time it takes for an instruction to wake up, be 1377376Sgblack@eecs.umich.edu * scheduled, and sent to a FU for execution. 1387376Sgblack@eecs.umich.edu */ 1397376Sgblack@eecs.umich.edu unsigned issueToExecuteDelay; 1407376Sgblack@eecs.umich.edu 1417376Sgblack@eecs.umich.edu /** Width of issue's read path, in instructions. The read path is both 1427376Sgblack@eecs.umich.edu * the skid buffer and the rename instruction queue. 1437376Sgblack@eecs.umich.edu * Note to self: is this really different than issueWidth? 1447376Sgblack@eecs.umich.edu */ 1457376Sgblack@eecs.umich.edu unsigned issueReadWidth; 1467376Sgblack@eecs.umich.edu 1477376Sgblack@eecs.umich.edu /** Width of issue, in instructions. */ 1487376Sgblack@eecs.umich.edu unsigned issueWidth; 1497376Sgblack@eecs.umich.edu 1507376Sgblack@eecs.umich.edu /** Width of execute, in instructions. Might make more sense to break 1517376Sgblack@eecs.umich.edu * down into FP vs int. 1527376Sgblack@eecs.umich.edu */ 1537376Sgblack@eecs.umich.edu unsigned executeWidth; 1547376Sgblack@eecs.umich.edu 1557376Sgblack@eecs.umich.edu /** Number of cycles stage has been squashing. Used so that the stage 1567376Sgblack@eecs.umich.edu * knows when it can start unblocking, which is when the previous stage 1577376Sgblack@eecs.umich.edu * has received the stall signal and clears up its outputs. 1587376Sgblack@eecs.umich.edu */ 1597376Sgblack@eecs.umich.edu unsigned cyclesSquashing; 1607376Sgblack@eecs.umich.edu 1617376Sgblack@eecs.umich.edu //Will implement later 1627376Sgblack@eecs.umich.edu //Load queue interface (probably one and the same) 1637376Sgblack@eecs.umich.edu //Store queue interface 1647376Sgblack@eecs.umich.edu}; 1657376Sgblack@eecs.umich.edu 1667376Sgblack@eecs.umich.edu#endif 1677376Sgblack@eecs.umich.edu