cpu_policy.hh revision 2670:9107b8bd08cd 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_CPU_POLICY_HH__
32#define __CPU_O3_CPU_POLICY_HH__
33
34#include "cpu/o3/bpred_unit.hh"
35#include "cpu/o3/free_list.hh"
36#include "cpu/o3/inst_queue.hh"
37#include "cpu/o3/lsq.hh"
38#include "cpu/o3/lsq_unit.hh"
39#include "cpu/o3/mem_dep_unit.hh"
40#include "cpu/o3/regfile.hh"
41#include "cpu/o3/rename_map.hh"
42#include "cpu/o3/rob.hh"
43#include "cpu/o3/store_set.hh"
44
45#include "cpu/o3/commit.hh"
46#include "cpu/o3/decode.hh"
47#include "cpu/o3/fetch.hh"
48#include "cpu/o3/iew.hh"
49#include "cpu/o3/rename.hh"
50
51#include "cpu/o3/comm.hh"
52
53template<class Impl>
54struct SimpleCPUPolicy
55{
56    typedef TwobitBPredUnit<Impl> BPredUnit;
57    typedef PhysRegFile<Impl> RegFile;
58    typedef SimpleFreeList FreeList;
59    typedef SimpleRenameMap RenameMap;
60    typedef ROB<Impl> ROB;
61    typedef InstructionQueue<Impl> IQ;
62    typedef MemDepUnit<StoreSet, Impl> MemDepUnit;
63    typedef LSQ<Impl> LSQ;
64    typedef LSQUnit<Impl> LSQUnit;
65
66
67    typedef DefaultFetch<Impl> Fetch;
68    typedef DefaultDecode<Impl> Decode;
69    typedef DefaultRename<Impl> Rename;
70    typedef DefaultIEW<Impl> IEW;
71    typedef DefaultCommit<Impl> Commit;
72
73    /** The struct for communication between fetch and decode. */
74    typedef DefaultFetchDefaultDecode<Impl> FetchStruct;
75
76    /** The struct for communication between decode and rename. */
77    typedef DefaultDecodeDefaultRename<Impl> DecodeStruct;
78
79    /** The struct for communication between rename and IEW. */
80    typedef DefaultRenameDefaultIEW<Impl> RenameStruct;
81
82    /** The struct for communication between IEW and commit. */
83    typedef DefaultIEWDefaultCommit<Impl> IEWStruct;
84
85    /** The struct for communication within the IEW stage. */
86    typedef IssueStruct<Impl> IssueStruct;
87
88    /** The struct for all backwards communication. */
89    typedef TimeBufStruct<Impl> TimeStruct;
90
91};
92
93#endif //__CPU_O3_CPU_POLICY_HH__
94